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? 2015 microchip technology inc. ds00001926b-page 1 highlights ? high performance 3-port switch with vlan, qos packet prioritization , rate limiting, igmp monitoring and management functions ? integrated ethernet ph ys with hp auto-mdix ? compliant with energy efficient ethernet 802.3az ? wake on lan (wol) support ? integrated ieee 1588v2 hardware time stamp unit ? cable diagnostic support ? 1.8v to 3.3v variable voltage i/o ? integrated 1.2v regulator for single 3.3v operation target applications ? cable, satellite, an d ip set-top boxes ? digital televisions & video recorders ? voip/video phone systems, home gateways ? test/measurement equipment, industrial automation key benefits ? ethernet switch fabric - 32k buffer ram, 512 entry forwarding table - port based ieee 802.1q vl an support (16 groups) - programmable ieee 802.1q tag insertion/removal - ieee 802.1d spanning tree protocol support - 4 separate transmit queues available per port - fixed or weighted egress priority servicing - qos/cos packet prioritization - input priority determined by vlan tag, da lookup, tos, diffserv or port default value - programmable traffic class map based on input priority on per port basis - remapping of 802.1q priority field on per port basis - programmable rate limiting at the ingress with coloring and random early discard, per port / priority - programmable rate limiting at the egress with leaky bucket algorithm, per port / priority - igmp v1/v2/v3 monitoring for multicast packet filtering - programmable broadcast storm protection with global % control and enable per port - programmable buffer usage limits - dynamic queues on internal memory - programmable filter by mac address ? switch management - port mirroring/monitoring/sni ffing: ingress and/or egress traffic on any port or port pair - fully compliant statistics (mib) gathering counters ?ports - port 0: rmii phy, rmii mac modes - port 1: internal phy - port 2: internal phy - 2 internal 10/100 phys with hp auto-mdix support - fully compliant with ieee 802.3 standards - 10base-t and 100base-tx support - 100base-fx support via exte rnal fiber transceiver - full and half duplex support, full duplex flow control - backpressure (forced collision) half duplex flow control - automatic flow control based on programmable levels - automatic 32-bit crc generation and checking - programmable interframe gap, flow control pause value - auto-negotiation, polarity correction & mdi/mdi-x ? ieee 1588v2 hardware time stamp unit - global 64-bit tunable clock - boundary clock: master / slave, one-step / two-step, end-to-end / peer-to-peer delay - transparent clock with ordinary clock: master / slave, one-step / two-step, end-to-end / peer- to-peer delay - fully programmable timestamp on tx or rx, timestamp on gpio - 64-bit timer comparator event generation (gpio or irq) ? comprehensive power management features - 3 power-down levels - wake on link status change (energy detect) - magic packet wakeup, wake on lan (wol), wake on broadcast, wake on perfect da - wakeup indicator event signal ? power and i/o - integrated power-on reset circuit - latch-up performance exceeds 150ma per eia/jesd78, class ii - jedec class 3a esd performance - single 3.3v power supply (integrated 1.2v regulator) ? additional features - multifunction gpios - ability to use low cost 25mhz crystal for reduced bom ? packaging - pb-free rohs compliant 56-pin qfn ? available in commercial and industrial temp. ranges LAN9354 3-port 10/100 managed ethernet switch with single rmii
LAN9354 ds00001926b-page 2 ? 2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current documentation to obtain the most up-to-date version of this document ation, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2015 microchip technology inc. ds00001926b-page 3 LAN9354 1.0 preface ................................................................................................................... ......................................................................... 4 2.0 general description ....................................................................................................... ................................................................. 8 3.0 pin descriptions and configuration ........................................................................................ ....................................................... 10 4.0 power connections ......................................................................................................... .............................................................. 26 5.0 register map .............................................................................................................. ................................................................... 29 6.0 clocks, resets, and power management ...................................................................................... ............................................... 37 7.0 configuration straps ...................................................................................................... ............................................................... 54 8.0 system interrupts ......................................................................................................... ................................................................. 67 9.0 ethernet phys ............................................................................................................. ................................................................. 77 10.0 switch fabric ............................................................................................................ ................................................................ 182 11.0 i2c slave controller ..................................................................................................... ............................................................. 319 12.0 i2c master eeprom controller ............................................................................................. .................................................. 324 13.0 mii data interfaces ...................................................................................................... .............................................................. 340 14.0 mii management ........................................................................................................... ............................................................ 346 15.0 ieee 1588 ................................................................................................................ ................................................................. 361 16.0 general purpose timer & free-running clock ............................................................................... ......................................... 447 17.0 gpio/led controller ...................................................................................................... .......................................................... 451 18.0 miscellaneous ............................................................................................................ ............................................................... 460 19.0 jtag ..................................................................................................................... .................................................................... 465 20.0 operational charac teristics .............................................................................................. ......................................................... 467 21.0 package outlines ......................................................................................................... ............................................................. 481 22.0 revision history ......................................................................................................... ............................................................... 483
LAN9354 ds00001926b-page 4 ? 2015 microchip technology inc. 1.0 preface 1.1 general terms table 1-1: general terms term description 10base-t 10 mbps ethernet, ieee 802.3 compliant 100base-tx 100 mbps fast ethernet, ieee802.3u compliant adc analog-to-digital converter alr address logic resolution an auto-negotiation blw baseline wander bm buffer manager - part of the switch fabric bpdu bridge protocol data unit - messages which carry the spanning tree protocol informa- tion byte 8 bits csma/cd carrier sense multiple access/collision detect csr control and status registers ctr counter da destination address dword 32 bits epc eeprom controller fcs frame check sequence - the extra checksum characters added to the end of an ethernet frame, used for error detection and correction. fifo first in first out buffer fsm finite state machine gpio general purpose i/o host external system (includes proce ssor, application software, etc.) igmp internet group management protocol inbound refers to data input to the device from the host level-triggered sticky bit this type of status bit is set whenever the c ondition that it represents is asserted. the bit remains set until the condition is no longer true and the status bit is cleared by writ- ing a zero. lsb least significant bit lsb least significant byte lvds low voltage differential signaling mdi medium dependent interface mdix media independent interf ace with crossover mii media independent interface miim media independent interface management mil mac interface layer mld multicast listening discovery mlt-3 multi-level transmission encoding (3-levels). a tri-level encoding method where a change in the logic level represents a code bi t ?1? and the logic output remaining at the same level represent s a code bit ?0?. msb most significant bit msb most significant byte
? 2015 microchip technology inc. ds00001926b-page 5 LAN9354 nrzi non return to zero inverted. this encoding method inverts the signal for a ?1? and leaves the signal unchanged for a ?0? n/a not applicable nc no connect oui organizationally unique identifier outbound refers to data output fr om the device to the host piso parallel in serial out pll phase locked loop ptp precision time protocol reserved refers to a reserved bit field or address. unless otherwise noted, reserved bits must always be zero for write operations. unle ss otherwise noted, va lues are not guaran- teed when reading reserved bits. unless other wise noted, do not read or write to reserved addresses. rtc real-time clock sa source address sfd start of frame delimiter - the 8-bit value indicating the end of the preamble of an ethernet frame. sipo serial in parallel out smi serial management interface sqe signal quality error (also known as ?heartbeat?) ssd start of stream delimiter udp user datagram protocol - a connectionl ess protocol run on top of ip networks uuid universally unique identifier word 16 bits table 1-1: general terms (continued) term description
LAN9354 ds00001926b-page 6 ? 2015 microchip technology inc. 1.2 buffer types table 1-2: buffer types buffer type description is schmitt-triggered input vis variable voltage schmitt-triggered input vo8 variable voltage output with 8 ma sink and 8 ma source vod8 variable voltage open-drain output with 8 ma sink vo12 variable voltage output with 12 ma sink and 12 ma source vod12 variable voltage open-drain output with 12 ma sink vos12 variable voltage open-sour ce output with 12 ma source vo16 variable voltage output with 16 ma sink and 16 ma source pu 50 a (typical) internal pull-up. unless other wise noted in the pin description, internal pull- ups are always enabled. internal pull-up resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled high, an external resistor must be added. pd 50 a (typical) internal pull-down. unless ot herwise noted in the pin description, internal pull-downs are always enabled. internal pull-down resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bidirectional iclk crystal oscillator input pin oclk crystal oscillator output pin ilvpecl low voltage pecl input pin olvpecl low voltage pecl output pin p power pin
? 2015 microchip technology inc. ds00001926b-page 7 LAN9354 1.3 register nomenclature table 1-3: register nomenclature register bit type notation register bit description r read: a register or bit with this attribute can be read. w read: a register or bit with this attribute can be written. ro read only: read only. writes have no effect. wo write only: if a register or bit is write-on ly, reads will return unspecified data. wc write one to clear: writing a one clears the value. writing a zero has no effect wac write anything to clear: writing anything clears the value. rc read to clear: contents is cleared after the read. writes have no effect. ll latch low: clear on read of register. lh latch high: clear on read of register. sc self-clearing: contents are self-cleared after the being set. writes of zero have no effect. contents can be read. ss self-setting: contents are self-setting after bei ng cleared. writes of one have no effect. contents can be read. ro/lh read only, latch high: bits with this attribute will stay high until the bit is read. after it is read, the bit will either remain high if th e high condition remains, or will go low if the high condition has been removed. if the bit has not been read, the bit will remain high regardless of a change to the high condition. this mode is used in some ethernet phy registers. nasr not affected by software reset. the state of nasr bits do not change on assertion of a software reset. reserved reserved field: reserved fields must be written with zeros to ensure future compati- bility. the value of reserved bits is not guaranteed on a read.
LAN9354 ds00001926b-page 8 ? 2015 microchip technology inc. 2.0 general description the LAN9354 is a full featured, 3 port 10/100 managed ethe rnet switch designed for em bedded applications where per- formance, flexibility, ease of integration and system cost control are required. the LAN9354 combines all the functions of a 10/100 switch system, including the switch fabric, packet buffers, buffer manager, media access controllers (macs), phy transceivers, and serial management. ieee 158 8v2 is supported via the integrated ieee 1588v2 hard- ware time stamp unit, which supports end-to-end and peer-to -peer transparent clocks. the LAN9354 complies with the ieee 802.3 (full/half-duplex 10base-t an d 100base-tx) ethernet protocol, ieee 802.3az energy efficient ethernet (eee) (100mbps only), and 802.1d/802.1 q network management protocol specif ications, enabling compatibility with industry standard ethernet and fa st ethernet applications. 100base-fx is sup ported via an external fiber transceiver. at the core of the device is the high performance, high efficiency 3 port ethernet switch fabric. the switch fabric con- tains a 3 port vlan layer 2 switch engine that supports untagged, vlan tagged, and priori ty tagged frames. the switch fabric provides an extensiv e feature set which includes sp anning tree protocol support, multicast packet filtering and quality of service (qos) packet prioritization by vlan tag, destination address, port default value or diffserv/tos, allowing for a range of prioritization implementations. 32k of buffer ram allows for the storage of multiple packets while forwarding operations are completed, and a 512 entry forw arding table provides ample room for mac address forward- ing tables. each port is allocated a cluster of 4 dynamic qos queues which allow each queue size to grow and shrink with traffic, effectively utilizing all available memory. this memory is managed dynamically via the buffer manager block within the switch fabric. all as pects of the switch fabric are managed via the switch fabric co nfiguration and status registers, which are indirect ly accessible via the system co ntrol and stat us registers. the LAN9354 provides 3 switched ports. each port is fully compliant with the ieee 802.3 st andard and all internal macs and phys support full/half duplex 10base-t and 100base-tx operation. the LAN9354 provides 2 on-chip phys, 1 virtual phy and 3 macs. the virtual phy and the third mac are used to connect t he switch fabric to an external mac or phy. in mac mode, the device can be connected to an ex ternal phy via the rmii interface. in phy mode, the device can be connected to an external mac via the rmii interface. all ports support aut omatic or manual full duplex flow con- trol or half duplex backpressure (forced collision) flow contro l. 2k jumbo packet (2048 byte) support allows for oversized packet transfers, effectively increasing throughput while decreasing cpu load. all mac and phy related settings are fully configurable via their respec tive registers within the device. the integrated i 2 c and smi slave controllers allow for full serial management of the devic e via the integrated i 2 c or rmii interface, respectively. the inclusion of these interfaces allows for greater flex ibility in the incorporation of the device into various designs. it is this flexibility which allows the device to operate in 2 differen t modes and under various man- agement conditions. in both mac and phy modes, the device can be smi managed or i 2 c managed. this flexibility in management makes the LAN9354 a candidate for virtually all switch applications. the LAN9354 supports numerous power management and wakeup features. the LAN9354 can be placed in a reduced power mode and can be programmed to issue an external wake signal (irq) via several methods, including ?magic packet?, ?wake on lan?, wake on broadcast, wake on perfect da, and ?link status change?. this signal is ideal for triggering system power-up using remote ethernet wakeup even ts. the device can be removed from the low power state via a host processor command or one of the wake events. the LAN9354 contains an i 2 c master eeprom controller for connection to an optional eeprom. this allows for the storage and retrieval of static data. the internal eeprom l oader can be optionally configured to automatically load stored configuration settings from the eeprom into the device at reset. the i 2 c management slave and master eeprom controller share common pins. in addition to the primary functiona lity described above, the LAN9354 provid es additional features designed for extended functionality. these include a configurable 16-bi t general purpose timer (gpt), a 32-bit 25mhz free running counter, a configurable gpio/led interface, and ieee 1 588 time stamping on all ports and all gpios. the ieee time stamp unit provides a 64-bit tunable clock for accurate ptp timing and a timer comparator to allow time based interrupt generation. the LAN9354 can be configured to operate via a single 3.3v supply utilizing an integrated 3. 3v to 1.2v linear regulator. the linear regulator may be optionally disabled, allowing usa ge of a high efficiency external regulator for lower system power dissipation. the LAN9354 is available in commercial and industrial temperature ranges. figure 2-1 provides an internal block dia- gram of the LAN9354.
? 2015 microchip technology inc. ds00001926b-page 9 LAN9354 figure 2-1: internal block diagram LAN9354 rmii registers virtual phy mac to mac switch registers (csrs) switch fabric dynamic qos 4 queues port 2 10/100 mac w/ 802.3az dynamic qos 4 queues port 1 10/100 mac w/ 802.3az dynamic qos 4 queues port 0 10/100 mac w/ 802.3az switch engine buffer manager search engine frame buffers 1588 transparent clocking ieee 1588v2 time stamp gpio/led controller to optional gpios/leds system interrupt controller irq gp timer free-run clk system clocks/ reset/pme controller external 25mhz crystal ieee 1588v2 clock/events configuration register access mux i 2 c slave i 2 c eeprom configuration 10/100 phy w/fiber w/802.3az registers ethernet eeprom loader smi slave controller pin mux configuration 10/100 phy w/fiber w/802.3az registers ethernet to rmii, smi, i2c
LAN9354 ds00001926b-page 10 ? 2015 microchip technology inc. 3.0 pin descriptions and configuration 3.1 56-qfn pin assignments figure 3-1: 56-qfn pin assignments (top view) note: when a ? # ? is used at the end of the signal name, it indica tes that the signal is active low. for example, rst# indicates that the reset signal is active low. the buffer type for each signal is indicated in the ?b uffer type? column of the pin description tables in sec- tion 3.2, "pin descriptions" . a description of the buffer types is provided in section 1.2, "buffer types" . note: exposed pad (vss ) on bottom of package must be connected to ground with a via field. (connect exposed pad to ground with a via field) vss LAN9354 56-qfn (top view) 4 5 6 7 8 9 10 11 39 38 37 36 35 34 33 32 reg_en vddcr fxlosen fxsda/fxlosa/fxsdena fxsdb/fxlosb/fxsdenb rst# gpio7 gpio6 vddio led1/gpio1/tdi irq p0_mdc vddio p0_duplex i2cscl/eescl/tck led2/gpio2/e2psize 2 3 12 13 31 30 41 40 vdd33 oscvss oscvdd12 osco i2csda/eesda/tms testmode p0_mdio vddcr 1 osci 14 vddio 29 led3/gpio3/eeeen led0/gpio0/tdo/mngt0 42
? 2015 microchip technology inc. ds00001926b-page 11 LAN9354 table 3-1 details the 56-qfn package pin assignments in table format. as shown, select pin functions may change based on the device?s mode of operati on. for modes where a specific pin has no function, the table cell will be marked with ?-?. table 3-1: 56-qfn package pin assignments pin number pin name 1 osci 2 osco 3 oscvdd12 4 oscvss 5 vdd33 6 vddcr 7 reg_en 8 fxlosen 9 fxsda/fxlosa/fxsdena 10 fxsdb/fxlosb/fxsdenb 11 rst# 12 gpio7 13 gpio6 14 vddio 15 led5/gpio5/phyadd 16 led4/gpio4/1588en 17 p0_speed 18 vddio 19 p0_outd1/p0_mode2 20 p0_outd0/p0_mode1 21 p0_outdv 22 vddcr 23 p0_refclk/p0_mode0 24 p0_indv 25 p0_ind0 26 p0_ind1 27 reserved 28 vddio 29 led3/gpio3/eeeen 30 p0_duplex 31 vddio 32 vddcr
LAN9354 ds00001926b-page 12 ? 2015 microchip technology inc. 33 p0_mdc 34 p0_mdio 35 testmode 36 i2csda/eesda/tms 37 i2cscl/eescl/tck 38 irq 39 led2/gpio2/e2psize 40 led1/gpio1/tdi 41 vddio 42 led0/gpio0/tdo/mngt0 43 vdd33txrx1 44 txna 45 txpa 46 rxna 47 rxpa 48 vdd12tx1 49 rbias 50 vdd33bias 51 vdd12tx2 52 rxpb 53 rxnb 54 txpb 55 txnb 56 vdd33txrx2 exposed pad vss table 3-1: 56-qfn package pin assignments (continued) pin number pin name
? 2015 microchip technology inc. ds00001926b-page 13 LAN9354 3.2 pin descriptions this section contains descriptions of the various LAN9354 pins. the pin descriptions have been broken into functional groups as follows: ? lan port a pin descriptions ? lan port b pin descriptions ? lan port a & b power and common pin descriptions ? switch port 0 rmii & configuration strap pin descriptions ? i2c management pin descriptions ? eeprom pin descriptions ? gpio, led & configuration strap pin descriptions ? miscellaneous pin descriptions ? jtag pin descriptions ? core and i/o power pin descriptions table 3-2: lan port a pin descriptions num pins name symbol buffer type description 1 port a tp tx/rx positive channel 1 txpa aio port a twisted pair tran smit/receive positive channel 1. see note 1 port a fx tx positive olvpecl port a fiber tran smit positive. 1 port a tp tx/rx negative channel 1 txna aio port a twisted pair transmit/receive negative channel 1. see note 1 . port a fx tx negative olvpecl port a fiber transmit negative. 1 port a tp tx/rx positive channel 2 rxpa aio port a twisted pair tran smit/receive positive channel 2. see note 1 . port a fx rx positive ai port a fiber receive positive. 1 port a tp tx/rx negative channel 2 rxna aio port a twisted pair transmit/receive negative channel 2. see note 1 . port a fx rx negative ai port a fiber receive negative.
LAN9354 ds00001926b-page 14 ? 2015 microchip technology inc. note 1: in copper mode, either channel 1 or 2 may function as the transmit pair while the other channel functions as the receive pair. the pin name symbols for the twisted pair pins apply to a normal connection. if hp auto- mdix is enabled and a reverse connection is detected or manually selected, the rx and tx pins will be swapped internally. note 2: configuration strap pins are ident ified by an underlined symbol name . configuration strap values are latched on power-on reset or rst# de-assertion. refer to section 7.0, "configuration straps," on page 54 for more in formation. 1 port a fx signal detect (sd) fxsda ilvpecl port a fiber signal detect. when fx-los mode is not selected, this pin functi ons as the signal detect input from the external transceiver. a level above 2 v (typ.) indicates valid signal. when fx-los mode is selected, the input buffer is disabled. port a fx loss of signal (los) fxlosa is (pu) port a fiber loss of signal. when fx-los mode is selected (via fx_los_strap_1 ), this pin functions as the loss of signal input from the external trans- ceiver. a high indicates los while a low indicates valid signal. when fx-los mode is not selected, the input buffer and pull-up are disabled. port a fx-sd enable strap fxsdena ai port a fx-sd enable. when fx-los mode is not selected, this strap input selects between fx-sd and copper twisted pair mode. a level above 1 v (typ.) selects fx-sd. when fx-los mode is selected, the input buffer is disabled. see note 2 . note: port a is connected to the switch fabric port 1. table 3-3: lan port b pin descriptions num pins name symbol buffer type description 1 port b tp tx/rx positive channel 1 txpb aio port b twisted pair tran smit/receive positive channel 1. see note 3 port b fx tx positive olvpecl port b fiber tran smit positive. 1 port b tp tx/rx negative channel 1 txnb aio port b twisted pair transmit/receive negative channel 1. see note 3 . port b fx tx negative olvpecl port b fiber transmit negative. table 3-2: lan port a pin descriptions (continued) num pins name symbol buffer type description
? 2015 microchip technology inc. ds00001926b-page 15 LAN9354 note 3: in copper mode, either channel 1 or 2 may function as the transmit pair while the other channel functions as the receive pair. the pin name symbols for the twisted pair pins apply to a normal connection. if hp auto- mdix is enabled and a reverse connection is detected or manually selected, the rx and tx pins will be swapped internally. note 4: configuration strap pins are ident ified by an underlined symbol name . configuration strap values are latched on power-on reset or rst# de-assertion. refer to section 7.0, "configuration straps," on page 54 for more in formation. 1 port btp tx/rx positive channel 2 rxpb aio port b twisted pair tran smit/receive positive channel 2. see note 3 . port b fx rx positive ai port b fiber receive positive. 1 port b tp tx/rx negative channel 2 rxnb aio port b twisted pair transmit/receive negative channel 2. see note 3 . port b fx rx negative ai port b fiber receive negative. 1 port b fx signal detect (sd) fxsdb ilvpecl port b fiber signal detect. when fx-los mode is not selected, this pin functi ons as the signal detect input from the external transceiver. a level above 2 v (typ.) indicates valid signal. when fx-los mode is selected, the input buffer is disabled. port b fx loss of signal (los) fxlosb is (pu) port b fiber loss of signal. when fx-los mode is selected (via fx_los_strap_2 ), this pin functions as the loss of signal input from the external trans- ceiver. a high indicates los while a low indicates valid signal. when fx-los mode is not selected, the input buffer and pull-up are disabled. port b fx-sd enable strap fxsdenb ai port b fx-sd enable. when fx-los mode is not selected, this strap input selects between fx-sd and copper twisted pair mode. a level above 1 v (typ.) selects fx-sd. when fx-los mode is selected, the input buffer is disabled. see note 4 . note: port b is connected to switch fabric port 2. table 3-3: lan port b pin descriptions (continued) num pins name symbol buffer type description
LAN9354 ds00001926b-page 16 ? 2015 microchip technology inc. note 5: refer to section 4.0, "power connections," on page 26 , the device reference schematics, and the device lancheck schematic checklist for additional connection information. table 3-4: lan port a & b power and common pin descriptions num pins name symbol buffer type description 1 bias reference rbias ai used for internal bias circuits. connect to an exter- nal 12.1 k ? , 1% resistor to ground. refer to the device reference schematic for connec- tion information. note: the nominal voltage is 1.2 v and the resistor will dissipate approximately 1 mw of power. 1 port a and b fx-los enable strap fxlosen ai port a and b fx-los enable. this 3 level strap input selects between fx-los and fx-sd / copper twisted pair mode. a level below 1 v (typ.) selects fx-sd / copper twisted pair for ports a and b, further determined by fxsdena and fxsdenb . a level of 1.5 v selects fx-los for port a and fx- sd / copper twisted pair for port b, further deter- mined by fxsdenb . a level above 2 v (typ.) selects fx-los for ports a and b. 1 +3.3 v port a analog power supply vdd33txrx1 p see note 5 . 1 +3.3 v port b analog power supply vdd33txrx2 p see note 5 . 1 +3.3 v master bias power supply vdd33bias p see note 5 . 1 port a transmitter +1.2 v power supply vdd12tx1 p this pin is supplied from either an external 1.2 v supply or from the device?s internal regulator via the pcb. this pin must be tied to the vdd12tx2 pin for proper operation. see note 5 . 1 port b transmitter +1.2 v power supply vdd12tx2 p this pin is supplied from either an external 1.2 v supply or from the device?s internal regulator via the pcb. this pin must be tied to the vdd12tx1 pin for proper operation. see note 5 .
? 2015 microchip technology inc. ds00001926b-page 17 LAN9354 table 3-5: switch port 0 rmii & configuration strap pin descriptions num pins name symbol buffer type description 1 port 0 rmii input data 1 p0_ind1 vis (pd) rmii mac mode: this pin is the receive data 1 bit from the external phy to the switch. vis (pd) rmii phy mode: this pin is the transmit data 1 bit from the external mac to the switch. the pull-down and input buffer are disabled when the isolate (vphy_iso) bit is set in the port 0 virtual phy basic control register (vphy_basic_ctrl) . 1 port 0 rmii input data 0 p0_ind0 vis (pd) rmii mac mode: this pin is the receive data 0 bit from the external phy to the switch. vis (pd) rmii phy mode: this pin is the transmit data 0 bit from the external mac to the switch. the pull-down and input buffer are disabled when the isolate (vphy_iso) bit is set in the port 0 virtual phy basic control register (vphy_basic_ctrl) . 1 port 0 rmii input data valid p0_indv vis (pd) rmii mac mode: this pin is the crs_dv signal from the external phy. vis (pd) rmii phy mode: this pin is the tx_en signal from the external mac and indicates valid data on p0_ind[1:0] . the pull-down and input buffer are dis- abled when the isolate (vphy_iso) bit is set in the port 0 virtual phy basic control register (vphy_basic_ctrl) . 1 port 0 rmii output data 1 p0_outd1 vo8 rmii mac mode: this pin is the transmit data 1 bit from the switch to the external phy. vo8 rmii phy mode: this pin is the receive data 1 bit from the switch to the ex ternal mac. the output driver is disabled when the isolate (vphy_iso) bit is set in the port 0 virtual phy basic control regis- ter (vphy_basic_ctrl) . port 0 mode[2] configuration strap p0_mode2 vis (pu) note 8 this strap configures the mode for port 0. see note 7 . refer to table 7-3, ?port 0 mode strap mapping,? on page 66 for the port 0 strap settings. 1 port 0 rmii output data 0 p0_outd0 vo8 rmii mac mode: this pin is the transmit data 0 bit from the switch to the external phy. vo8 rmii phy mode: this pin is the receive data 0 bit from the switch to the ex ternal mac. the output driver is disabled when the isolate (vphy_iso) bit is set in the port 0 virtual phy basic control regis- ter (vphy_basic_ctrl) . port 0 mode[1] configuration strap p0_mode1 vis (pu) note 8 this strap configures the mode for port 0. see note 7 . refer to table 7-3, ?port 0 mode strap mapping,? on page 66 for the port 0 strap settings.
LAN9354 ds00001926b-page 18 ? 2015 microchip technology inc. 1 port 0 rmii output data valid p0_outdv vo8 rmii mac mode: this pin is the tx_en signal to the external phy. vo8 rmii phy mode: this pin is the crs_dv signal to the external mac. the output driver is disabled when the isolate (vphy_iso) bit is set in the port 0 virtual phy basic control register (vphy_ba- sic_ctrl) . 1 port 0 speed p0_speed vis (pu) rmii mac mode: this pin can be changed at any time (live value) and is typically tied to the speed indication from the external phy. it can be overrid- den by the speed select lsb (vphy_- speed_sel_lsb) bit in the port 0 virtual phy basic control register (vphy_basic_ctrl) by clearing the auto-negotiation (vphy_an) bit in the same register. the polarity of this pin is determined by the speed_pol_strap_0 . - rmii phy mode: this pin is not used. 1 port 0 rmii duplex p0_duplex vis (pu) rmii mac mode: this pin can be changed at any time (live value) and is typically tied to the duplex indication from the external phy. it can be overrid- den by the duplex mode (vphy_duplex) bit in the port 0 virtual phy basic control register (vphy_basic_ctrl) by clearing the auto-negoti- ation (vphy_an) bit in the same register. the polarity of this pin is determined by the duplex- _pol_strap_0 . - rmii phy mode: this pin is not used. table 3-5: switch port 0 rmii & co nfiguration strap pin descriptions (continued) num pins name symbol buffer type description
? 2015 microchip technology inc. ds00001926b-page 19 LAN9354 1 port 0 rmii reference clock p0_refclk vis/ vo12/ vo16 (pd) note 6 rmii mac mode: this pin is an input or an output running at 50 mhz and is used as the reference clock for the p0_ind[1:0] , p0_indv , p0_outd[1:0] , and p0_outdv pins. the choice of input verses output is based on the setting of the rmii clock direction bit in the port 0 virtual phy special con- trol/status register (vphy_special_con- trol_status) . a low selects p0_outclk as an input and a high selects p0_outclk as an output. as an input, the pull-down is enabled by default. as an output, the input buffer and pull-down are dis- abled. the choice of drive strength is based on the mii virtual phy rmii clock strength bit. a low selects a 12 ma drive, while a high selects a 16 ma drive. vis/ vo12/ vo16 (pd) note 6 rmii phy mode: this pin is an input or an output running at 50 mhz and is used as the reference clock for the p0_ind[1:0] , p0_indv , p0_outd[1:0] , and p0_outdv pins. the choice of input verses output is based on the setting of the rmii clock direction bit in the port 0 virtual phy special con- trol/status register (vphy_special_con- trol_status) . a low selects p0_outclk as an input and a high selects p0_outclk as an output. as an input, the pull-down is normally enabled. the input buffer and pull-down are disabled when the isolate (vphy_iso) bit is set in the port 0 virtual phy basic control regi ster (vphy_basic_ctrl) . as an output, the input buffer and pull-down are dis- abled. the choice of drive strength is based on the mii virtual phy rmii clock strength bit. a low selects a 12 ma drive, while a high selects a 16 ma drive. the output driver is disabled when the isolate (vphy_iso) bit is set in the port 0 virtual phy basic control register (vphy_basic_ctrl) . port 0 mode[0] configuration strap p0_mode0 vis (pu) note 8 this strap configures the mode for port 0. see note 7 . refer to table 7-3, ?port 0 mode strap mapping,? on page 66 for the port 0 strap settings. table 3-5: switch port 0 rmii & co nfiguration strap pin descriptions (continued) num pins name symbol buffer type description
LAN9354 ds00001926b-page 20 ? 2015 microchip technology inc. note 6: a series terminating resistor is recommended for the best pcb signal integrity. note 7: configuration strap pins are ident ified by an underlined symbol name . configuration strap values are latched on power-on reset or rst# de-assertion. refer to section 7.0, "configuration straps," on page 54 for more in formation. note 8: an external supplemental pull-up may be needed, depending upon the input current loading of the external mac/phy device. 1 port 0 smi/mii management data input/output p0_mdio vis/vo8 smi/mii slave management modes: this is the management data to/from an external master and is used to access port 0?s virtual phy, the two physical phys and internal registers. mii master management modes: this is the man- agement data to/from an external phy(s). note: an external pull-up is required when the smi or mii management interface is used, to ensure that the idle state of the mdio signal is a logic one. note: an external pull-up is recommended when the smi or mii management inter- face is not used, to avoid a floating sig- nal. 1 port 0 smi/mii management clock p0_mdc vis smi/mii slave management modes: this is the management clock input from an external master and is used to access port 0?s virtual phy, the two physical phys and internal registers. note: when smi or mii is not used, an external pull-down is recommended to avoid a floating signal. vo8 mii master management modes: this is the man- agement clock output to an external phy(s). table 3-6: i 2 c management pin descriptions num pins name symbol buffer type description 1 i 2 c slave serial data input/output i2csda vis/vod8 this pin is the i 2 c serial data input/output from/to the external master note: this pin must be pulled-up by an exter- nal resistor at all times. 1 i 2 c slave serial clock i2cscl vis this pin is the i 2 c clock input from the external mas- ter. note: these signals are not driven (high impedance) until the eeprom is loaded. table 3-5: switch port 0 rmii & co nfiguration strap pin descriptions (continued) num pins name symbol buffer type description
? 2015 microchip technology inc. ds00001926b-page 21 LAN9354 table 3-7: eeprom pin descriptions num pins name symbol buffer type description 1 eeprom i 2 c serial data input/output eesda vis/vod8 when the device is accessing an external eeprom this pin is the i 2 c serial data input/open-drain out- put. note: this pin must be pulled-up by an exter- nal resistor at all times. 1 eeprom i 2 c serial clock eescl vis/vod8 when the device is accessing an external eeprom this pin is the i 2 c clock input/open-drain output. note: this pin must be pulled-up by an exter- nal resistor at all times. table 3-8: gpio, led & configuration strap pin descriptions num pins name symbol buffer type description 1 general purpose i/o 7 gpio7 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio. the pin is fully programmable as either a push-pull output, an open-drain output or a sc hmitt-triggered input by writing the general purpose i/o configuration reg- ister (gpio_cfg) and the general purpose i/o data & direction register (gpio_data_dir) . 1 general purpose i/o 6 gpio6 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio. the pin is fully programmable as either a push-pull output, an open-drain output or a sc hmitt-triggered input by writing the general purpose i/o configuration reg- ister (gpio_cfg) and the general purpose i/o data & direction register (gpio_data_dir) . 1 led 5 led5 vo12/ vod12/ vos12 this pin is configured to operate as an led when the led 5 enable bit of the led configuration reg- ister (led_cfg) is set. the buffer type depends on the setting of the led function 2-0 (led_fun[2:0]) field in the led configuration register (led_cfg) and is configured to be either a push-pull or open- drain/open-source output. when selected as an open-drain/open-source output, the polarity of this pin depends upon the phyadd strap value sam- pled at reset. note: refer to section 17.3, "led operation," on page 452 to additional information. general purpose i/o 5 gpio5 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio when the led 5 enable bit of the led configuration reg- ister (led_cfg) is clear. the pin is fully program- mable as either a push-pull output, an open-drain output or a schmitt-triggered input by writing the general purpose i/o configuration register (gpi- o_cfg) and the general purpose i/o data & direc- tion register (gpio_data_dir) . phy address configuration strap phyadd vis (pu) this strap configures the default value of the switch phy address select soft-strap. see note 9 .
LAN9354 ds00001926b-page 22 ? 2015 microchip technology inc. 1 led 4 led4 vo12/ vod12/ vos12 this pin is configured to operate as an led when the led 4 enable bit of the led configuration reg- ister (led_cfg) is set. the buffer type depends on the setting of the led function 2-0 (led_fun[2:0]) field in the led configuration register (led_cfg) and is configured to be either a push-pull or open- drain/open-source output. when selected as an open-drain/open-source output, the polarity of this pin depends upon the 1588en strap value sampled at reset. note: refer to section 17.3, "led operation," on page 452 to additional information. general purpose i/o 4 gpio4 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio when the led 4 enable bit of the led configuration reg- ister (led_cfg) is clear. the pin is fully program- mable as either a push-pull output, an open-drain output or a schmitt-triggered input by writing the general purpose i/o configuration register (gpi- o_cfg) and the general purpose i/o data & direc- tion register (gpio_data_dir) . 1588 enable configuration strap 1588en vis (pu) this strap configures th e default value of the 1588 enable soft-strap. see note 9 . 1 led 3 led3 vo12/ vod12/ vos12 this pin is configured to operate as an led when the led 3 enable bit of the led configuration reg- ister (led_cfg) is set. the buffer type depends on the setting of the led function 2-0 (led_fun[2:0]) field in the led configuration register (led_cfg) and is configured to be either a push-pull or open- drain/open-source output. when selected as an open-drain/open-source output, the polarity of this pin depends upon the eeeen strap value sampled at reset. note: refer to section 17.3, "led operation," on page 452 to additional information. general purpose i/o 3 gpio3 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio when the led 3 enable bit of the led configuration reg- ister (led_cfg) is clear. the pin is fully program- mable as either a push-pull output, an open-drain output or a schmitt-triggered input by writing the general purpose i/o configuration register (gpi- o_cfg) and the general purpose i/o data & direc- tion register (gpio_data_dir) . energy efficient ethernet enable configuration strap eeeen vis (pu) this strap configures th e default value of the eee enable 2-1 soft-straps. see note 9 . table 3-8: gpio, led & configuratio n strap pin descriptions (continued) num pins name symbol buffer type description
? 2015 microchip technology inc. ds00001926b-page 23 LAN9354 1 led 2 led2 vo12/ vod12/ vos12 this pin is configured to operate as an led when the led 2 enable bit of the led configuration reg- ister (led_cfg) is set. the buffer type depends on the setting of the led function 2-0 (led_fun[2:0]) field in the led configuration register (led_cfg) and is configured to be either a push-pull or open- drain/open-source output. when selected as an open-drain/open-source output, the polarity of this pin depends upon the e2psize strap value sam- pled at reset. note: refer to section 17.3, "led operation," on page 452 to additional information. general purpose i/o 2 gpio2 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio when the led 2 enable bit of the led configuration reg- ister (led_cfg) is clear. the pin is fully program- mable as either a push-pull output, an open-drain output or a schmitt-triggered input by writing the general purpose i/o configuration register (gpi- o_cfg) and the general purpose i/o data & direc- tion register (gpio_data_dir) . eeprom size configuration strap e2psize vis (pu) this strap configures the value of the eeprom size hard-strap. see note 9 . a low selects 1k bits (128 x 8) through 16k bits (2k x 8). a high selects 32k bits (4k x 8) through 512k bits (64k x 8). 1 led 1 led1 vo12/ vod12/ vos12 this pin is configured to operate as an led when the led 1 enable bit of the led configuration reg- ister (led_cfg) is set. the buffer type depends on the setting of the led function 2-0 (led_fun[2:0]) field in the led configuration register (led_cfg) and is configured to be either a push-pull or open- drain/open-source output. note: refer to section 17.3, "led operation," on page 452 to additional information. general purpose i/o 1 gpio1 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio when the led 1 enable bit of the led configuration register (led_cfg) is clear. the pin is fully programmable as either a push-pull output, an open-drain output or a schmitt-triggered input by writing the general purpose i/o configuration register (gpio_cfg) and the general purpose i/ o data & direction register (gpio_data_dir) . table 3-8: gpio, led & configuration strap pin descriptions (continued) num pins name symbol buffer type description
LAN9354 ds00001926b-page 24 ? 2015 microchip technology inc. note 9: configuration strap pins are ident ified by an underlined symbol name . configuration strap values are latched on power-on reset or rst# de-assertion. refer to section 7.0, "configuration straps," on page 54 for more in formation. 1 led 0 led0 vo12/ vod12/ vos12 this pin is configured to operate as an led when the led 0 enable bit of the led configuration reg- ister (led_cfg) is set. the buffer type depends on the setting of the led function 2-0 (led_fun[2:0]) field in the led configuration register (led_cfg) and is configured to be either a push-pull or open- drain/open-source output. when selected as an open-drain/open-source output, the polarity of this pin depends upon the mngt0 strap value sampled at reset. note: refer to section 17.3, "led operation," on page 452 to additional information. general purpose i/o 0 gpio0 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio when the led 0 enable bit of the led configuration reg- ister (led_cfg) is clear. the pin is fully program- mable as either a push-pull output, an open-drain output or a schmitt-triggered input by writing the general purpose i/o configuration register (gpi- o_cfg) and the general purpose i/o data & direc- tion register (gpio_data_dir) . host interface configuration strap 0 mngt0 vis (pu) this strap configures the value of the serial management mode hard-strap. table 3-9: miscellaneous pin descriptions num pins name symbol buffer type description 1 interrupt output irq vo8/vod8 interrupt request output. the polarity, source and buffer type of this signal is programmable via the interrupt configuration register (irq_cfg) . for more information, refer to section 8.0, "system interrupts," on page 67 . 1 system reset input rst# vis (pu) as an input, this active low signal allows external hardware to reset the device. the device also con- tains an internal power-on reset circuit. thus this signal may be left unconnected if an external hard- ware reset is not needed. when used this signal must adhere to the reset timing requirements as detailed in the section 20.0, "operational character- istics," on page 467 . 1 regulator enable reg_en ai when tied to 3.3 v, the internal 1.2 v regulators are enabled. 1 test mode testmode vis (pd) this pin must be tied to vss for proper operation. 1 crystal input osci iclk external 25 mhz crystal input. this signal can also be driven by a single-ended clock oscillator. when this method is used, osco should be left uncon- nected. table 3-8: gpio, led & configuratio n strap pin descriptions (continued) num pins name symbol buffer type description
? 2015 microchip technology inc. ds00001926b-page 25 LAN9354 note 10: refer to section 4.0, "power connections," on page 26 , the device reference schematic, and the device lancheck schematic checklist for additional connection information. 1 crystal output osco oclk external 25 mhz crystal output. 1 crystal +1.2 v power supply oscvdd12 p supplied by the on-chip regulator unless configured for regulator off mode via reg_en . 1 crystal ground oscvss p crystal ground. 1 reserved reserved - this pin is reserved and must be left unconnected for proper operation. table 3-10: jtag pin descriptions num pins name symbol buffer type description 1 jtag test mux select tms vis jtag test mode select 1 jtag test clock tck vis jtag test clock 1 jtag test data input tdi vis jtag data input 1 jtag test data output tdo vo12 jtag data output table 3-11: core and i/o power pin descriptions num pins name symbol buffer type description 1 regulator +3.3 v power supply vdd33 p +3.3 v power supply for internal regulators. see note 10 . note: +3.3 v must be supplied to this pin even if the internal regulators are disabled. 5 +1.8 v to +3.3 v variable i/o power vddio p +1.8 v to +3.3 v variable i/o power. see note 10 . 3 +1.2 v digital core power supply vddcr p supplied by the on-chip regulator unless configured for regulator off mode via reg_en . 1 f and 470 pf decoupling capacitors in parallel to ground should be used on pin 6. see note 10 . 1 pad ground vss p common ground. this exposed pad must be con- nected to the ground plane with a via array. table 3-9: miscellaneous pin descriptions (continued) num pins name symbol buffer type description
LAN9354 ds00001926b-page 26 ? 2015 microchip technology inc. 4.0 power connections figure 4-1 and figure 4-2 illustrate the device power connections for regulator enabled and disabled cases, respec- tively. refer to the device reference schematic and the de vice lancheck schematic check list for additional information. section 4.1 provides additional information on the devices internal voltage regulators. figure 4-1: power connecti ons - regulators enabled +1.8 v to +3.3 v vddcr core logic & phy digital vdd12tx2 ethernet phy 1 analog 1.0 f 0.1 ? esr vdd33bias vdd33txrx1 vss vddcr ethernet phy 2 analog vdd12tx1 vdd33txrx2 ethernet master bias io pads to phy1 magnetics to phy2 magnetics note: bypass and bulk caps as needed for pcb vddio vdd33 +3.3 v +3.3 v 470 pf crystal oscillator vss pll (exposed pad) (or separate 2.5v) (or separate 2.5v) vddio vddio vddio vddio vddcr oscvdd12 oscvss +3.3 v (in) +1.2 v (out) internal 1.2 v core regulator enable +3.3 v (in) +1.2 v (out) internal 1.2 v oscillator regulator vss enable reg_en (pin 6)
? 2015 microchip technology inc. ds00001926b-page 27 LAN9354 figure 4-2: power connections - regulators disabled +1.8 v to +3.3 v vddcr core logic & phy digital vdd12tx2 ethernet phy 1 analog vdd33bias vdd33txrx1 vss vddcr ethernet phy 2 analog vdd12tx1 vdd33txrx2 ethernet master bias io pads to phy1 magnetics to phy2 magnetics note: bypass and bulk caps as needed for pcb vddio vdd33 +3.3 v +3.3 v crystal oscillator vss pll (exposed pad) (or separate 2.5v) (or separate 2.5v) vddio vddio vddio vddio vddcr oscvdd12 oscvss +3.3 v (in) +1.2 v (out) internal 1.2 v core regulator enable +3.3 v (in) +1.2 v (out) internal 1.2 v oscillator regulator vss enable reg_en +1.2 v (pin 6)
LAN9354 ds00001926b-page 28 ? 2015 microchip technology inc. 4.1 internal voltage regulators the device contains two internal 1.2 v regulators: ? 1.2 v core regulator ? 1.2 v crystal oscillator regulator 4.1.1 1.2 v core regulator the core regulator supplies 1.2 v volts to the main core digital logic, the i/o pads, and the phys? digital logic and can be used to supply the 1.2 v power to the phy analog sections (via an external connection). when the reg_en input pin is connected to 3.3 v, the core regulator is enabled and receives 3.3 v on the vdd33 pin. a 1.0 uf 0.1 ? esr capacitor must be connected to the vddcr pin associated with the regulator. when the reg_en input pin is connected to vss , the core regulator is disabled. however, 3.3 v must still be supplied to the vdd33 pin. the 1.2 v core voltage must then be externally input into the vddcr pins. 4.1.2 1.2 v crystal oscillator regulator the crystal oscillator regulator supplies 1.2 v volts to the crystal oscillator. when the reg_en input pin is connected to 3.3 v, the crystal oscillator regulator is enabled and receives 3.3 v on the vdd33 pin. an external capacitor is not required. when the reg_en input pin is connected to vss , the crystal oscillator regulator is disabled. however, 3.3 v must still be supplied to the vdd33 pin. the 1.2 v crystal oscillator volta ge must then be externally input into the oscvdd12 pin.
? 2015 microchip technology inc. ds00001926b-page 29 LAN9354 5.0 register map this chapter details the device regist er map and summarizes the various dire ctly addressable system control and sta- tus registers (csrs). detailed descriptions of the system cs rs are provided in the chapters corresponding to their function. additional indi rectly addressable registers are available in the vari ous sub-blocks of the device. these regis- ters are also detailed in their corresponding chapters. directly addressable registers ? section 5.1, "system control an d status registers," on page 31 indirectly addressable registers ? section 9.2.20, "physical phy registers," on page 102 ? section 10.7, "switch fabric contro l and status registers," on page 225 figure 5-1 contains an overall base register memory map of t he device. this memory map is not drawn to scale, and should be used for general reference only. table 5-1 provides a summary of all directly addressable csrs and their corresponding addresses. note: register bit type definitions are provided in section 1.3, "register nomenclature," on page 7 . not all device registers are memory mapped or directly addressable. for details on the accessibility of the various device registers, refer the register sub- sections listed above.
LAN9354 ds00001926b-page 30 ? 2015 microchip technology inc. figure 5-1: register address map 000h 100h 2f8h switch csr direct data registers 200h 1588 registers virtual phy 1c0h 1dch 18ch switch fabric indirect access 1ach 1b0h 0a4h 0a8h phy management interface test 0e0h 0fch gpio 1e0h 1e8h 3ffh interrupts 054h 05ch switch fabric flow control 1a0h 1a8h eeprom 1b4h 1b8h gp timer and free run counter 09ch 08ch led configuration 1bch note: not all registers are shown
? 2015 microchip technology inc. ds00001926b-page 31 LAN9354 5.1 system control and status registers the system csrs are directly addressable memory mapped r egisters with a base address offset range of 050h to 2f8h. these registers are accessed through the i 2 c serial interface or the miim/smi se rial interface. for more information on the various device modes and their corresponding address configurations, see section 2.0, "general description," on page 8 . table 5-1 lists the system csrs and their corresponding addresses in order. all system csrs are reset to their default value on the assertion of a chip-level reset. the system csrs can be divided into the following sub-categor ies. each of these sub-categories is located in the cor- responding chapter and contains the s ystem csr descriptions of the associated registers. the register descriptions are categorized as follows: ? section 6.2.3, "reset registers," on page 43 ? section 6.3.5, "power manag ement registers," on page 49 ? section 8.3, "interrupt registers," on page 71 ? section 17.4, "gpio/led registers," on page 454 ? section 12.5, "i2c master eeprom controller registers," on page 336 ? section 15.8, "1588 registers," on page 382 ? section 10.6, "switch fabric inte rface logic registers," on page 210 ? section 14.3.5, "phy management in terface (pmi) registers," on page 352 ? section 9.3.5, "virtual phy registers," on page 167 ? section 18.1, "miscellaneous system conf iguration & status registers," on page 460 note: unlisted registers are reserved for future use. table 5-1: system control and status registers address register name (symbol) 050h chip id and revision (id_rev) 054h interrupt configuration register (irq_cfg) 058h interrupt status register (int_sts) 05ch interrupt enable register (int_en) 064h byte order test re gister (byte_test) 074h hardware configuration register (hw_cfg) 084h power management control register (pmt_ctrl) 08ch general purpose timer config uration register (gpt_cfg) 090h general purpose timer count register (gpt_cnt) 09ch free running 25mhz counter register (free_run) 0a4h phy management interface data register (pmi_data) 0a8h phy management interface access register (pmi_access) 1588 registers 100h 1588 command and control register (1588_cmd_ctl) 104h 1588 general configuration register (1588_general_config) 108h 1588 interrupt status register (1588_int_sts) 10ch 1588 interrupt enable register (1588_int_en) 110h 1588 clock seconds register (1588_clock_sec) 114h 1588 clock nanoseconds register (1588_clock_ns) 118h 1588 clock sub-nanoseconds register (1588_clock_subns) 11ch 1588 clock rate adjustment register (1588_clock_rate_adj) 120h 1588 clock temporary rate adjustment register (1588_clock_temp_rate_adj) 124h 1588 clock temporary rate duration register (1588_clock_temp_rate_duration)
LAN9354 ds00001926b-page 32 ? 2015 microchip technology inc. 128h 1588 clock step adjustment re gister (1588_clock_step_adj) 12ch 1588 clock target x seconds register (1588_clock_target_sec_x) x=a 130h 1588 clock target x nanoseconds register (1588_clock_target_ns_x) x=a 134h 1588 clock target x reload / add seconds re gister (1588_clock_target_reload_sec_x) x=a 138h 1588 clock target x reload / add nanose conds register (1588_clock_target_re- load_ns_x) x=a 13ch 1588 clock target x seconds register (1588_clock_target_sec_x) x=b 140h 1588 clock target x nanoseconds register (1588_clock_target_ns_x) x=b 144h 1588 clock target x reload / add seconds re gister (1588_clock_target_reload_sec_x) x=b 148h 1588 clock target x reload / add nanose conds register (1588_clock_target_re- load_ns_x) x=b 14ch 1588 user mac address high-word register (1588_user_mac_hi) 150h 1588 user mac address low-dwo rd register (1588_user_mac_lo) 154h 1588 bank port gpio select regi ster (1588_bank_port_gpio_sel) 158h 1588 port x latency register (1588_latency_x) 158h 1588 port x rx parsing configurati on register (1588_rx_parse_config_x) 158h 1588 port x tx parsing configuratio n register (1588_tx_parse_config_x) 15ch 1588 port x asymmetry and peer de lay register (1588 _asym_peerdly_x) 15ch 1588 port x rx timestamp configuration register (1588_rx_timestamp_config_x) 15ch 1588 port x tx timestamp configuration register (1588_tx_timestamp_config_x) 15ch 1588 gpio capture configuration register (1588_gpio_cap_config) 160h 1588 port x capture information register (1588_cap_info_x) 160h 1588 port x rx timestamp insertion configur ation register (1588_r x_ts_insert_config_x) 164h 1588 port x rx correction field modification register (1588_rx_cf_mod_x) 164h 1588 port x tx modification register (1588_tx_mod_x) 168h 1588 port x rx filter configuratio n register (1588_rx_filter_config_x) 168h 1588 port x tx modification register 2 (1588_tx_mod2_x) 16ch 1588 port x rx ingress time seco nds register (1588_rx_ingress_sec_x) 16ch 1588 port x tx egress time seconds register (1588_tx_egress_sec_x) 16ch 1588 gpio x rising edge clock seconds capture register (1588_gpio_re_clock_sec_cap_x) 170h 1588 port x rx ingress time nanose conds register (1588_rx_ingress_ns_x) 170h 1588 port x tx egress time nanoseconds register (1588_tx_egress_ns_x) 170h 1588 gpio x rising edge clock nanoseconds capture register (1588_gpio_re_clock_ns_- cap_x) 174h 1588 port x rx message header register (1588_rx_msg_header_x) 174h 1588 port x tx message header register (1588_tx_msg_header_x) 178h 1588 port x rx pdelay_req ingress time seconds register (1588_rx_pdreq_sec_x) 178h 1588 port x tx delay_req egress time seconds register (1588_tx_dreq_sec_x) 178h 1588 gpio x falling edge clock seconds captur e register (1588_gpio_fe_clock_sec_cap_x) 17ch 1588 port x rx pdelay_req ingress time nanoseconds register (1588_rx_pdreq_ns_x) 17ch 1588 port x tx delay_req egress time nanoseconds register (1588_tx_dreq_ns_x) 17ch 1588 gpio x falling edge clock nanoseconds capture register (1588_gpio_fe_clock_ns_- cap_x) 180h 1588 port x rx pdelay_req ingress correction field high register (1588_rx_pdreq_cf_hi_x) table 5-1: system control and st atus registers (continued) address register name (symbol)
? 2015 microchip technology inc. ds00001926b-page 33 LAN9354 180h 1588 tx one-step sync upper seconds register (1588_tx_one_step_sync_sec) 184h 1588 port x rx pdelay_req ingress correction field low register (1588_rx_pdreq_cf_low_x) 188h 1588 port x rx checksum dropped count register (1588_rx_chksum_dropped_cnt_x) 18ch 1588 port x rx filtered count r egister (1588_rx_filtered_cnt_x) switch registers 1a0h port 1 manual flow cont rol register (manual_fc_1) 1a4h port 2 manual flow cont rol register (manual_fc_2) 1a8h port 0 manual flow cont rol register (manual_fc_0) 1ach switch fabric csr interface data register (switch_csr_data) 1b0h switch fabric csr interface co mmand register (switch_csr_cmd) eeprom/led registers 1b4h eeprom command register (e2p_cmd) 1b8h eeprom data register (e2p_data) 1bch led configuration register (led_cfg) virtual phy registers 1c0h virtual phy basic control re gister (vphy_basic_ctrl) 1c4h virtual phy basic status register (vphy_basic_status) 1c8h virtual phy identification msb register (vphy_id_msb) 1cch virtual phy identification lsb register (vphy_id_lsb) 1d0h virtual phy auto-negotiation adve rtisement register (vphy_an_adv) 1d4h virtual phy auto-negotiation link partner base page abilit y register (vphy_an_lp_base_abil- ity) 1d8h virtual phy auto-negotiation ex pansion register (vphy_an_exp) 1dch virtual phy special cont rol/status register (vphy_special_control_status) gpio registers 1e0h general purpose i/o configuration register (gpio_cfg) 1e4h general purpose i/o data & direction register (gpio_data_dir) 1e8h general purpose i/o interrupt status and enable register (gpio_int_sts_en) switch fabric mac address registers 1f0h switch fabric mac address hig h register (switch_mac_addrh) 1f4h switch fabric mac address lo w register (switch_mac_addrl) reset register 1f8h reset control register (reset_ctl) switch fabric csr interface direct data registers 200h-2f8h switch fabric csr interface direct da ta registers (switch_csr_direct_data) table 5-1: system control and st atus registers (continued) address register name (symbol)
LAN9354 ds00001926b-page 34 ? 2015 microchip technology inc. 5.2 special restrictions on back-to-back cycles 5.2.1 back-to-back write-read cycles it is important to note that there are sp ecific restrictions on the timing of back-to -back host write-read operations. these restrictions concern reading re gisters after any write cycle that may affect the register. in all cases there is a delay between writing to a register and the new value becoming available to be read. in other cases, there is a delay between writing to a register and the subseque nt side effect on other registers. in order to prevent the host from reading stale data after a write operation, minimum wait periods have been established. these periods are specified in ta b l e 5 - 2 . the host processor is required to wait t he specified period of time after writing to the indicated register before reading the resource specified in the table. no te that the required wait period is depen- dent upon the register being read after the write. performing ?dummy? reads of the byte order test register (byte_test) register is a convenient way to guarantee that the minimum write-to-read ti ming restriction is met. ta b l e 5 - 2 shows the number of dummy reads that are required before reading the register in dicated. the number of byte_ test reads in this table is based on the minimum cycle timing of 45ns. for microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the tabl e. note that dummy reads of the byte_test register are not required as long as the minimum time period is met. note that depending on the host interface mode in use, th e basic host interface cycle may naturally provide sufficient time between writes and read. it is required of the system design and register access mechanisms to ensure the proper timing. for example, a wr ite and read to the same register may occur fa ster than a write and read to different registers. table 5-2: read after write timing rules after writing... wait for this many nanoseconds... or perform this many reads of byte_test? (assuming t cyc of 45ns) before reading... any register 45 1 the same register or any other register affected by the write interrupt configuration regis- ter (irq_cfg) 60 2 interrupt configuration regis- ter (irq_cfg) interrupt enable register (int_en) 90 2 interrupt configuration regis- ter (irq_cfg) 60 2 interrupt status register (int_sts) interrupt status register (int_sts) 180 4 interrupt configuration regis- ter (irq_cfg) 170 4 interrupt status register (int_sts) power management control register (pmt_ctrl) 165 4 power management control register (pmt_ctrl) 170 4 interrupt configuration regis- ter (irq_cfg) 160 4 interrupt status register (int_sts)
? 2015 microchip technology inc. ds00001926b-page 35 LAN9354 note 11: this timing applies only to the auto-increment and auto-decrement modes of switch fabric csr register access. 5.2.2 back-to-back read cycles there are also restrictions on specific back-to-back host re ad operations. these restrict ions concern reading specific registers after reading a resource that has side effects. in many cases there is a delay between reading the device, and the subsequent indication of the expected change in the control and status register values. in order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been estab- lished. these periods are specified in table 5-3 . the host processor is required to wait the specified period of time between read operations of specific combinations of res ources. the wait period is dependent upon the combination of registers being read. performing ?dummy ? reads of the byte order test register (byte_test) register is a convenient way to guarantee that the minimum wait time restriction is met. table 5-3 below also shows the number of dummy reads that are required for back-to-back read operations. the number of byte_test read s in this table is based on the minimum timing for t cyc (45ns). for microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the table. dummy reads of the byte_t est register are not required as long as the minimum time period is met. note that depending on the host interface mode in use, th e basic host interface cycle may naturally provide sufficient time between reads. it is re quired of the system design and register access mechanisms to ensure the proper timing. for example, multiple reads to the same register may occur faster than reads to different registers. general purpose timer con- figuration register (gpt_cfg) 55 2 general purpose timer con- figuration register (gpt_cfg) 170 4 general purpose timer count register (gpt_cnt) 1588 command and control register (1588_cmd_ctl) 70 2 interrupt configuration regis- ter (irq_cfg) 50 2 interrupt status register (int_sts) 50 2 1588 interrupt status register (1588_int_sts) 1588 interrupt status register (1588_int_sts) 60 2 interrupt configuration regis- ter (irq_cfg) 1588 interrupt enable regis- ter (1588_int_en) 60 2 interrupt configuration regis- ter (irq_cfg) switch fabric csr interface data register (switch_cs- r_data) 50 2 switch fabric csr interface command register (switch_csr_cmd) note 11 general purpose i/o interrupt status and enable register (gpio_int_sts_en) 60 2 interrupt configuration regis- ter (irq_cfg) table 5-2: read after write timing rules (continued) after writing... wait for this many nanoseconds... or perform this many reads of byte_test? (assuming t cyc of 45ns) before reading...
LAN9354 ds00001926b-page 36 ? 2015 microchip technology inc. note 12: this timing applies only to the auto-increment and auto-decrement modes of switch fabric csr register access. table 5-3: read after read timing rules after reading... wait for this many nanoseconds... or perform this many reads of byte_test? (assuming t cyc of 45ns) before reading... switch fabric csr interface data register (switch_cs- r_data) 50 2 switch fabric csr interface command register (switch_csr_cmd) note 12 virtual phy auto-negotiation expansion register (vphy_an_exp) 40 1 virtual phy auto-negotiation expansion register (vphy_an_exp)
? 2015 microchip technology inc. ds00001926b-page 37 LAN9354 6.0 clocks, resets, a nd power management 6.1 clocks the device provides generation of all sys tem clocks as required by the various sub-modules of the device. the clocking sub-system is comprised of the following: ? crystal oscillator ? phy pll 6.1.1 crystal oscillator the device requires a fixed-frequency 25 mhz clock source for use by the internal clock oscillator and pll. this is typ- ically provided by attaching a 25 mhz crystal to the osci and osco pins as specified in section 20.7, "clock circuit," on page 480 . optionally, this clock can be provided by driving the osci input pin with a single-ended 25 mhz clock source. if a single-ended source is sele cted, the clock input must run continuous ly for normal device operation. power savings modes allow for the oscillator or external clock input to be halted. the crystal oscillator can be disabled as describe in section 6.3.4, "chip level power management," on page 47 . for system level verificati on, the crystal oscillator output ca n be enabled onto the irq pin. see section 8.2.9, "clock output test mode," on page 71 . power for the crystal oscillator is provided by a dedicated regulator or separate input pin. see section 4.1.2, "1.2 v crys- tal oscillator regulator," on page 28 . 6.1.2 phy pll the phy module receives the 25 mhz reference clock and, in addition to its internal clock usage, outputs a main system clock that is used to de rive device sub-system clocks. the phy pll can be disabled as describe in section 6.3.4, "chip level power management," on page 47 . the phy pll will be disabled only when requested and if the phy ports are in a power down mode. power for phy pll is provided by an external input pin, us ually sourced by the device?s 1.2v core regulator. see section 4.0, "power connections," on page 26 . note: crystal specifications are provided in table 20-12, ?crystal specifications,? on page 480 .
LAN9354 ds00001926b-page 38 ? 2015 microchip technology inc. 6.2 resets the device provides multiple hardware and software reset s ources, which allow varying levels of the device to be reset. all resets can be categorized into three reset types as described in the following sections: ? chip-level resets - power-on reset (por) - rst# pin reset ? multi-module resets - digital reset (digital_rst) ? single-module resets - port a phy reset - port b phy reset - virtual phy reset - switch reset - 1588 reset the device supports the use of configuratio n straps to allow automatic custom configurations of various device param- eters. these configurati on strap values are set upon de-assertion of all chip-level resets and can be used to easily set the default parameters of the chip at power-on or pin (rst#) reset. refer to section 6.3, "power management," on page 45 for detailed information on the usage of these straps. table 6-1 summarizes the effect of the various reset sources on the device. refer to the following sections for detailed information on each of these reset types. table 6-1: reset sources and affected device functionality module/ functionality por rst# pin digital reset 25 mhz oscillator ( 1 ) voltage regulators ( 2 ) switch fabric xxx switch logic xxx switch registers xxx switch mac 0 xxx switch mac 1 xxx switch mac 2 xxx phy a xx phy b xx phy common ( 3 ) voltage supervision ( 3 ) pll ( 3 ) virtual phy xx 1588 clock / event gen. xxx 1588 timestamp unit 0 xxx 1588 timestamp unit 1 xxx 1588 timestamp unit 2 xxx smi slave controller xxx i2c slave xxx pmi master controller xxx power management xxx device eeprom loader xxx note 1: por is performed by the xtal voltage regulator, not at the system level 2: por is performed internal to the voltage regulators 3: por is performed internal to the phy 4: strap inputs are not re-latched, however soft-straps are retu rned to their previously latched pin defaults before they are potentially updated by the eeprom values. 5: only those output pins that are used for straps
? 2015 microchip technology inc. ds00001926b-page 39 LAN9354 6.2.1 chip-level resets a chip-level reset event activates all internal resets, effectiv ely resetting the entire device. a chip-level reset is initiate d by assertion of any of the following input events: ? power-on reset (por) ? rst# pin reset chip-level reset/configuration completion can be determined by first polling the byte order test register (byte_test) . the returned data will be invalid until the host interface resets are complete. once the returned data is the correct byte ordering value, the host interface resets have completed. the completion of the entire chip-level reset mu st be determined by polling the ready bit of the hardware configura- tion register (hw_cfg) or power management control register (pmt_ctrl) until it is set. when set, the ready bit indicates that the reset has completed and the device is ready to be accessed. with the exception of the hardware configuration register (hw_cfg) , power management control register (pmt_c- trl) , byte order test register (byte_test) , and reset control register (reset_ctl) , read access to any internal resources should not be done by s/w while the ready bit is cl eared. writes to any addre ss are invalid until the ready bit is set. a chip-level reset involves tuning of the variable output le vel pads, latching of configuration straps and generation of the master reset. configuration straps latching during por or rst# pin reset, the latches for the straps are open. following the release of por or rst# pin reset, the latches for the straps are closed. variable level i/o pad tuning following the release of the por or rst# pin resets, a 1 us pulse (active low), is sent into the vo tuning circuit. 2 us later, the output pins are enabled. the 2 us delay allows time for the variable output leve l pins to tune before enabling the outputs and also provides input hold time for strap pins that are s hared with output pins. master reset and clock generation reset following the enabling of the output pins, the rese t is synchronized to the main syst em clock to become the master reset. master reset is used to generate the lo cal resets and to reset the clocks generation. 6.2.1.1 power-on reset (por) a power-on reset occurs whenever power is initially applied to the device or if the power is removed and reapplied to the device. this event resets all circuitry within the dev ice. configuration straps are latched and eeprom loading is performed as a result of this reset. the por is used to tr igger the tuning of the variable level i/o pads as well as a chip-level reset. i2c master xxx gpio/led controller xxx general purpose timer xxx free running counter xxx system csr xxx config. straps latched yes yes no( 4 ) eeprom loader run yes yes yes tristate output pins ( 5 ) yes yes rst# pin driven low table 6-1: reset sources and affected device functionality (continued) module/ functionality por rst# pin digital reset note 1: por is performed by the xtal voltage regulator, not at the system level 2: por is performed internal to the voltage regulators 3: por is performed internal to the phy 4: strap inputs are not re-latched, however soft-straps are retu rned to their previously latched pin defaults before they are potentially updated by the eeprom values. 5: only those output pins that are used for straps
LAN9354 ds00001926b-page 40 ? 2015 microchip technology inc. following valid voltage levels, a por reset typically takes appr oximately 21 ms, plus any additional time (91 us per byte) for data loaded from the eeprom. a full 64kb eeprom load would complete in approximately 6 seconds. 6.2.1.2 rst# pin reset driving the rst# input pin low initiates a chip-level reset. this ev ent resets all circuitry within the device. use of this reset input is optional, but when used, it must be driven for the period of time specified in section 20.6.3, "reset and configuration strap timing," on page 478 . configuration straps are latched, and eeprom loading is performed as a result of this reset. a rst# pin reset typically takes approximately 760 ? s plus any additional time (91 us per byte) for data loaded from the eeprom. a full 64kb eeprom load would co mplete in approximately 6 seconds. please refer to table 3-9, ?miscellaneous pin descriptions,? on page 24 for a description of the rst# pin. 6.2.2 block-level resets the block level resets co ntain an assortment of reset regi ster bit inputs and generate resets for the various blocks. block level resets can affect one or multiple modules. 6.2.2.1 multi-module resets multi-module resets activate multiple internal resets, but do not reset the entire ch ip. configuration straps are not latched upon multi-module resets. a multi-module reset is initiated by assertion of the following: ? digital reset (digital_rst) multi-module reset/configuration completion can be determined by first polling the byte order test register (byte_test) . the returned data will be invalid until the host interface resets are complete. once the returned data is the correct byte ordering value, the ho st interface resets have completed. the completion of the entire chip-level reset mu st be determined by polling the ready bit of the hardware configura- tion register (hw_cfg) or power management control register (pmt_ctrl) until it is set. when set, the ready bit indicates that the reset has completed and the device is ready to be accessed. with the exception of the hardware configuration register (hw_cfg) , power management control register (pmt_c- trl) , byte order test register (byte_test) , and reset control register (reset_ctl) , read access to any internal resources should not be done by s/w while the ready bit is cleared. writes to any address are invalid until the ready bit is set. digital reset (digital_rst) a digital reset is performed by setting the digital_rst bit of the reset control register (reset_ctl) . a digital reset will reset all device sub-modules except the ethernet phys . eeprom loading is performed following this reset. con- figuration straps are not latched as a result of a digital reset. however, soft straps are first returned to their previously latched pin values and register bits that default to strap values are reloaded. a digital reset typically takes approximately 760 ? s plus any additional time (91 us per byte) for data loaded from the eeprom. a full 64kb eeprom load would co mplete in approximately 6 seconds. 6.2.2.2 single-module resets a single-module reset will reset only the specified module. single-module resets do not latch the configuration straps or initiate the eeprom loader. a si ngle-module reset is initiated by assertio n of the following: ? port a phy reset ? port b phy reset ? virtual phy reset note: the rst# pin is pulled-high internally. if unused, this signal can be left unconnected. do not rely on internal pull-up resistors to drive signals external to the device. note: the digital reset does not reset register bits designated as nasr.
? 2015 microchip technology inc. ds00001926b-page 41 LAN9354 ? switch reset ? 1588 reset port a phy reset a port a phy reset is performed by setting the phy_a_rst bit of the reset control regi ster (reset_ctl) or the soft reset bit in the phy x basic control register (phy_basic_control_x) . upon completion of the port a phy reset, the phy_a_rst and soft reset bits are automatically cleared . no other modules of the de vice are affected by this reset. port a phy reset completion can be determined by polling the phy_a_rst bit in the reset control register (reset_ctl) or the soft reset bit in the phy x basic control regist er (phy_basic_control_x) until it clears. under normal conditions, the phy_a_rst and soft reset bit will clear approximately 102 us after the port a phy reset occurrence. in addition to the methods above, the port a phy is autom atically reset after returning from a phy power-down mode. this reset differs in that the phy power-down mode reset does not reload or reset any of the phy registers. refer to section 9.2.10, "phy power-down modes," on page 90 for additional information. refer to section 9.2.13, "resets," on page 95 for additional information on port a phy resets. port b phy reset a port b phy reset is performed by setting the phy_b_rst bit of the reset control regi ster (reset_ctl) or the soft reset bit in the phy x basic control register (phy_basic_control_x) . upon completion of the port b phy reset, the phy_b_rst and soft reset bits are automatically cleared . no other modules of the de vice are affected by this reset. port b phy reset completion can be determined by polling the phy_b_rst bit in the reset control register (reset_ctl) or the soft reset bit in the phy x basic control regist er (phy_basic_control_x) until it clears. under normal conditions, the phy_b_rst and soft reset bit will clear approximately 102 us after the port b phy reset occurrence. in addition to the methods above, the port b phy is autom atically reset after returning from a phy power-down mode. this reset differs in that the phy power-down mode reset does not reload or reset any of the phy registers. refer to section 9.2.10, "phy power-down modes," on page 90 for additional information. refer to section 9.2.13, "resets," on page 95 for additional information on port b phy resets. virtual phy reset a virtual phy reset is performed by setting the virtual phy reset (vphy_rst) bit of the reset control register (reset_ctl) or reset in the virtual phy basic control register (vphy_basic_ctrl) . no other modules of the device are affected by this reset. virtual phy reset completion can be determined by polling the vphy_0_rst bit in the reset control register (reset_ctl) or the reset bit in the virtual phy basic control register (vphy_basic_ctrl) until it clears. under normal conditions, the vphy_0_rst and reset bit will clear a pproximately 1 us after the virtual phy reset occurrence. refer to section 9.3.3, "virtual phy resets," on page 165 for additional information on virtual phy resets. switch reset a reset of the switch fabric, including its macs , is performed by setting the sw_reset bit in the switch reset register (sw_reset) . the bit must then be manually cleared. the registers described in section 10.7, "switch fabric contro l and status registers," on page 225 are reset. the func- tionality described in section 10.5, "switch fabric interface logic," on page 205 and the registers described in section 10.6, "switch fabric interfac e logic registers," on page 210 are not reset. no other modules of the device are affected by this reset. 1588 reset note: when using the soft reset bit to reset the port a ph y, register bits designated as nasr are not reset. note: when using the soft reset bit to reset the port b ph y, register bits designated as nasr are not reset.
LAN9354 ds00001926b-page 42 ? 2015 microchip technology inc. a reset of all 1588 related logic, including the clock/ev ent generation and 1588 tsus, is performed by setting the 1588 reset (1588_reset) bit in the 1588 command and control register (1588_cmd_ctl) . the registers described in section 15.0, "ieee 1588," on page 361 are reset. no other modules of the device are affected by this reset. 1588 reset completion can be determined by polling the 1588 reset (1588_reset) bit in the 1588 command and con- trol register (1588_cmd_ctl) until it clears.
? 2015 microchip technology inc. ds00001926b-page 43 LAN9354 6.2.3 reset registers 6.2.3.1 reset control register (reset_ctl) this register contains software controlled resets. offset: 1f8h size: 32 bits note: this register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. if the host interface is in a reset state, returned data may be invalid. it is not necessary to read all four bytes of this register. dword access rules do not apply to this register. bits description type default 31:7 reserved ro - 6 reserved ro - 5 reserved ro - 4 reserved ro - 3 virtual phy reset (vphy_rst) setting this bit resets the virtual phy. when the virtual phy is released from reset, this bit is automatically cleared. all writes to this bit are ignored while this bit is set. note: this bit is not accessible via the eeprom loader?s register initialization function ( section 12.4.5 ). r/w sc 0b
LAN9354 ds00001926b-page 44 ? 2015 microchip technology inc. 2 port b phy reset (phy_b_rst) setting this bit resets the port b phy. the internal logic automatically holds the phy reset for a minimum of 102us. when the port b phy is released from reset, this bit is automatically cl eared. all writes to this bit are ignored while this bit is set. note: this bit is not accessible via the eeprom loader?s register initialization function ( section 12.4.5 ). r/w sc 0b 1 port a phy reset (phy_a_rst) setting this bit resets the port a phy. the internal logic automatically holds the phy reset for a minimum of 102us. when the port a phy is released from reset, this bit is automatically cl eared. all writes to this bit are ignored while this bit is set. note: this bit is not accessible via the eeprom loader?s register initialization function ( section 12.4.5 ). r/w sc 0b 0 digital reset (digital_rst) setting this bit resets the complete chip except the pll, virtual phy, port b phy and port a phy. all system csrs are reset except for any nasr type bits. any in progress eeprom comman ds (including reload) are termi- nated. the eeprom loader will automatically reload the configuration following this reset, but will not reset the virtual phy, port b phy or port a phy. if desired, the above phy resets can be issued once the device is configured. when the chip is released from reset, this bit is automat ically cleared. all writes to this bit are ignored while this bit is set. note: this bit is not accessible via the eeprom loader?s register initialization function ( section 12.4.5 ). r/w sc 0b bits description type default
? 2015 microchip technology inc. ds00001926b-page 45 LAN9354 6.3 power management the device supports several block and chip level power ma nagement features as well as wake-up event detection and notification. 6.3.1 wake-up event detection 6.3.1.1 phy a & b energy detect energy detect power down mode reduces phy power consum ption. in energy-detect power-down mode, the phy will resume from power-down when energy is seen on the cabl e (typically from link pulses) and set the energyon inter- rupt bit in the phy x interrupt source flags register (phy_interrupt_source_x) . refer to section 9.2.10.2, "energy de tect power-down," on page 90 for details on the operation and configuration of the phy energy-detect power-down mode. if enabled, via the phy x interrupt mask register (phy_interrupt_mask_x) , the phy will generate an interrupt. this interrupt is reflected in the interrupt status register (int_sts) , bit 26 (phy_int_a) for phy a and bit 27 (phy_int_b) for phy b. the int_sts register bits will trig ger the irq interrupt output pi n if enabled, as described in section 8.2.3, "ethernet phy interrupts," on page 69 . the energy-detect phy interrupts will also set the appropriate energy-detect / wol status port a (ed_wol_sts_a) or energy-detect / wol status port b (ed_wol_sts_b) bit of the power management control register (pmt_ctrl) . the energy-detect / wol enable port a (ed_wol_en_a) and energy-detect / wol enable port b (ed_wol_en_b) bits will enable the corresponding status bits as a pme event. 6.3.1.2 phy a & b wake on lan (wol) phy a and b provide wol event detection of perfec t da, broadcast, magic packet, and wakeup frames. when enabled, the phy will detect wol events and set the wol interrupt bit in the phy x interrupt source flags reg- ister (phy_interrupt_source_x) . if enabled via the phy x interrupt mask r egister (phy_inter- rupt_mask_x) , the phy will generate an interrupt. this interrupt is reflected in the interrupt status register (int_sts) , bit 26 (phy_int_a) for phy a and bit 27 (phy_int_b) for phy b. the int_sts re gister bits will trigger the irq interrupt output pin if enabled, as described in section 8.2.3, "ethernet phy interrupts," on page 69 . refer to section 9.2.12, "wake on lan (wol)," on page 91 for details on the operation and configuration of the phy wol. the wol phy interrupts will also set the appropriate energy-detect / wol status port a (ed_wol_sts_a) or energy- detect / wol status port b (ed_wol_sts_b) bit of the power management control register (pmt_ctrl) . the energy-detect / wol enable port a (ed_wol_en_a) and energy-detect / wol enable port b (ed_wol_en_b) bits enable the corresponding status bits as a pme event. 6.3.2 wake-up (pme) notification a simplified diagram of the logic that co ntrols the pme interrupt can be seen in figure 6-1 . the pme module handles the latching of the phy b energy-detect / wol status port b (ed_wol_sts_b) bit and the phy a energy-detect / wol status port a (ed_wol_sts_a) bit in the power management control register (pmt_c- trl) . note: if a carrier is present when energy detect power down is enabled, then detection will occur immediately. note: any phy interrupt will set the above status bits. t he host should only enable the appropriate phy interrupt source in the phy x interrupt mask register (phy_interrupt_mask_x) . note: any phy interrupt will set the above status bits. t he host should only enable the appropriate phy interrupt source in the phy x interrupt mask register (phy_interrupt_mask_x) .
LAN9354 ds00001926b-page 46 ? 2015 microchip technology inc. this module also masks the status bits with the correspondi ng enable bits ( energy-detect / wol enable port b (ed_wol_en_b) and energy-detect / wol enable port a (ed_wol_en_a) ) and combines the results together to generate the power management interrupt event (pme_int) status bit in the interrupt status register (int_sts) . the pme_int status bit is then masked with the power management event interrupt enable (pme_int_en) bit and com- bined with the other interrupt sources to drive the irq output pin. when the pm_wake bit of the power management control register (pmt_ctrl) is set, the pme event will automat- ically wake up the system in certain chip level power modes, as described in section 6.3.4.2, "exiting low power modes," on page 48 . 6.3.3 block level power management the device supports software controlled clock disabling of various modules in order to reduce power consumption. 6.3.3.1 disabling th e switch fabric the entire switch fabric may be disabled by setting the switch_dis bit in the power management control register (pmt_ctrl) . as a safety precaution, in order for this bit to be se t, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. note: the pme interrupt status bit (pme_int) in the in t_sts register is set regardless of the setting of pme_int_en. figure 6-1: pme interrupt signal generation note: disabling individual blocks does not automatically reset t he block, it only places it into a static non-opera- tional state in order to reduce the power consumption of the device. if a block re set is not performed before re-enabling the block, then care must be taken to ensu re that the block is in a state where it can be disabled and then re-enabled. ed_wol_en_a (bit 14) of pmt_ctrl register denotes a level-triggered "sticky" status bit pme_int_en (bit 17) of int_en register pme_int (bit 17) of int_sts register irq_en (bit 8) of irq_cfg register irq other system interrupts ed_wol_sts_a (bit 16) of pmt_ctrl register phys a & b int7_mask (bit 7) of phy_interrupt_mask_a register int7 (bit 7) of phy_interrupt_source_a register polarity & buffer type logic int8_mask (bit 8) of phy_interrupt_mask_a register int8 (bit 8) of phy_interrupt_source_a register ed_wol_en_b (bit 15) of pmt_ctrl register ed_wol_sts_b (bit 17) of pmt_ctrl register int7_mask (bit 7) of phy_interrupt_mask_b register int7 (bit 7) of phy_interrupt_source_b register int8_mask (bit 8) of phy_interrupt_mask_b register int8 (bit 8) of phy_interrupt_source_b register other phy interrupts other phy interrupts pm_wake (bit 28) of pmt_ctrl register pme wake-up
? 2015 microchip technology inc. ds00001926b-page 47 LAN9354 6.3.3.2 disabling the 1588 unit the entire 1588 unit, including the csrs, may be disabled by setting the 1588_dis bit in the power management con- trol register (pmt_ctrl) . as a safety precaution, in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. individual timestamp units, including their local csrs, may be disabled by setting the appropriate 1588_tsu_x_dis bit in the power management control register (pmt_ctrl) . as a safety precaution, in or der for a bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. 6.3.3.3 phy power down a phy may be placed into power-down as described in section 9.2.10, "phy power-down modes," on page 90 . 6.3.3.4 led pins power down all led outputs may be disabled by setting the led_dis bit in the power management control register (pmt_ctrl) . open-drain / open-source leds are un-driven. push-pull leds are still driven but are set to their inactive state. application note: individual leds can be disabled by setting them open-drain gpio outputs with a data value of 1. 6.3.4 chip level power management the device supports power-down modes to allow applications to minimize power consumption. power is reduced by disabling the clocks as outlined in table 6-2, "power management states" . all configuration data is saved when in any power state. register contents are not af fected unless sp ecifically indicated in the register descrip- tion. there is one normal operating power state, d0, and three power saving states: d1, d2 and d3. although appropriate for various wake-up detection functions, the power states do not directly enable and are not enforced by these functions. d0 : normal mode - this is the normal mode of operation of th is device. in this mode, all functionality is available. this mode is entered automatically on any chip-level reset (por, rst# pin reset). d1 : system clocks disabled, xtal, pll a nd network clocks enabled - in this low power mode, all clocks derived from the pll clock are disabled. the network clocks rema in enabled if supplied by the phys or externally. the crystal oscillator and the pll remain enabled. exit fr om this mode may be done manually or automatically. this mode could be used for phy general power down mode, phy wol mode and phy energy detect power down mode. d2 : system clocks disabled, pll disable requested, xtal enabled - in this low power mode, all clocks derived from the pll clock are disabled. the pll is allowed to be disabled (and will disable if both of the phys are in either energy detect or general po wer down). the network clocks remain enabled if supplied by the phys or externally. the crystal oscillator remains enabled. exit from this mode may be done manually or automatically. this mode is useful for phy energy detect power down mode and phy wol mode. this mode could be used for phy general power down mode. d3 : system clocks disabled, pll disabled, xtal disabled - in this low power mode, all clocks derived from the pll clock are disabled. the pll will be disabled. external network clocks are gated off. the crystal oscillator is disabled. exit from this mode may be only be done manually. this mode is useful for phy general power down mode. the host must place the phys into ge neral power down mode by setting the power down (phy_pwr_dwn) bit of the phy x basic control regist er (phy_basic_control_x) before setting this power state. table 6-2: power management states clock source d0 d1 d2 d3 25 mhz crystal oscillator on on on off pll ononoff( 2 )off system clocks (100 mhz, 50 mhz, 25 mhz and others) on off off off network clocks available( 1 ) available( 1 ) available( 1 )off( 3 )
LAN9354 ds00001926b-page 48 ? 2015 microchip technology inc. 6.3.4.1 entering low power modes to enter any of the low power modes (d1 - d3) from normal mode (d0), follow these steps: 1. write the pm_mode and pm_wake fields in the power management control register (pmt_ctrl) to their desired values 2. set the wake-up detection desired per section 6.3.1, "wake-up event detection" . 3. set the appropriate wake-up notification per section 6.3.2, "wake-up (pme) notification" . 4. ensure that the device is in a state where it can safely be placed into a low power mode (all packets transmitted, receivers disabled, packets processed / flushed, etc.) 5. set the pm_sleep_en bit in the power management control register (pmt_ctrl) . note: the eeprom loader register data burst sequence ( section 12.4.5 ) can be used to achieve an initial power down state without the need of software by: ?first setting the phys into general purpose power down by setting the phy_pwr_dwn bi t in phy_basic_ control_1/2 via the pmi_data / pmi_access registers. ?setting the pm_m ode and pm_sleep_en bits in the power management control register (pmt_c- trl) . upon entering any low power mode, the device ready (ready) bit in the hardware configuration register (hw_cfg) and the power management control register (pmt_ctrl) is forced low. 6.3.4.2 exiting low power modes exiting from a low power mode can be done manually or automatically. an automatic wake-up will occur based on the events described in section 6.3.2, "wake-up (pme) notification" . auto- matic wake-up is enabled with the power management wakeup (pm_wake) bit in the power management control register (pmt_ctrl) . a manual wake-up is initiated by the host when: ? an i 2 c cycle (start condition detected) is performed. altho ugh all reads and writes are ignored until the device has been woken, the host should direct the use a read of the byte order test register (byte_test) to wake the device. reads and writes to any other addresses should not be attempted until the device is awake. note: since the i 2 c bus may have multiple slaves, the device will be woken on a cycle to any slave. this is a sys- tem level issue which can be solved with appropriate gating logic. ? an smi cycle ( mdc high and mdio low) is performed. although all reads and writes are ignored until the device has been woken, the host should direct the use a read of the byte order test register (byte_test) to wake the device. reads and writes to any other addresses should not be attempted until the device is awake. note: since the smi bus may have multiple slaves, the device will be woken on a cycle to any slave. this is a system level issue which can be solv ed with appropria te gating logic. to determine when the host interface is functional, the byte order test re gister (byte_test) should be polled. once the correct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) or the power management control register (pmt_ctrl) can be polled to determine when the device is fully awake. note 1: if supplied by the phys or externally 2: pll is requested to be turned off and will disable if both of t he phys are in either energy detect or general power down 3: phy clocks are off, external clocks are gated off note: the pm_mode field cannot be changed at the same time as the pm_sleep_en bit is set and the pm_sleep_en bit cannot be set at the same time that the pm_mode field is changed. note: upon entry into any of the power saving stat es the host interfac es are not functional. table 6-2: power management states clock source d0 d1 d2 d3
? 2015 microchip technology inc. ds00001926b-page 49 LAN9354 for both automatic and manual wake-up, the device ready (ready) bit will go high once the device is returned to power savings state d0 and the pl l has re-stabilized. the pm_mode and pm_sleep_en fields in the power man- agement control register (pmt_ctrl) will also clear at this point. under normal conditions, the device will wake-up within 2 ms. 6.3.5 power management registers 6.3.5.1 power management control register (pmt_ctrl) this read-write register controls the power management feat ures of the device. the ready state of the device be deter- mined via the device ready (ready) bit of this register. offset: 084h size: 32 bits note: this register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. if the host interface is in a reset state, returned data may be invalid. it is not necessary to read all four bytes of this register. dword access rules do not apply to this register. bits description type default 31:29 power management mode (pm_mode) this register field determines the chip level power management mode that will be entered when the power management sleep enable (pm_sleep_en) bit is set. 000: d0 001: d1 010: d2 011: d3 100: reserved 101: reserved 110: reserved 111: reserved writes to this field are ignored if power management sleep enable (pm_sleep_en) is also being written with a 1. this field is cleared when the device wakes up. r/w/sc 000b
LAN9354 ds00001926b-page 50 ? 2015 microchip technology inc. 28 power management sleep enable (pm_sleep_en) setting this bit enters the chip level power management mode specified with the power management mode (pm_mode) field. 0: device is not in a low power sleep state 1: device is in a low power sleep state this bit can not be written at the same time as the pm_mode register field. the pm_mode field must be set, and then this bit must be set for proper device operation. writes to this bit with a value of 1 are ignored if power management mode (pm_mode) is being written with a new value. note: although not prevented by h/w, th is bit should not be written with a value of 1 while power management mode (pm_mode) has a value of ?d0?. this field is cleared when the device wakes up. r/w/sc 0b 27 power management wakeup (pm_wake) when set, this bit enables automatic wake-up based on pme events. 0: manual wakeup only 1: auto wakeup enabled r/w 0b 26 led disable (led_dis) this bit disables led outputs. open-dr ain / open-source leds are un-driven. push-pull leds are still driven but are set to their inactive state. 0: leds are enabled 1: leds are disabled r/w 0b 25 1588 clock disable (1588_dis) this bit disables the clocks for the entire 1588 unit. 0: clocks are enabled 1: clocks are disabled in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. r/w 0b 24 1588 timestamp unit 2 clock disable (1588_tsu_2_dis) this bit disables the clocks for 1588 timestamp unit 2. 0: clocks are enabled 1: clocks are disabled in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. r/w 0b bits description type default
? 2015 microchip technology inc. ds00001926b-page 51 LAN9354 23 1588 timestamp unit 1 clock disable (1588_tsu_1_dis) this bit disables the clocks for 1588 timestamp unit 1. 0: clocks are enabled 1: clocks are disabled in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. r/w 0b 22 1588 timestamp unit 0 clock disable (1588_tsu_0_dis) this bit disables the clocks for 1588 timestamp unit 0. 0: clocks are enabled 1: clocks are disabled in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. r/w 0b 21 reserved ro - 20 switch fabric clock disable (switch_dis) this bit disables the clocks for the switch fabric. 0: clocks are enabled 1: clocks are disabled in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. r/w 0b 19:18 reserved ro - 17 energy-detect / wol status port b (ed_wol_sts_b) this bit indicates an energy detect or wol event occurred on the port b phy. in order to clear this bit, it is required that the event in the phy be cleared as well. the event sources are described in section 6.3, "power management," on page 45 . r/wc 0b 16 energy-detect / wol status port a (ed_wol_sts_a) this bit indicates an energy detect or wol event occurred on the port a phy. in order to clear this bit, it is required that the event in the phy be cleared as well. the event sources are described in section 6.3, "power management," on page 45 . r/wc 0b 15 energy-detect / wol enable port b (ed_wol_en_b) when set, the pme_int bit in the interrupt status register (int_sts) will be asserted upon an energy-detect or wol event from port b. r/w 0b 14 energy-detect / wol enable port a (ed_wol_en_a) when set, the pme_int bit in the interrupt status register (int_sts) will be asserted upon an energy-detect or wol event from port a. r/w 0b 13:10 reserved ro - 9 reserved ro - bits description type default
LAN9354 ds00001926b-page 52 ? 2015 microchip technology inc. 8:7 reserved ro - 6:5 reserved ro - 4 reserved ro - 3:1 reserved ro - 0 device ready (ready) when set, this bit indicates that the device is ready to be accessed. upon power-up, rst# reset, return from power savings states, or digital reset, the host processor may interrogate this fiel d as an indication that the device has stabilized and is fully active. this rising edge of this bit will assert the device ready (ready) bit in int_sts and can cause an interrupt if enabled. note: with the exception of the hw_cfg, pmt_ctrl, byte_test, and reset_ctl registers, read access to any internal resources is forbidden while the ready bit is cleared. writes to any address are invalid until this bit is set. note: this bit is identical to bit 27 of the hardware configuration register (hw_cfg) . ro 0b bits description type default
? 2015 microchip technology inc. ds00001926b-page 53 LAN9354 6.4 device ready operation the device supports a ready status register bit that indicates to the host softwa re when the device is fully ready for operation. this bit may be read via the power management contro l register (pmt_ctrl) or the hardware configura- tion register (hw_cfg) . following power-up reset, rst# reset, or digital reset (see section 6.2, "resets" ), the device ready (ready) bit indi- cates that the device has read, and is c onfigured from, the contents of the eeprom. an eeprom reload command, via the eeprom command register (e2p_cmd) , will restart the eeprom loader, temporarily causing the device ready (ready) to be low. entry into any power savings state (see section 6.3.4, "chip level power management" ) other than d0 will cause device ready (ready) to be low. upon wake-up, the device ready (ready) bit will go high once the device is returned to power savings state d0 and the pll has re-stabilized.
LAN9354 ds00001926b-page 54 ? 2015 microchip technology inc. 7.0 configuration straps configuration straps allow various features of the device to be automatically c onfigured to user defined values. config- uration straps can be organized into two main categories: hard-straps and soft-straps . both hard-straps and soft-straps are latched upon power-on reset (por), or pin reset ( rst# ). the primary difference betwe en these strap types is that soft-strap default values can be overridden by the eeprom loa der, while hard-s traps cannot. configuration straps which have a corresponding external pin include internal resistors in order to prevent the signal from floating when unconnected. if a particular configuratio n strap is connected to a load, an external pull-up or pull- down resistor should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. the internal resistor can also be ov erridden by the addition of an external resistor. 7.1 soft-straps soft-strap values are latched on the release of por or rst# and are overridden by values from the eeprom loader (when an eeprom is present). these straps are used as dire ct configuration values or as defaults for cpu registers. some, but not all, soft-straps have an asso ciated pin. those that do not have an associated pin, have a tie off default value. all soft-strap values can be overridden by the eeprom loader. refer to section 12.4, "eepr om loader," on page 332 for information on the opera tion of the eeprom l oader and the loading of strap values. table 12-4, ?eeprom configuration bits,? on page 334 defines the soft-strap eeprom bit map. straps which have an associated pin are also fully defined in section 3.0, "pin descriptions and configuration," on page 10 . table 7-1 provides a list of all soft-straps and their associated pin or default value. upon setting the digital reset (digital_rst) bit in the reset control register (reset_ctl) or upon issuing a reload command via the eeprom command register (e2p_cmd) , these straps return to their original latched (non- overridden) values if an eeprom is no longer attached or has been erased. the associ ated pins are not re-sampled (i.e. the value latched on the pin during the last por or rst# will be used, not the value on the pin during the digital reset or reload command issuance). if it is desired to re -latch the current configuration strap pin values, a por or rst# must be issued. note: the system designer must guarantee that configuration stra p pins meet the timing requirements specified in section 20.6.3, "reset and configuration strap timing" . if configuration strap pins are not at the correct voltage level prior to being latched, the dev ice may capture incorrect strap values. note: the use of the term ?configures? in the ?description? section of ta b l e 7 - 1 indicates the register bit is loaded with the strap value, while the term ?affects? means the value of the register bit is determined by the strap value and some other condition(s). table 7-1: soft-strap config uration strap definitions strap name description pin / default value led_en_strap[5:0] led enable straps: configures the default value for the led enable 5-0 (led_en[5:0]) bits of the led configuration register (led_cfg) . 111111b led_fun_strap[2:0] led function straps: configures the default value for the led function 2-0 (led_fun[2:0]) bits of the led configuration register (led_cfg) . 000b i2c_addr_override_strap i 2 c address override strap: when set, the i 2 c slave uses the address given by i2c_address_strap[6:0] . 0 i2c_address_strap[6:0] i 2 c address straps: when i2c_addr_override_strap set, the i 2 c slave uses this address. 0001010b
? 2015 microchip technology inc. ds00001926b-page 55 LAN9354 1588_enable_strap 1588 enable strap: configures the default value of the 1588 enable (1588_enable) bit in the 1588 command and con- trol register (1588_cmd_ctl) . note: the defaults of the 1588 register set are such that the device will perform end-to-end transparent clock functionality without further configuration. 1588en auto_mdix_strap_1 phy a auto-mdix enable strap: configures the default value of the amdix_en strap state port a bit of the hardware configuration register (hw_cfg) . this strap is also used in conjunction with manual_mdix- _strap_1 to configure phy a auto-mdix functionality when the auto-mdix control (amdixctrl) bit in the (x=a) phy x special control/status indi cation register (phy_special_- control_stat_ind_x) indicates the strap settings should be used for auto-mdix configuration. note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b manual_mdix_strap_1 phy a manual mdix strap: configures mdi(0) or mdix(1) for phy a when the auto_mdix_strap_1 is low and the auto- mdix control (amdixctrl) bit in the (x=a) phy x special control/status indication register (phy_special_con- trol_stat_ind_x) indicates the strap settings are to be used for auto-mdix configuration. note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 0b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value
LAN9354 ds00001926b-page 56 ? 2015 microchip technology inc. autoneg_strap_1 phy a auto negotiation enable strap: configures the default value of the auto-negotiation enable (phy_an) enable bit in the (x=a) phy x basic control register (phy_basic_control_x) . this strap also affects the default value of the following regis- ter bits (x=a): ? speed select lsb (phy_speed_sel_lsb) and duplex mode (phy_duplex) bits of the phy x basic control register (phy_basic_control_x) ? 10base-t full duplex and 10base-t half duplex bits of the phy x auto-negotiation advertisement register (phy_an_adv_x) ? phy mode (mode[2:0]) bits of the phy x special modes register (phy_special_modes_x) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b speed_strap_1 phy a speed select strap: this strap affects the default value of the following register bits (x=a): ? speed select lsb (phy_speed_sel_lsb) bit of the phy x basic control r egister (phy_basic_con- trol_x) ? 10base-t full duplex and 10base-t half duplex bits of the phy x auto-negotiation advertisement register (phy_an_adv_x) ? phy mode (mode[2:0]) bits of the phy x special modes register (phy_special_modes_x) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b duplex_strap_1 phy a duplex select strap: this strap affects the default value of the following register bits (x=a): ? duplex mode (phy_duplex) bit of the phy x basic control register (p hy_basic_control_x) ? 10base-t full duplex bit of the phy x auto-negotiation advertisement register (phy_an_adv_x) ? phy mode (mode[2:0]) bits of the phy x special modes register (phy_special_modes_x) refer to the respective register definition sections for addi- tional information. 1b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value
? 2015 microchip technology inc. ds00001926b-page 57 LAN9354 bp_en_strap_1 switch port 1 backpressure enable strap: configures the default value for the port 1 backpressure enable (bp_en_1) bit of the port 1 manual flow control register (manual_f- c_1) . refer to the respective register definition sections for addi- tional information. 1b fd_fc_strap_1 switch port 1 full-duplex flow control enable strap: this strap is used to configure the default value of the following register bits: ? port 1 full-duplex transmit flow control enable (tx_f- c_1) and port 1 full-duplex receive flow control enable (rx_fc_1) bits of the port 1 manual flow control regis- ter (manual_fc_1) refer to the respective register definition sections for addi- tional information. 1b fd_fc_strap_1 (cont.) phy a full-duplex flow control enable strap: this strap affects the default value of the following register bits (x=a): ? asymmetric pause bit of the phy x auto-negotiation advertisement register (phy_an_adv_x) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b manual_fc_strap_1 switch port 1 manual flow control enable strap: config- ures the default value of the port 1 full-duplex manual flow control select (manual_fc_1) bit in the port 1 manual flow control register (manual_fc_1) . refer to the respective register definition sections for addi- tional information. 0b manual_fc_strap_1 (cont.) phy a manual flow co ntrol enable strap: this strap affects the default value of the following register bits (x=a): ? asymmetric pause and symmetric pause bit of the phy x auto-negotiation advertisement register (phy_an_adv_x) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 0b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value
LAN9354 ds00001926b-page 58 ? 2015 microchip technology inc. eee_enable_strap_1 switch port 1 energy effici ent ethernet enable strap: configures the default value of the energy efficient ethernet (eee_enable) bit in the (x=1) port x mac transmit configu- ration register (mac_tx_cfg_x) . note: this has no effect when in port 1 internal phy mode when the phy is in 100base-fx mode (lack of eee auto-negotiation results disables eee). refer to the respective register definition sections for addi- tional information. eeeen eee_enable_strap_1 (cont.) phy a energy efficient et hernet enable strap: this strap affects the default value of the following register bits (x=a): ? phy energy efficient et hernet enable (phyeeeen) bit of the phy x edpd nlp / crossover time / eee configu- ration register (phy_edpd_cfg_x) ? 100base-tx eee bit of the phy x eee capability regis- ter (phy_eee_cap_x) ? 100base-tx eee bit of the phy x eee advertisement register (phy_eee_adv_x) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. eeeen auto_mdix_strap_2 phy b auto-mdix enable strap: configures the default value of the amdix_en strap state port b bit of the hardware configuration register (hw_cfg) . this strap is also used in conjunction with manual_mdix- _strap_2 to configure phy b auto-mdix functionality when the auto-mdix control (amdixctrl) bit in the (x=b) phy x special control/status indi cation register (phy_special_- control_stat_ind_x) indicates the strap settings should be used for auto-mdix configuration. note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b manual_mdix_strap_2 phy b manual mdix strap: configures mdi(0) or mdix(1) for port 2 when the auto_mdix_strap_2 is low and the auto- mdix control (amdixctrl) bit in the (x=b) phy x special control/status indication register (phy_special_con- trol_stat_ind_x) indicates the strap settings are to be used for auto-mdix configuration. note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 0b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value
? 2015 microchip technology inc. ds00001926b-page 59 LAN9354 autoneg_strap_2 phy b auto negotiation enable strap: configures the default value of the auto-negotiation enable (phy_an) enable bit in the (x=b) phy x basic control register (phy_basic_control_x) . this strap also affects the default value of the following regis- ter bits (x=b): ? speed select lsb (phy_speed_sel_lsb) and duplex mode (phy_duplex) bits of the phy x basic control register (phy_basic_control_x) ? 10base-t full duplex and 10base-t half duplex bits of the phy x auto-negotiation advertisement register (phy_an_adv_x) ? phy mode (mode[2:0]) bits of the phy x special modes register (phy_special_modes_x) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b speed_strap_2 phy b speed select strap: this strap affects the default value of the following register bits (x=b): ? speed select lsb (phy_speed_sel_lsb) bit of the phy x basic control r egister (phy_basic_con- trol_x) ? 10base-t full duplex and 10base-t half duplex bits of the phy x auto-negotiation advertisement register (phy_an_adv_x) ? phy mode (mode[2:0]) bits of the phy x special modes register (phy_special_modes_x) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b duplex_strap_2 phy b duplex select strap: this strap affects the default value of the following register bits (x=b): ? duplex mode (phy_duplex) bit of the phy x basic control register (p hy_basic_control_x) ? 10base-t full duplex bit of the phy x auto-negotiation advertisement register (phy_an_adv_x) ? phy mode (mode[2:0]) bits of the phy x special modes register (phy_special_modes_x) refer to the respective register definition sections for addi- tional information. 1b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value
LAN9354 ds00001926b-page 60 ? 2015 microchip technology inc. bp_en_strap_2 switch port 2 backpressure enable strap: configures the default value for the port 2 backpressure enable (bp_en_2) bit of the port 2 manual flow control register (manual_f- c_2) . refer to the respective register definition sections for addi- tional information. 1b fd_fc_strap_2 switch port 2 full-duplex flow control enable strap: this strap is used to configure the default value of the following register bits: ? port 2 full-duplex transmit flow control enable (tx_f- c_2) and port 2 full-duplex receive flow control enable (rx_fc_2) bits of the port 2 manual flow control regis- ter (manual_fc_2) . refer to the respective register definition sections for addi- tional information. 1b fd_fc_strap_2 (cont.) phy b full-duplex flow control enable strap: this strap also affects the default value of the following register bits (x=b): ? asymmetric pause bit of the phy x auto-negotiation advertisement register (phy_an_adv_x) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b manual_fc_strap_2 switch port 2 manual flow control enable strap: config- ures the default value of the port 2 full-duplex manual flow control select (manual_fc_2) bit in the port 2 manual flow control register (manual_fc_2) . refer to the respective register definition sections for addi- tional information. 0b manual_fc_strap_2 (cont.) phy b manual flow co ntrol enable strap: this strap affects the default value of the following register bits (x=b): ? asymmetric pause and symmetric pause bits of the phy x auto-negotiation advertisement register (phy_an_adv_x) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 0b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value
? 2015 microchip technology inc. ds00001926b-page 61 LAN9354 eee_enable_strap_2 switch port 2 energy effici ent ethernet enable strap: configures the default value of the energy efficient ethernet (eee_enable) bit in the (x=2) port x mac transmit configu- ration register (mac_tx_cfg_x) . note: this has no effect when the phy is in 100base-fx mode (lack of eee auto-negotiation results disables eee). refer to the respective register definition sections for addi- tional information. eeeen eee_enable_strap_2 (cont.) phy b energy efficient et hernet enable strap: this strap affects the default value of the following register bits (x=b): ? phy energy efficient ethernet enable (phyeeeen) bit of the phy x edpd nlp / crossover time / eee configu- ration register (phy_edpd_cfg_x) ? 100base-tx eee bit of the phy x eee capability regis- ter (phy_eee_cap_x) ? 100base-tx eee bit of the phy x eee advertisement register (phy_eee_adv_x) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. eeeen speed_strap_0 note: speed_strap_0 and speed_pol_strap_0 share the same strap register and eeprom bit. port 0 virtual phy speed select strap: this strap affects the default value of the following bits in the (x=0) virtual phy auto-negotiation link partner base page ability register (vphy_an_lp_base_ability) : ? 100base-x full duplex ? 100base-x half duplex ? 10base-t full duplex ? 10base-t half duplex refer to section 9.3.5.6 and table 9-23 for more information. this strap also configures the speed for port 0 when virtual auto-negotiation fails. refer to section 9.2.6.2, "parallel detection," on page 85 for additional information. refer to the respective register definition sections for addi- tional information. 1b speed_pol_strap_0 note: speed_strap_0 and speed_pol_strap_0 share the same strap register and eeprom bit. switch port 0 speed polarity strap: this strap determines the polarity of the p0_speed when in port 0 rmii mac mode. 0 = p0_speed low means 100mbps, high means 10mbps 1 = p0_speed high means 100mbps, low means 10mbps refer to the respective register definition sections for addi- tional information. 1b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value
LAN9354 ds00001926b-page 62 ? 2015 microchip technology inc. duplex_strap_0 note: duplex_strap_0 and duplex_pol_strap_0 share the same strap register and eeprom bit. port 0 virtual phy duplex select strap: this strap affects the default value of the following bits in the (x=0) virtual phy auto-negotiation link partner base page ability register (vphy_an_lp_base_ability) : ? 100base-x full duplex ? 100base-x half duplex ? 10base-t full duplex ? 10base-t half duplex refer to section 9.3.5.6 and table 9-23 for more information. refer to the respective register definition sections for addi- tional information. 1b duplex_pol_strap_0 note: duplex_strap_0 and duplex_pol_strap_0 share the same strap register and eeprom bit. switch port 0 duplex polarity strap: this strap determines the polarity of the p0_duplex pin when in port 0 mii mac and rmii mac modes. 0 = p0_duplex low means full-duplex 1 = p0_duplex high means full-duplex refer to the respective register definition sections for addi- tional information. 1b bp_en_strap_0 switch port 0 backpressure enable strap: configures the default value of the port 0 backpressure enable (bp_en_0) bit of the port 0 manual flow control register (manual_f- c_0) . refer to the respective register definition sections for addi- tional information. 1b fd_fc_strap_0 switch port 0 full-duplex flow control enable strap : this strap is used to configure the default value of the following register bits: ? port 0 full-duplex transmit flow control enable (tx_f- c_0) and port 0 full-duplex receive flow control enable (rx_fc_0) bits of the port 0 manual flow control regis- ter (manual_fc_0) refer to the respective register definition sections for addi- tional information. 1b fd_fc_strap_0 (cont.) port 0 virtual phy full-duplex flow control enable strap: this strap affects the default value of the following register bits: ? asymmetric pause and pause bits of the virtual phy auto-negotiation link partner base page ability register (vphy_an_lp_base_ability) refer to the respective register definition sections for addi- tional information. 1b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value
? 2015 microchip technology inc. ds00001926b-page 63 LAN9354 7.2 hard-straps hard-straps are latched upon power-on reset (por) or pin reset ( rst# ) only. unlike soft-straps, hard-straps always have an associated pin and can not be overridden by the eeprom loader. these straps are us ed as either direct con- figuration values or as register defaults. table 7-2 provides a list of all hard-stra ps and their associated pin. these straps, along with their pin assignments are also fully defined in section 3.0, "pin descripti ons and configuration," on page 10 . manual_fc_strap_0 port 0 virtual phy manual fl ow control enable strap: this strap affects the default value of the following register bits: ? asymmetric pause and symmetric pause bits of the vir- tual phy auto-negotiation advertisement register (vphy_an_adv) refer to the respective register definition sections for addi- tional information. 0b table 7-2: hard-strap config uration strap definitions strap name description pins eeprom_size_strap eeprom size strap: configures the eeprom size range. a low selects 1k bits (128 x 8) through 16k bits (2k x 8). a high selects 32k bits (4k x 8) through 512k bits (64k x 8). e2psize serial_mngt_mode_strap serial management mode strap: configures the serial management mode. 0 = smi managed mode 1 = i 2 c managed mode refer to section 2.0, "general description," on page 8 for additional information on the various modes of the device. mngt0 table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value
LAN9354 ds00001926b-page 64 ? 2015 microchip technology inc. p0_mode_strap[1:0] switch port 0 mode strap: configures the mode of opera- tion for port 0. 00 = (reserved) 01 = (reserved) 10 = rmii mac mode 11 = rmii phy mode for the LAN9354 these operating modes result from the fol- lowing mapping: note: only rmii is supported. see ta b l e 7 - 3 for the combined port 0 mode strapping. p0_mode2 p0_rmii_clock_dir_strap switch port 0 rmii clock direction strap: configures the default value of the rmii clock direction bit in the (x=0) vir- tual phy special control/status register (vphy_spe- cial_control_status) . 0 = input 1 = output see ta b l e 7 - 3 for the combined port 0 mode strapping. p0_mode1 p0_clock_strength_strap switch port 0 clock strength strap: configures the default value of the rmii clock strength bit in the (x=0) virtual phy special control/status r egister (vphy_special_con- trol_status) 0 = 12ma 1 = 16ma see ta b l e 7 - 3 for the combined port 0 mode strapping. p0_mode0 table 7-2: hard-strap co nfiguration strap definitions (continued) strap name description pins p0_mode[2] p0_mode_strap[1:0] 0 10 (rmii mac) 1 11 (rmii phy)
? 2015 microchip technology inc. ds00001926b-page 65 LAN9354 p1_mode_strap[2:0] switch port 1 mode strap: configures the mode of opera- tion for port 1. 000 = (reserved ) 001 = (reserved ) 010 = (reserved ) 011 = (reserved ) 100 = internal phy the only mode supported is internal phy mode. phy_addr_sel_strap switch phy address select strap: configures the default mii management address values for the phys and virtual phy as detailed in section 9.1.1, "phy addressing," on page 77 . phyadd fx_mode_strap_1 phy a fx mode strap: selects fx mode for phy a. this strap is set high when fxlosen is above 1 v (typ.) or fxsdena is above 1 v (typ.). fxlosen : fxsdena fx_mode_strap_2 phy b fx mode strap: selects fx mode for phy b. this strap is set high when fxlosen is above 2 v (typ.) or fxsdenb is above 1 v (typ.). fxlosen : fxsdenb fx_los_strap_1 phy a fx-los select strap: selects loss of signal mode for phy a. this strap is set high when fxlosen is above 1 v (typ.). fxlosen fx_los_strap_2 phy b fx-los select strap: selects loss of signal mode for phy b. this strap is set high when fxlosen is above 2 v (typ.). fxlosen table 7-2: hard-strap co nfiguration strap definitions (continued) strap name description pins
LAN9354 ds00001926b-page 66 ? 2015 microchip technology inc. note 1: the combined port 0 strap chart is as follows: table 7-3: port 0 mode strap mapping p0_mode2 p0_mode1 p0_mode0 mode 0 0 x rmii mac clock in 0 1 0 rmii mac clock out 12ma 0 1 1 rmii mac clock out 16ma 1 0 x rmii phy clock in 1 1 0 rmii phy clock out 12ma 1 1 1 rmii phy clock out 16ma
? 2015 microchip technology inc. ds00001926b-page 67 LAN9354 8.0 system interrupts 8.1 functional overview this chapter describes the system interrupt structure of the device. the device provides a multi-tier programmable inter- rupt structure which is controlled by the system interrupt controller. the pr ogrammable system interrupts are generated internally by the various device sub-modules and can be config ured to generate a single external host interrupt via the irq interrupt output pin. the programmabl e nature of the host interr upt provides the user with the ability to optimize performance dependent upon the application requirements. the irq interrupt buffer type, polarity and de-assertion interval are modifiable. the irq interrupt can be configured as an open-drain output to facilitate the sharing of interrupts with other devices. all internal interrupts are maskable and capable of triggering the irq interrupt. 8.2 interrupt sources the device is capable of generating the following interrupt types: ? 1588 interrupts ? switch fabric interrupts (buffer manager, switch engine and port 2,1,0 macs) ? ethernet phy interrupts ? gpio interrupts ? power management interrupts ? general purpose timer interrupt (gpt) ? software interrupt (general purpose) ? device ready interrupt ? clock output test mode all interrupts are accessed and configured via registers arra nged into a multi-tier, branch -like structure, as shown in figure 8-1 . at the top level of the devic e interrupt structure are the interrupt status register (int_sts) , interrupt enable register (int_en) and interrupt configuration register (irq_cfg) . the interrupt status register (int_sts) and interrupt enable register (int_en) aggregate and enable/disable all inter- rupts from the various device sub-modules, combining them together to create the irq interrupt. these registers pro- vide direct interrupt access/configuration to the general purpose timer, software and device ready interrupts. these interrupts can be monitored, enabled/disabled and cleared, dire ctly within these two register s. in addition, event indica- tions are provided for the 1588, switch fabric, power m anagement, gpio and ethernet phy interrupts. these inter- rupts differ in that the interrupt sources are generated a nd cleared in other sub-block r egisters. the int_sts register does not provide details on what specific event within the sub-module caused the interrupt and requires the software to poll an additional sub-module interrupt register (as shown in figure 8-1 ) to determine the exact interrupt source and clear it. for interrupts which involve multiple registers, only after the interrupt has been serviced and cleared at its source will it be cleared in the int_sts register. the interrupt configuration register (irq_cfg) is responsible for enabling/disabling the irq interrupt output pin as well as configuring its properties. the irq_ cfg register allows the modification of the irq pin buffer type, polarity and de-assertion interval. the de-assertion timer guarant ees a minimum interrupt de-assertion period for the irq output and is programmable via the interrupt de-assertio n interval (int_deas) field of the interrupt configuration register
LAN9354 ds00001926b-page 68 ? 2015 microchip technology inc. (irq_cfg) . a setting of all zeros disables the de-assertion timer. the de-assertion interval starts when the irq pin de- asserts, regardless of the reason. figure 8-1: functional interrupt hierarchy int_cfg int_sts int_en top level interrupt registers (system csrs) bit 29 (1588_evnt) of int_sts register phy_interrupt_source_b phy_interrupt_mask_b phy b interrupt registers bit 27 (phy_int_b) of int_sts register phy_interrupt_source_a phy_interrupt_mask_a phy a interrupt registers bit 26 (phy_int_a) of int_sts register sw_imr sw_ipr switch fabric interrupt registers bit 28 (switch_int) of int_sts register bm_imr bm_ipr buffer manager interrupt registers bit 6 (bm) of sw_ipr register swe_imr swe_ipr switch engine interrupt registers bit 5 (swe) of sw_ipr register mac_imr_[2,1,0] mac_ipr_[2,1,0] port [2,1,0] mac interrupt registers bits [2,1,0] (mac_[2,1,0]) of sw_ipr register pmt_ctrl power management control register bit 17 (pme_int) of int_sts register gpio_int_sts_en gpio interrupt register bit 12 (gpio) of int_sts register 1588_int_sts 1588_int_en 1588 time stamp interrupt registers
? 2015 microchip technology inc. ds00001926b-page 69 LAN9354 the following sections detail each category of interrupts and their related registers. refer to the corresponding function?s chapter for bit-level definitions of all interrupt registers. 8.2.1 1588 interrupts multiple 1588 time stamp interrupt sources are provided by the device. the top-level 1588 interrupt event (1588_evnt) bit of the interrupt status register (int_sts) provides indication that a 1588 interrupt event occurred in the 1588 interrupt status register (1588_int_sts) . the 1588 interrupt enable register (1588_int_en) provides enabling/disabling of all 1588 interrupt conditions. the 1588 interrupt status register (1588_int_sts) provides the status of all 1588 interrupts. these include tx/rx 1588 clock capture indication on ports 2,1,0, 1588 clock capture fo r gpio events, as well as 1 588 timer interru pt indication. in order for a 1588 interrupt event to trigger the external irq interrupt pin, the desir ed 1588 interrupt event must be enabled in the 1588 interrupt enable register (1588_int_en) , bit 29 (1588_evnt_en) of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the of the interrupt con- figuration register (irq_cfg) . for additional details on the 1588 time stamp interrupts, refer to section 15.0, "ieee 1 588," on page 361 . 8.2.2 switch fabric interrupts multiple switch fabric interrupt sources are provided by t he device in a three-tiered register structure as shown in figure 8-1 . the top-level switch fabric interrupt event (switch_int) bit of the interrupt status register (int_sts) provides indication that a switch fabric interrupt event occurred in the switch global interrupt pending register (sw_ipr) . the switch global interrupt pending register (sw_ipr) and switch global interrupt mask register (sw_imr) provide status and enabling/disabling of all switch fabric sub-modul es interrupts (buffer manager, switch engine and port 2,1,0 macs). the low-level switch fabric sub-module interrupt pending and mask registers of the buffer manager, switch engine and port 2,1,0 macs provide multiple interr upt sources from their respective sub-m odules. these low-level registers provide the following interrupt sources: ? buffer manager ( buffer manager interrupt mask register (bm_imr) and buffer manager interrupt pending reg- ister (bm_ipr) ) - status b pending - status a pending ? switch engine ( switch engine interrupt mask register (swe_imr) and switch engine interrupt pending regis- ter (swe_ipr) ) - interrupt pending ? port 2,1,0 macs ( port x mac interrupt ma sk register (mac_imr_x) and port x mac interrupt pending register (mac_ipr_x) ) - no currently supported interr upt sources. these registers are reserved for future use. in order for a switch fabric interrupt event to trigger the external irq interrupt pin, the following must be configured: ? the desired switch fabric sub-module interrupt even t must be enabled in the corresponding mask register ( buffer manager interrupt mask register (bm_imr) for the buffer manager, switch engine interrupt mask register (swe_imr) for the switch engine and/or port x mac interrupt mask register (mac_imr_x) for the port 2,1,0 macs) ? the desired switch fabric sub-module interrupt event must be enabled in the switch global interrupt mask regis- ter (sw_imr) ?the switch engine interrupt event enable (switch_int_en) bit of the interrupt enable register (int_en) must be set ?the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configuration register (irq_cfg) 8.2.3 ethernet phy interrupts the ethernet phys each provide a set of id entical interrupt sources. the top-level physical phy a interrupt event (phy_int_a) and physical phy b interrupt event (phy_int_b) bits of the interrupt status register (int_sts) provide indication that a phy interrupt event occurred in the phy x interrupt source flags register (phy_interrupt_- source_x) .
LAN9354 ds00001926b-page 70 ? 2015 microchip technology inc. phy interrupts are enabled/disabled via their respective phy x interrupt mask register (phy_interrupt_mask_x) . the source of a phy interrupt can be determined and cleared via the phy x interrupt source flags register (phy_in- terrupt_source_x) . unique interrupts are generated based on the following events: ? energyon activated ? auto-negotiation complete ? remote fault detected ? link down (link status negated) ? link up (link status asserted) ? auto-negotiation lp acknowledge ? parallel detection fault ? auto-negotiation page received ? wake-on-lan event detected in order for an interrupt event to trigger the external irq interrupt pin, the desired phy interrupt event must be enabled in the corresponding phy x interrupt mask register (phy_interrupt_mask_x) , the physical phy a interrupt event enable (phy_int_a_en) and/or physical phy b interrupt event enable (phy_int_b_en) bits of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configuration register (irq_cfg) . for additional details on the ethernet phy interrupts, refer to section 9.2.9, "phy interrupts," on page 87 . 8.2.4 gpio interrupts each gpio of the device is provid ed with its own interrupt. the top-level gpio interrupt event (gpio) bit of the interrupt status register (int_sts) provides indication that a gpio interrupt event occurred in the general purpose i/o interrupt status and enable register (gpio_int_sts_en) . the general purpose i/o interrupt status and enable register (gpi- o_int_sts_en) provides enabling/disabling and status of each gpio interrupt. in order for a gpio interrupt event to trigger the external irq interrupt pin, the desired gpio interrupt must be enabled in the general purpose i/o interrupt status an d enable register (gpio_int_sts_en) , the gpio interrupt event enable (gpio_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configuration register (irq_cfg) . for additional details on the gpio interrupts, refer to section 17.2.1, "gpio interrupts," on page 451 . 8.2.5 power management interrupts multiple power management event interrupt sour ces are provided by the device. the top-level power management interrupt event (pme_int) bit of the interrupt status register (int_sts) provides indication that a power management interrupt event occurred in the power management control register (pmt_ctrl) . the power management control register (pmt_ctrl) provides enabling/disabling and status of all power manage- ment conditions. these include energy- detect on the phys and wake-on-lan (p erfect da, broadcast, wake-up frame or magic packet) detection by phys a&b. in order for a power management interr upt event to trigger the external irq interrupt pin, the desired power manage- ment interrupt event must be enabled in the power management control register (pmt_ctrl) , the power manage- ment event interrupt enable (pme_int_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit 8 of the interrupt configurati on register (irq_cfg) . the power management interrupts are only a portion of the power management features of the device. for additional details on power management, refer to section 6.3, "power management," on page 45 . 8.2.6 general purpo se timer interrupt a gp timer (gpt_int) interrupt is provided in the top-level interrupt status register (int_sts) and interrupt enable register (int_en) . this interrupt is issued when the general purpose timer count register (gpt_cnt) wraps past zero to ffffh and is cleared when the gp timer (gpt_int) bit of the interrupt status register (int_sts) is written with 1. in order for a general purpose timer in terrupt event to trigger the external irq interrupt pin, the gpt must be enabled via the general purpose timer enable (timer_en) bit in the general purpose timer configuration register (gpt_cfg) , the gp timer interrupt enable (gpt_int_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configuration register (irq_cfg) .
? 2015 microchip technology inc. ds00001926b-page 71 LAN9354 for additional details on the general purpose timer, refer to section 16.1, "general purpose timer," on page 447 . 8.2.7 software interrupt a general purpose software interrupt is provided in the top level interrupt status register (int_sts) and interrupt enable register (int_en) . the software interrupt (sw_int) bit of the interrupt status register (int_sts) is generated when the software interrupt enable (sw_int_en) bit of the interrupt enable register (int_en) changes from cleared to set (i.e. on the rising edge of the enable). this interrupt provides an easy way for software to generate an interrupt and is designed for general software usage. in order for a software interrupt event to trigger the external irq interrupt pin, the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configurati on register (irq_cfg) . 8.2.8 device ready interrupt a device ready interrupt is provided in the top-level interrupt status register (int_sts) and interrupt enable register (int_en) . the device ready (ready) bit of the interrupt status register (int_sts) indicates that the device is ready to be accessed after a power-up or reset condition. writing a 1 to this bit in the interrupt status register (int_sts) will clear it. in order for a device ready interrupt event to trigger the external irq interrupt pin, the device ready enable (ready_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configurati on register (irq_cfg) . 8.2.9 clock output test mode in order to facilitate system level debug, the crystal clock can be enabled onto the irq pin by setting the irq clock select (irq_clk_select) bit of the interrupt configuration register (irq_cfg) . the irq pin should be set to a push-pull driver by using the irq buffer type (irq_type) bit for the best result. 8.3 interrupt registers this section details the directly addressable interrupt rela ted system csrs. these register s control, configure and mon- itor the irq interrupt output pin and the various device interrupt sources. for an over view of the entire directly address- able register map, refer to section 5.0, "register map," on page 29 . table 8-1: interrupt registers address register name (symbol) 054h interrupt configuration register (irq_cfg) 058h interrupt status register (int_sts) 05ch interrupt enable register (int_en)
LAN9354 ds00001926b-page 72 ? 2015 microchip technology inc. 8.3.1 interrupt configurat ion register (irq_cfg) this read/write register c onfigures and indicates the state of the irq signal. offset: 054h size: 32 bits bits description type default 31:24 interrupt de-assertion interval (int_deas) this field determines the interrupt reque st de-assertion inte rval in multiples of 10 microseconds. setting this field to zero causes the device to disable the int_deas interval, reset the interval counter and issue any pending interrupts. if a new, non-zero value is written to this field, any subsequent interrupts will obey the new set- ting. r/w 00h 23:15 reserved ro - 14 interrupt de-assertion interval clear (int_deas_clr) writing a 1 to this register clears the de-assertion counter in the interrupt controller, thus causing a new de-assertion interval to begin (regardless of whether or not the interrupt controller is currently in an active de-assertion interval). 0: normal operation 1: clear de-assertion counter r/w sc 0h 13 interrupt de-assertion status (int_deas_sts) when set, this bit indicates that the interrupt controller is currently in a de- assertion interval and potential interrup ts will not be sent to the irq pin. when this bit is clear, the interrupt cont roller is not currently in a de-assertion interval and interrupts will be sent to the irq pin. 0: interrupt controller not in de-assertion interval 1: interrupt controller in de-assertion interval ro 0b 12 master interrupt (irq_int) this read-only bit indicates the state of the internal irq line, regardless of the setting of the irq_en bit, or the stat e of the interrupt de-assertion function. when this bit is set, one of the enabled interrupts is currently active. 0: no enabled interrupts active 1: one or more enabled interrupts active ro 0b 11:9 reserved ro - 8 irq enable (irq_en) this bit controls the final interrupt out put to the irq pin. when clear, the irq output is disabled and permanently de-asserted. this bit has no effect on any internal interrupt status bits. 0: disable output on irq pin 1: enable output on irq pin r/w 0b 7:5 reserved ro -
? 2015 microchip technology inc. ds00001926b-page 73 LAN9354 note 1: register bits designated as nasr are not reset when the digital_rst bit in the reset control register (reset_ctl) is set. 4 irq polarity (irq_pol) when cleared, this bit enables the irq lin e to function as an active low out- put. when set, the irq output is acti ve high. when the irq is configured as an open-drain out put (via the irq_type bit), this bit is ig nored and the inter- rupt is always active low. 0: irq active low output 1: irq active high output r/w nasr note 1 0b 3:2 reserved ro - 1 irq clock select (irq_clk_select) when this bit is set, the crystal clock ma y be output on the irq pin. this is intended to be used for system debug purposes in order to observe the clock and not for any functional purpose. note: when using this bit, the irq pin should be set to a push-pull driver. r/w 0b 0 irq buffer type (irq_type) when this bit is cleared, the irq pin functions as an open-drain output for use in a wired-or interrupt configurati on. when set, the irq is a push-pull driver. note: when configured as an open-drain output, the irq_pol bit is ignored and the interrupt output is always active low. 0: irq pin open-drain output 1: irq pin push-pull driver r/w nasr note 1 0b bits description type default
LAN9354 ds00001926b-page 74 ? 2015 microchip technology inc. 8.3.2 interrupt status register (int_sts) this register contains the current stat us of the generated interrupts. a value of 1 indicates the corresponding interrupt conditions have been met, while a value of 0 indicates the inte rrupt conditions have not been met. the bits of this register reflect the status of the interrupt sour ce regardless of whether the source has been enabled as an interrupt in the inter- rupt enable register (int_en) . where indicated as r/wc, writing a 1 to the corresponding bits acknowledges and clears the interrupt. offset: 058h size: 32 bits bits description type default 31 software interrupt (sw_int) this interrupt is generated when the software interrupt enable (sw_int_en) bit of the interrupt enable register (int_en) is set high. writing a one clears this interrupt. r/wc 0b 30 device ready (ready) this interrupt indicates that the device is ready to be accessed after a power-up or reset condition. r/wc 0b 29 1588 interrupt event (1588_evnt) this bit indicates an interrupt event from the ieee 1588 module. this bit should be used in conjunction with the 1588 interrupt status register (1588_int_sts) to determine the source of the interrupt event within the 1588 module. ro 0b 28 switch fabric interr upt event (switch_int) this bit indicates an inte rrupt event from the switch fabric. this bit should be used in conjunction with the switch global interrupt pending register (sw_ipr) to determine the source of the interrupt event within the switch fabric. ro 0b 27 physical phy b interrupt event (phy_int_b) this bit indicates an interrupt event fr om the physical phy b. the source of the interrupt can be det ermined by polling the phy x interrupt source flags register (phy_interrupt_source_x) . ro 0b 26 physical phy a interrupt event (phy_int_a) this bit indicates an interrupt event fr om the physical phy a. the source of the interrupt can be det ermined by polling the phy x interrupt source flags register (phy_interrupt_source_x) . ro 0b 25:23 reserved ro - 22 reserved ro - 21:20 reserved ro - 19 gp timer (gpt_int) this interrupt is issued when the general purpose timer count register (gpt_cnt) wraps past zero to ffffh. r/wc 0b 18 reserved ro -
? 2015 microchip technology inc. ds00001926b-page 75 LAN9354 17 power management inte rrupt event (pme_int) this interrupt is issued when a power management event is detected as configured in the power management control register (pmt_ctrl) . writ- ing a '1' clears this bit. in order to clear this bit, all unmasked bits in the power management control register (pmt_ctrl) must first be cleared. note: the interrupt de-assertion interval does not apply to the pme interrupt. r/wc 0b 16:13 reserved ro - 12 gpio interrupt event (gpio) this bit indicates an interrupt event from the general purpose i/o. the source of the interrupt can be determined by polling the general purpose i/ o interrupt status and enable register (gpio_int_sts_en) ro 0b 11:3 reserved ro - 2:1 reserved ro - 0 reserved ro - bits description type default
LAN9354 ds00001926b-page 76 ? 2015 microchip technology inc. 8.3.3 interrupt enable register (int_en) this register contains the interrupt enables for the irq output pin. writing 1 to any of the bits enables the corresponding interrupt as a source for irq . bits in the interrupt status register (int_sts) register will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this regi ster (with the exception of soft- ware interrupt enable (sw_int_en) . for descriptions of each interrupt, refer to the interrupt status register (int_sts) bits, which mimic the lay out of this register. offset: 05ch size: 32 bits bits description type default 31 software interrupt enable (sw_int_en) r/w 0b 30 device ready enable (ready_en) r/w 0b 29 1588 interrupt event enable (1588_evnt_en) r/w 0b 28 switch engine interrupt event enable (switch_int_en) r/w 0b 27 physical phy b interrupt event enable (phy_int_b_en) r/w 0b 26 physical phy a interrupt event enable (phy_int_a_en) r/w 0b 25:23 reserved ro - 22 reserved ro - 21:20 reserved ro - 19 gp timer interrupt enable (gpt_int_en) r/w 0b 18 reserved ro - 17 power management event inte rrupt enable (pme_int_en) r/w 0b 16:13 reserved ro - 12 gpio interrupt event enable (gpio_en) r/w 0b 11:3 reserved ro - 2:1 reserved ro - 0 reserved ro -
? 2015 microchip technology inc. ds00001926b-page 77 LAN9354 9.0 ethernet phys 9.1 functional overview the device contains physical phys a and b, and a virtual phy. the a and b physical phys are identical in functionality. physi cal phy a connects to the switch fabric port 1. physical phy b connects to. these phys interface with thei r respective mac via an internal mii interface. the virtual phy provides the vi rtual functionality of a phy and allows connect ion of an external mac to port 0 of the switch fabric as if it was connected to a single port phy. the physical phys comply with the ieee 802.3 physical laye r for twisted pair ethernet and can be configured for full/ half duplex 100 mbps (100base-tx / 1 00base-fx) or 10 mbps (10base-t) etherne t operation. all phy registers fol- low the ieee 802.3 (claus e 22.2.4) specified mii ma nagement register set and are fully configurable. the device ethernet phys are discussed in detail in the following sections: ? section 9.2, "physical phys a & b," on page 77 ? section 9.3, "virtual phy," on page 163 9.1.1 phy addressing each individual phy is assigned a default phy address via the phy_addr_sel_strap configuration strap as shown in table 9-1 . in addition, the addresses for physical phy a and b can be changed via the phy address (phyadd) field in the phy x special modes register (phy_special_modes_x) . for proper operation, the addresses for the virtual phy and physical phys a and b must be unique. no check is perfo rmed to assure each phy is set to a different address. 9.2 physical phys a & b the device integrates two ieee 802.3 phy functions. the phys can be configured for either 100 mbps copper (100base-tx), 100 mbps fiber (100base-fx) or 10 mbps copper (10base-t) ethernet operation and include auto- negotiation and hp auto-mdix. 9.2.1 functional description functionally, each phy can be divided into the following sections: ? 100base-tx transmit and 100base-tx receive ? 10base-t transmit and 10base-t receive ? auto-negotiation ? hp auto-mdix ? phy management control and phy interrupts ? phy power-down modes and energy efficient ethernet ? wake on lan (wol) ? resets table 9-1: default phy serial mii addressing phy_addr_sel_strap virtual phy default address value phy a default address value phy b default address value 0012 1123 note: because the physical phys a and b are functionally iden tical, this section will describe them as the ?phys- ical phy x?, or simply ?phy?. wherever a lowercase ?x? has been appended to a port or signal name, it can be replaced with ?a? or ?b? to indicate the phy a or phy b respectively. in some instances, a ?1? or a ?2? may be appropriate instead. all references to ?phy? in this section can be used interchangeably for both the physical phys a and b.
LAN9354 ds00001926b-page 78 ? 2015 microchip technology inc. ? link integrity test ? cable diagnostics ? loopback operation ? 100base-fx far end fault indication a block diagram of the main components of each phy can be seen in figure 9-1 . 9.2.2 100base-tx transmit the 100base-tx transmit data path is shown in figure 9-2 . shaded blocks are those whic h are internal to the phy. each major block is explained in the following sections. figure 9-1: physical phy block diagram figure 9-2: 100base-tx transmit data path hp auto-mdix txpx/txnx rxpx/rxnx to external port x ethernet pins 10/100 transmitter 10/100 reciever mii mac interface mii mdio auto- negotiation to port x switch fabric mac to mii mux pll phy management control registers from system clocks controller interrupts to system interrupt controller port x mac 100m tx driver mlt-3 converter nrzi converter 4b/5b encoder magnetics cat-5 rj45 100m pll internal mii 25 mhz by 4 bits internal mii transmit clock 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 mlt-3 scrambler and piso 125 mbps serial mii mac interface 25mhz by 4 bits
? 2015 microchip technology inc. ds00001926b-page 79 LAN9354 9.2.2.1 100base-tx transmit data across the internal mii interface for a transmission, the switch fabric ma c drives the transmit data onto the internal mii txd bus and asserts the inter- nal mii txen to indicate valid data. the data is in the form of 4-bit wide 25 mhz data. 9.2.2.2 4b/5b encoder the transmit data passes from the mii block to the 4b/5b enc oder. this block encodes the data from 4-bit nibbles to 5- bit symbols (known as ?code-groups?) according to ta b l e 9 - 2 . each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. the remaining 16 code-groups are either used for control information or are not valid. the first 16 code-groups are referred to by the hexadecimal va lues of their corresponding data nibbles, 0 through f. the remaining code-groups are given letter designations with slashe s on either side. for example, an idle code-group is / i/, a transmit error code-group is /h/, etc. table 9-2: 4b/5b code table code group sym receiver interpreta tion transmitter interpretation 11110 0 0 0000 data 0 0000 data 01001 1 1 0001 1 0001 10100 2 2 0010 2 0010 10101 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 a a 1010 a 1010 10111 b b 1011 b 1011 11010 c c 1100 c 1100 11011 d d 1101 d 1101 11100 e e 1110 e 1110 11101 f f 1111 f 1111 11111 /i/ idle sent after /t/r/ until the mii transmitter enable signal (txen) is received 11000 /j/ first nibble of ssd, translated to ?0101? following idle, else mii receive error (rxer) sent for rising mii transmitter enable signal (txen) 10001 /k/ second nibble of ssd, translated to ?0101? following j, el se mii receive error (rxer) sent for rising mii transmitter enable signal (txen) 01101 /t/ first nibble of esd, causes de-assertion of crs if followed by /r/, else assertion of mii receive error (rxer) sent for falling mii transmitter enable signal (txen)
LAN9354 ds00001926b-page 80 ? 2015 microchip technology inc. 9.2.2.3 scrambler and piso repeated data patterns (especially the idle code-group) ca n have power spectral densities with large narrow-band peaks. scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. this uniform spectral density is requir ed by fcc regulations to prevent excessive emi from being radiated by the physical wiring. the seed for the scrambler is generated from the phy addr ess, ensuring that each phy will have its own scrambler sequence. for more information on phy addressing, refer to section 9.1.1, "phy addressing" . the scrambler also performs the parallel in serial out conversion (piso) of the data. 9.2.2.4 nrzi and mlt-3 encoding the scrambler block passes the 5-bit wide parallel data to t he nrzi converter where it becomes a serial 125mhz nrzi data stream. the nrzi is then encoded to mlt-3. mlt-3 is a tri-level code where a change in the logic level represents a code bit ?1? and the logic output remaining at the same level represents a code bit ?0?. 9.2.2.5 100m transmit driver the mlt-3 data is then passed to the analog transmitter, whic h drives the differential mlt-3 signal on output pins txpx and txnx, to the twisted pair media across a 1:1 ratio isolation transformer. the 10 base-t and 100base-tx signals pass through the same transformer so that common ?magnetics? can be used for both. the transmitter drives into the 100 ? impedance of the cat-5 cable. cable termination and impedance matching require external components. 00111 /r/ second nibble of esd, causes de-asser- tion of crs if following /t/, else assertion of mii receive error (rxer) sent for falling mii transmitter enable signal (txen) 00100 /h/ transmit error symbol sent fo r rising mii transmit error (txer) 00110 /v/ invalid, mii re ceive error (rxer) if during mii receive data valid (rxdv) invalid 11001 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 00000 /p/ sleep, indicates to receiver that the transmitter will be going to lpi sent due to lpi. used to tell receiver before transmitter goes to lpi. also used for refresh cycles during lpi. 00001 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 00010 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 00011 /v/ invalid, mii re ceive error (rxer) if during mii receive data valid (rxdv) invalid 00101 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 01000 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 01100 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 10000 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid table 9-2: 4b/5b code table (continued) code group sym receiver interpreta tion transmitter interpretation
? 2015 microchip technology inc. ds00001926b-page 81 LAN9354 9.2.2.6 100m phase lock loop (pll) the 100m pll locks onto the reference clock and generates the 125 mhz clock used to drive the 125 mhz logic and the 100base-tx transmitter. 9.2.3 100base-tx receive the 100base-tx receive data path is shown in figure 9-3 . shaded blocks are those which are internal to the phy. each major block is explained in the following sections. 9.2.3.1 100m receive input the mlt-3 data from the cable is fed into the phy on inputs rxpx and rxnx via a 1:1 ratio transformer. the adc sam- ples the incoming differential signal at a rate of 125m sa mples per second. using a 64-level quantizer, 6 digital bits are generated to represent each sample. the dsp adjusts the gain of the adc according to the observed signal levels such that the full dynamic range of the adc can be used. 9.2.3.2 equalizer, blw correction and clock/data recovery the 6 bits from the adc are fed into the dsp block. the equalizer in the dsp section compensates for phase and ampli- tude distortion caused by the physical channel consisting of magnetics, connectors, and cat- 5 cable. the equalizer can restore the signal for any good-qua lity cat-5 cable between 1m and 100m. if the dc content of t he signal is such that the low-frequency comp onents fall below the low frequency pole of the iso- lation transformer, then the droop characteristics of the transformer will become significant and baseline wander (blw) on the received signal will result. to prevent corruption of the received data, the phy corrects for blw and can receive the ansi x3.263-1995 fddi tp-pmd defined ?killer packet? with no bit errors. the 100m pll generates multiple phases of the 125mhz clock. a multip lexer, controlled by the timing unit of the dsp, selects the optimum phase for sampling the data. this is used as the received recovered clock. this clock is used to extract the serial data from the received signal. 9.2.3.3 nrzi and mlt-3 decoding the dsp generates the mlt-3 recovered le vels that are fed to the mlt-3 converter. the mlt-3 is then converted to an nrzi data stream. figure 9-3: 100base-tx receive data path port x mac a/d converter mlt-3 converter nrzi converter 4b/5b decoder magnetics cat-5 rj45 100m pll internal mii 25mhz by 4 bits internal mii receive clock 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 6 bit data descrambler and sipo 125 mbps serial dsp: timing recovery, equalizer and blw correction mlt-3 mii mac interface 25mhz by 4 bits
LAN9354 ds00001926b-page 82 ? 2015 microchip technology inc. 9.2.3.4 descrambler the descrambler performs an inverse function to the scrambler in the transmitter and also performs the serial in parallel out (sipo) conversion of the data. during reception of idle (/i/) symbols. the descrambler synchronizes its descram bler key to the incoming stream. once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data. special logic in the descrambler ensures synchronization wi th the remote transceiver by searching for idle symbols within a window of 4000 bytes (40 us). this window ensures that a maximum packet size of 1514 bytes, allowed by the ieee 802.3 standard, can be received wi th no interference. if no idle-symbols are detected within this time-period, receive operation is aborted and the descram bler re-starts the synchronization process. the de-scrambled signal is then aligned into 5-bit code-grou ps by recognizing the /j/k/ st art-of-stream delimiter (ssd) pair at the start of a packet. once the code-word alignment is determined, it is stored and utilized until the next start of frame. 9.2.3.5 5b/4b decoding the 5-bit code-groups are translated into 4-bit data nibble s according to the 4b/5b table. the translated data is pre- sented on the internal mii rxd[3:0] signal li nes. the ssd, /j/k/, is translated to ? 0101 0101? as the first 2 nibbles of the mac preamble. reception of the ssd causes the transceiver to assert the receive data valid signal, indicating that valid data is available on the rxd bus. successive valid code-grou ps are translated to data nibbles. reception of either the end of stream delimiter (esd) consisting of the /t/r/ symbols , or at least two /i/ symbols causes the transceiver to de- assert carrier sense and receive data valid signal. 9.2.3.6 receive data valid signal the internal mii?s receive data valid signal (rxdv) indicates that recovered and decoded nibbles are being presented on the rxd[3:0] outputs synchronous to rxclk. rxdv becom es active after the /j/k/ delimiter has been recognized and rxd is aligned to nibble boundaries. it remains active until either the /t/r/ delimiter is recognized or link test indi- cates failure or sigdet becomes false. rxdv is asserted when the first nibble of translated /j/k/ is ready for trans fer over the media independent interface. 9.2.3.7 receiver errors during a frame, unexpected code-groups are considered re ceive errors. expected code groups are the data set (0 through f), and the /t/r/ (esd) symbol pair. when a receive error occurs, the internal mii?s rxer signal is asserted and arbitrary data is driven onto the inte rnal mii?s rxd[3:0] lines. should an error be detected during the time that the / j/k/ delimiter is being decoded (bad ssd error), rxer is as serted true and the value 11 10b is driven onto the rxd[3:0] lines. note that the internal mii?s data valid signal (rxdv) is not yet assert ed when the bad ssd occurs. 9.2.3.8 100m receive data across the internal mii interface for reception, the 4-bit data nibbles are sent to the mii mac interface block. these data nibbles are clocked to the con- troller at a rate of 25 mhz. rxclk is the output clock for the internal mii bus. it is reco vered from the received data to clock the rxd bus. if there is no received signal, it is derived from the system reference clock. 9.2.4 10base-t transmit the 10base-t transmitter receives 4-bit nibbles from th e internal mii at a rate of 2. 5 mhz and converts them to a 10 mbps serial data stream. the data stream is then mancheste r-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. 10base-t transmissions use the following blocks: ? mii (digital) ? tx 10m (digital) ? 10m transmitter (analog) ? 10m pll (analog) 9.2.4.1 10m transmit data acro ss the internal mii interface for a transmission, the switch fabric mac drives the transm it data onto the internal mii txd bus and asserts the inter- nal mii txen to indicate valid data. the data is in the form of 4-bit wide 2.5 mhz data. note: these symbols are not translated into data.
? 2015 microchip technology inc. ds00001926b-page 83 LAN9354 in half-duplex mode the transceiver loops back the transmitte d data, on the receive path. this does not confuse the mac/controller since the col signal is not asserted during th is time. the transceiver also supports the sqe (heartbeat) signal. 9.2.4.2 manchester encoding the 4-bit wide data is sent to the 10m tx block. the nibbles are converted to a 10mbps serial nrzi data stream. the 10m pll produces a 20mhz clock. this is used to manchester encode the nrz data stream. when no data is being transmitted (internal mii txen is low), the 10m tx driver block outputs normal link pulses (nlps) to maintain commu- nications with the remote link partner. 9.2.4.3 10m transmit drivers the manchester encoded data is sent to the analog tran smitter where it is shaped a nd filtered before being driven out as a differential signal across the txpx and txnx outputs. 9.2.5 10base-t receive the 10base-t receiver gets the manchester-encoded analog si gnal from the cable via the magnetics. it recovers the receive clock from the signal and uses this clock to recover the nrzi data stream. this 10m serial data is converted to 4-bit data nibbles which are passed to the controller across the internal mii at a rate of 2.5mhz. 10base-t reception uses the following blocks: ? filter and squelch (analog) ? 10m pll (analog) ? rx 10m (digital) ? mii (digital) 9.2.5.1 10m receive input and squelch the manchester signal from the cable is fed into the transceiver (on inputs rxpx and rxnx) via 1:1 ratio magnetics. it is first filtered to reduce any out-of -band noise. it then passes through a sq uelch circuit. the squelch is a set of amplitude and timing comparators that norm ally reject differential voltage levels below 300mv and detect and recognize differential voltages above 585mv. 9.2.5.2 manchester decoding the output of the squelch goes to the 10m rx block where it is validated as manchester encoded data. the polarity of the signal is also checked. if the pol arity is reversed (local rxp is connect ed to rxn of the remote partner and vice versa), the condition is identified and corrected . the reversed condition is indicated by the 10base-t polarity state (xpol) bit in phy x special control/status indication register (phy_special_ control_stat_ind_x) . the 10m pll is locked onto the received manche ster signal, from which the 20mhz clock is generated. using this clock, the man- chester encoded data is extracted and converted to a 10mhz nr zi data stream. it is then converted from serial to 4-bit wide parallel data. the rx10m block also detects valid 10 base-t idle signals - normal link puls es (nlps) - to maintain the link. 9.2.5.3 10m receive data across the internal mii interface for reception, the 4-bit data nibbles are sent to the mii ma c interface block. these data nibbles are clocked to the con- troller at a rate of 2.5 mhz. 9.2.5.4 jabber detection jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition, which results in holding the internal mii txen input for a long period. special logic is used to detect the jabber state and abort the transmission to the line, within 45 ms. once txen is deasserted, the logic resets the jabber condition. the jabber detect bit in the phy x basic status regist er (phy_basic_status_x) indicates that a jabber condition was detected.
LAN9354 ds00001926b-page 84 ? 2015 microchip technology inc. 9.2.6 auto-negotiation the purpose of the auto-negotiation func tion is to automatically configure the transceiver to the optimum link parame- ters based on the capabilities of its link partner. auto-nego tiation is a mechanism for exchanging configuration informa- tion between two link-partners and automatically selectin g the highest performance mode of operation supported by both sides. auto-negotiation is fully defined in clause 28 of the ieee 802.3 spec ification and is enabled by setting the auto-negotiation enable (phy_an) of the phy x basic control regist er (phy_basic_control_x) . the advertised capabilities of the phy are stored in the phy x auto-negotiation advert isement register (phy_an_ad- v_x) . the phy contains the ability to advertise 100base-tx and 10base-t in both full or half-duplex modes. besides the connection speed, the phy can advertise remote fault i ndication and symmetric or asymmetric pause flow control as defined in the ieee 802.3 specificati on. the transceiver supports ?next page? capability which is used to negotiate energy efficient ethernet functionality as well as to sup port software controlled pages. many of the default advertised capabilities of the phy are determined via configuration straps as shown in section 9.2.20.5, "p hy x auto-negotiation advertisement register (phy_an_adv_x)," on page 111 . refer to section 7.0, "configuration straps," on page 54 for additional details on how to use the device configuration straps. once auto-negotiation has completed, information about the resolved link and the results of the negotiation process are reflected in the speed indication bits in the phy x special control/status register (phy_special_con- trol_status_x) , as well as the phy x auto-negotiation link partner base page ability register (phy_an_lp_base_ability_x) . the auto-negotiation protocol is a purely physical layer activity and proceeds inde- pendently of the mac controller. the following blocks are activated during an auto-negotiation session: ? auto-negotiation (digital) ? 100m adc (analog) ? 100m pll (analog) ? 100m equalizer/blw/clock recovery (dsp) ? 10m squelch (analog) ? 10m pll (analog) ? 10m transmitter (analog) when enabled, auto-negotiation is started by the occurrence of any of the following events: ? power-on reset (por) ? hardware reset (rst#) ? phy software reset (via reset control register (reset_ctl) , or bit 15 of the phy x basic control register (phy_basic_control_x) ) ? phy power-down reset ( section 9.2.10, "phy power-down modes," on page 90 ) ? phy link status down (bit 2 of the phy x basic status register (phy_basic_status_x) is cleared) ? setting the phy x basic control register (phy_basic_control_x) , bit 9 high (auto-neg restart) ? digital reset (via bit 0 of the reset control register (reset_ctl) ) ? issuing an eeprom loade r reload command ( section 12.4, "eeprom loader," on page 332 ) via eeprom loader run sequence on detection of one of these ev ents, the transceiver begins auto-negotiation by transmitting bursts of fast link pulses (flp). these are bursts of link pulses from the 10m tx driver. they are s haped as normal link pulses and can pass uncorrupted down cat-3 or cat-5 cable. a fast link pulse burst consists of up to 33 pulses. the 17 odd-numbered pulses, which are always present, fram e the flp burst. the 16 even-numbered pu lses, which may be present or absent, contain the data word being transmitted. presence of a dat a pulse represents a ?1?, while absence represents a ?0?. the data transmitted by an flp burst is known as a ?link code word.? these are defined fully in ieee 802.3 clause 28. in summary, the transceiver advertises 802.3 compliance in its selector field (the first 5 bits of the link code word). it advertises its technology ability according to the bits set in the phy x auto-negotiation advertisement register (phy_an_adv_x) . note: auto-negotiation is not used for 100base-fx mode. note: refer to section 6.2, "resets," on page 38 for information on these and other system resets.
? 2015 microchip technology inc. ds00001926b-page 85 LAN9354 there are 4 possible matches of the technology abilities. in the order of priority these are: ? 100m full duplex (highest priority) ? 100m half duplex ? 10m full duplex ? 10m half duplex (lowest priority) if the full capabilities of the transceiver are advertised (100m, full-duplex), and if the link partner is capable of 10m and 100m, then auto-negotiation selects 100m as the highest pe rformance mode. if the link partner is capable of half and full-duplex modes, then auto-negotiation sele cts full-duplex as the highest performance mode. once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any dif- ference in the main content of the link code words at this time will caus e auto-negotiation to re-start. auto-negotiation will also re-start if not all of the required flp bursts are received. writing the phy x auto-negotiation advertisement register (phy_an_adv_x) bits [8:5] allows software control of the capabilities advertised by the transceiver. writing the phy x auto-negotiation advertisement register (phy_an_ad- v_x) does not automatically re-start auto-negotiation. the restart auto-negotiation (phy_rst_an) bit of the phy x basic control register (phy_basic_control_x) must be set before the new abilities will be advertised. auto-nego- tiation can also be disabled via software by clearing the auto-negotiation enable (phy_an) bit of the phy x basic con- trol register (phy_basic_control_x) . 9.2.6.1 pause flow control the switch fabric macs are capable of generat ing and receiving pause flow control frames pe r the ieee 802.3 speci- fication. the phy?s advertised pause flow control abilities are set via the asymmetric pause and symmetric pause bits of the phy x auto-negotiation advertisement register (phy_an_adv_x) . this allows the phy to advertise its flow con- trol abilities and auto-negotiate the flow control settings with its link partner. the default values of these bits are deter- mined via configuration straps as defined in section 9.2.20.5, "phy x auto-ne gotiation advertisement register (phy_an_adv_x)," on page 111 . 9.2.6.2 parallel detection if the device is connected to a device lack ing the ability to auto-negotiate (i.e. no flps are detected), it is able to deter- mine the speed of the link based on either 100m mlt-3 symbols or 10m normal link pulses. in this case the link is presumed to be half-duplex per the ieee 802.3 standard. this ability is known as ?paralle l detection.? this feature ensures interoperability with legacy link partners. if a link is formed via parallel detection, then the link partner auto- negotiation able bit of the phy x auto-negotiation exp ansion register (phy_an_exp_x) is cleared to indicate that the link partner is not capable of auto-negotiation. if a fault occurs during parallel detection, the parallel detection fault bit of the phy x auto-negotiation expansion register (phy_an_exp_x) is set. the phy x auto-negotiation link pa rtner base page ability regi ster (phy_an_lp_base_ability_x) is used to store the link partner ability information, which is coded in the re ceived flps. if the link partner is not auto-negotiation capa- ble, then this register is updated after completion of parallel detection to reflect the speed capability of the link partner. 9.2.6.3 restarting auto-negotiation auto-negotiation can be re-started at any time by setting the restart auto-negotiation (phy_rst_an) bit of the phy x basic control register (phy_basic_control_x) . auto-negotiation will also re-start if the link is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto-negotiation re sumes in an attempt to determine the new link configuration. if the management entity re-starts auto-negotiation by setting the restart auto-negotiation (phy_rst_an) bit of the phy x basic control regist er (phy_basic_control_x) , the device will respond by stopping all transmission/receiv- ing operations. once the internal break_link_time is comp leted in the auto-negotiation state-machine (approximately 1200ms), auto-negotiation will re-start. in this case, the li nk partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negotiation. auto-negotiation is also restarted afte r the eeprom loader updates the straps. 9.2.6.4 disabling auto-negotiation auto-negotiation can be disabled by clearing the auto-negotiation enable (phy_an) bit of the phy x basic control register (phy_ basic_control_x) . the transceiver will then force its speed of operation to reflect the information in the phy x basic control register (phy_basic_control_x) ( speed select lsb (phy_speed_sel_lsb) and duplex mode (phy_duplex) ). these bits are ignored when auto-negotiation is enabled.
LAN9354 ds00001926b-page 86 ? 2015 microchip technology inc. 9.2.6.5 half vs. full-duplex half-duplex operation relies on the csma/ cd (carrier sense multiple access / collision detect) protocol to handle net- work traffic and collisions. in this mode , the carrier sense signal, crs, responds to both transmit and receive activity. if data is received while the transceiver is transmitting, a collision results. in full-duplex mode, the transceiver is able to transmit and receive data simultaneously. in this mode, crs responds only to receive activity. the csma/cd protocol does not apply and collision detection is disabled. 9.2.7 hp auto-mdix hp auto-mdix facilitates the use of cat-3 (10 base-t) or cat-5 (100 base-t) media utp interconnect cable without consideration of interface wiring scheme. if a user plugs in either a direct conne ct lan cable or a cross-over patch cable, as shown in figure 9-4 , the transceiver is capable of configuring t he txpx/txnx and rxpx/rxnx twisted pair pins for correct transceiver operation. the internal logic of the device detects the tx and rx pi ns of the connecting device. since the rx and tx line pairs are interchangeable, special pcb design considerations are needed to accommodate the symmetrical magnetics and termination of an auto-mdix design. the auto-mdix function is enabled using the auto_mdix_strap_1 and auto_mdix_strap_2 configuration straps. manual selection of the cross-over can be set using the manual_mdix_strap_1 and manual_mdix_strap_2 configuration straps. software based control of the auto-mdi x function may be performed using the auto-mdix control (amdixctrl) bit of the phy x special control/status indication register (phy _special_control_stat_ind_x) . when amdixctrl is set to 1, the auto-mdix capability is determined by the auto-mdix enable (amdixen) and auto-mdix state (amdix- state) bits of the phy x special control/status indication register (phy_special_control_stat_ind_x) . note: auto-mdix is not used for 100base-fx mode. note: when operating in 10base-t or 100base-tx manual modes, the auto -mdix crossover time can be extended via the extend manual 10/100 auto-mdix crossover time bit of the phy x edpd nlp / cross- over time / eee configurati on register (phy_edpd_cfg_x) . refer to section 9.2.20.12, on page 120 for additional information. when energy detect power-down is enabled, the au to-mdix crossover time can be extended via the edpd extend crossover bit of the phy x edpd nlp / crossover ti me / eee configuration register (phy_edpd_cfg_x) . refer to section 9.2.20.12, on page 120 for additional information figure 9-4: direct cable connection vs. cross-over cable connection 1 2 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used 1 2 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used direct connect cable rj-45 8-pin straight-through for 10base-t/100base-tx signaling 1 2 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used 1 2 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used cross-over cable rj-45 8-pin cross-over for 10base-t/100base-tx signaling
? 2015 microchip technology inc. ds00001926b-page 87 LAN9354 9.2.8 phy management control the phy management control block is responsible for the m anagement functions of the phy, including register access and interrupt generation. a serial manag ement interface (smi) is used to support registers as required by the ieee 802.3 (clause 22), as well as the vendor specific registers allowed by the specificat ion. the smi interface consists of the mii management data (mdio) signal and the mii manag ement clock (mdc) signal. these signals allow access to all phy registers. refer to section 9.2.20, "physical phy registers," on page 102 for a list of all supported registers and register descriptions. non-supported registers will be read as ffffh. 9.2.9 phy interrupts the phy contains the ability to generate various interrupt events. reading the phy x interrupt source flags register (phy_interrupt_source_x) shows the source of the interrupt. the phy x interrupt mask re gister (phy_inter- rupt_mask_x) enables or disables each phy interrupt. the phy management control block aggregates the enabled inte rrupts status into an internal signal which is sent to the system interrupt controller and is reflected via the physical phy a interrupt event (phy_int_a) bit of the interrupt status register (int_sts) . for more information on the device interrupts, refer to section 8.0, "system interrupts," on page 67 . the phy interrupt system provides two modes, a primary interrupt mode and an alternative interrupt mode. both modes will assert the internal interrupt signal sent to the system interrupt controller when the corresponding mask bit is set. these modes differ only in how they de-assert the internal interrupt signal. these modes are detailed in the following subsections. 9.2.9.1 primary interrupt mode the primary interrupt mode is the default interrupt mode. th e primary interrupt mode is always selected after power-up or hard reset. in this mode, to enable an interrupt, set the corresponding mask bit in the phy x interrupt mask register (phy_interrupt_mask_x) (see ta b l e 9 - 3 ). when the event to assert an interrupt is true, the internal interrupt signal will be asserted. when the corresponding event to de-assert the interrupt is true, the internal interrupt signal will be de- asserted. note: the primary interrupt mode is the default interrupt mode after a power-up or hard reset. the alternative interrupt mode requires setup after a power-up or hard reset. table 9-3: interrupt management table mask interrupt source flag interrupt source event to assert interrupt event to de-assert interrupt 30.9 29.9 link up linkstat see note 1 link status rising link- stat falling linksat or reading register 29 30.8 29.8 wake on lan wol_int see note 2 enabled wol event rising wol_int falling wol_int or reading register 29 30.7 29.7 energyon 17.1 energyon rising 17.1 ( note 3 ) falling 17.1 or reading register 29 30.6 29.6 auto-negotia- tion complete 1.5 auto-negoti- ate com- plete rising 1.5 falling 1.5 or reading register 29
LAN9354 ds00001926b-page 88 ? 2015 microchip technology inc. note 1: linkstat is the internal link status and is not directly available in any register bit. note 2: wol_int is defined as bits 7:4 in the phy x wakeup control and status register (phy_wucsr_x) anded with bits 3:0 of the same register, wi th the resultant 4 bits or?ed together. note 3: if the mask bit is enabled and the internal interrupt signal has been de-asserted while energyon is still high, the internal interrupt signal will assert for 256 ms, approximately one second after energyon goes low when the cable is unplugged. to prevent an unexpected assertion of the internal interrupt signal, the energyon interrupt mask should always be cleared as part of the energyon interrupt service routine. 9.2.9.2 alternate interrupt mode the alternate interrupt mode is enabled by setting the altint bit of the phy x mode control/status register (phy_- mode_control_status_x) to ?1?. in this mode, to enable an interrupt, set the corresponding bit of the in the phy x interrupt mask register (phy_interrupt_mask_x) (see ta b l e 9 - 4 ). to clear an interrupt, clear the interrupt source and write a ?1? to the corresponding interrupt source flag. wr iting a ?1? to the interrupt source flag will cause the state machine to check the interrupt source to determine if the inte rrupt source flag should clear or stay as a ?1?. if the con- 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 falling 1.4, or reading register 1 or reading register 29 30.4 29.4 link down 1.2 link status falling 1.2 reading register 1 or reading register 29 30.3 29.3 auto-negotia- tion lp acknowl- edge 5.14 acknowl- edge rising 5.14 falling 5.14 or reading register 29 30.2 29.2 parallel detec- tion fault 6.4 parallel detection fault rising 6.4 falling 6.4 or reading register 6, or reading register 29, or re-auto negotiate or link down 30.1 29.1 auto-negotia- tion page received 6.1 page received rising 6.1 falling 6.1 or reading register 6, or reading register 29, or re-auto negotiate, or link down. note: the energy on (energyon) bit in the phy x mode control/status register (phy_mode_con- trol_status_x) is defaulted to a ?1? at the start of th e signal acquisition process, therefore the int7 bit in the phy x interrupt source flags register (phy_interrupt_source_x) will also read as a ?1? at power-up. if no signal is present, then both energy on (energyon) and int7 will clear within a few mil- liseconds. table 9-3: interrupt management table (continued)
? 2015 microchip technology inc. ds00001926b-page 89 LAN9354 dition to de-assert is true, th en the interrupt source flag is cleared and the internal interrupt signal is also deasserted. if the condition to de-assert is false, then the interrupt source flag remains set, and the internal interrupt signal remains asserted. note 4: linkstat is the internal link status and is not directly available in any register bit. note 5: wol_int is defined as bits 7:4 in the phy x wakeup control and status register (phy_wucsr_x) anded with bits 3:0 of the same register, wi th the resultant 4 bits or?ed together. table 9-4: alternative interrupt mode management table mask interrupt source flag interrupt source event to assert interrupt condition to de-assert bit to clear interrupt 30.9 29.9 link up linkstat see note 4 link status rising link- stat linkstat low 29.9 30.8 29.8 wake on lan wol_int see note 5 enabled wol event rising wol_int wol_int low 29.8 30.7 29.7 energyon 17.1 energyon rising 17.1 17.1 low 29.7 30.6 29.6 auto-negotia- tion complete 1.5 auto-negoti- ate com- plete rising 1.5 1.5 low 29.6 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 1.4 low 29.5 30.4 29.4 link down 1.2 link status falling 1.2 1.2 high 29.4 30.3 29.3 auto-negotia- tion lp acknowl- edge 5.14 acknowl- edge rising 5.14 5.14 low 29.3 30.2 29.2 parallel detec- tion fault 6.4 parallel detection fault rising 6.4 6.4 low 29.2 30.1 29.1 auto-negotia- tion page received 6.1 page received rising 6.1 6.1 low 29.1 note: the energy on (energyon) bit in the phy x mode control/status register (phy_mode_con- trol_status_x) is defaulted to a ?1? at the start of th e signal acquisition process, therefore the int7 bit in the phy x interrupt source flags register (phy_interrupt_source_x) will also read as a ?1? at power-up. if no signal is present, then both energy on (energyon) and int7 will clear within a few mil- liseconds.
LAN9354 ds00001926b-page 90 ? 2015 microchip technology inc. 9.2.10 phy power-down modes there are two phy power-down modes: general power-down mode and energy detect power-down mode. these modes are described in the following subsections. 9.2.10.1 general power-down this power-down mode is controlled by the power down (phy_pwr_dwn) bit of the phy x basic control register (phy_basic_control_x) . in this mode the entire tr ansceiver, except the phy management control interface, is powered down. the transceiver will remain in this power-down state as long as the power down (phy_pwr_dwn) bit is set. when the power down (phy_pwr_dwn) bit is cleared, the transceiver powers up and is automatically reset. 9.2.10.2 energy detect power-down this power-down mode is enabled by setting the energy detect power-down (edpwrdown) bit of the phy x mode control/status register (phy_mode_control_status_x) . in this mode, when no energy is present on the line, the entire transceiver is powered down (exc ept for the phy management control inte rface, the squelch circuit and the energyon logic). the energyon logic is used to dete ct the presence of valid energy from 100base-tx, 10base- t, or auto-negotiation signals. in this mode, when the energy on (energyon) bit in the phy x mode control/status register (phy_mode_con- trol_status_x) signal is low, the transceiver is powered down and nothing is transmitted. when energy is received, via link pulses or packets, the energy on (energyon) bit goes high, and the transceiver powers up. the transceiver automatically resets itself into the state prior to power-down, and asserts the int7 bit of the phy x interrupt source flags register (phy_interrupt_source_x) . the first and possibly second packet to activate energyon may be lost. when the energy detect power-down (edpwrdown) bit of the phy x mode control/status register (phy_mode_- control_status_x) is low, energy detect power-down is disabled. when in edpd mode, the device?s nlp characteristics may be modified. the device can be configured to transmit nlps in edpd via the edpd tx nlp enable bit of the phy x edpd nlp / crossover ti me / eee configur ation register (phy_edpd_cfg_x) . when enabled, the tx nlp time interval is configurable via the edpd tx nlp interval timer select field of the phy x edpd nlp / crossover time / eee co nfiguration register (phy_edpd_cfg_x) . when in edpd mode, the device can also be configured to wake on the reception of one or two nlps. setting the edpd rx single nlp wake enable bit of the phy x edpd nlp / crossover time / eee configuration register (phy_edpd_cf- g_x) will enable the device to wake on reception of a single nlp. if the edpd rx single nlp wake enable bit is cleared, the maximum interval for detecting reception of two nlps to wake from edpd is configurable via the edpd rx nlp max interval detect select field of the phy x edpd nlp / crossover time / eee configuration register (phy_edp- d_cfg_x) . the energy detect power down feature is part of the broad er power management features of the device and can be used to trigger the power management even t or general interrupt request pin ( irq ). this is accomplished by enabling the energy detect power-down feature of the phy as described a bove, and setting the corresponding energy detect enable (bit 14 for phy a, bi t 15 for phy b) of the power management control register (pmt_ctrl) . refer to power manage- ment for additional information. 9.2.11 energy ef ficient ethernet the phys support ieee 802.3az energy ef ficient ethernet (eee). the eee functi onality is enabled/disabled via the phy energy efficient ethernet enable (phyeeeen) bit of the phy x edpd nlp / crossove r time / eee configuration register (phy_edpd_cfg_x) . energy efficient ethernet is enabled or disabled by default via the eee_enable_strap_1 and eee_enable_strap_2 configuration straps. in order for eee to be utiliz ed, the following condit ions must be met: ? eee functionality must be enabled via the phy energy efficient et hernet enable (phyeeeen) bit of the phy x edpd nlp / crossover time / eee conf iguration register (phy_edpd_cfg_x) ?the 100base-tx eee bit of the mmd phy x eee advertisement register (phy_eee_adv_x) must be set note: for more information on the various power ma nagement features of the device, refer to section 6.3, "power management," on page 45 . the power-down modes of each phy are controlled independently. the phy power-down modes do not reload or reset the phy registers.
? 2015 microchip technology inc. ds00001926b-page 91 LAN9354 ? the mac and link-partner must support and be configured for eee operation ? the device and link-partner must link in 100base-tx full-duplex mode the value of the phy energy efficient et hernet enable (phyeeeen) bit affects the default values of the following reg- ister bits: ? 100base-tx eee bit of the mmd phy x eee capability register (phy_eee_cap_x) ? 100base-tx eee bit of the mmd phy x eee advertisement register (phy_eee_adv_x) note: energy efficient ethernet is not used for 100base-fx mode. 9.2.12 wake on lan (wol) the phy supports layer wol event detection of perf ect da, broadcast, magic packet, and wakeup frames. each type of supported wake event (perfect da, broadca st, magic packet, or wakeup frames) may be individually enabled via perfect da wakeup enable (pfda_en) , broadcast wakeup enable (bcst_en) , magic packet enable (mpen) , and wakeup frame enable (wuen) bits of the phy x wakeup control and status register (phy_wucsr_x) , respectively. the wol event is indicated via the int8 bit of the phy x interrupt source fl ags register (phy_inter- rupt_source_x) . the wol feature is part of the broader power management features of the device and can be used to trigger the power management event or general interrupt request pin ( irq ). this is accomplished by enabling the wol feature of the phy as described above, and setting the corresponding wol enable (bit 14 for phy a, bit 15 for phy b) of the power man- agement control register (pmt_ctrl) . refer to section 6.3, "power management," on page 45 for additional informa- tion. the phy x wakeup control and status register (phy_wucsr_x) also provides a wol configured bit, which may be set by software after all wol registers are configured. bec ause all wol related registers are not affected by software resets, software can poll the wol configured bit to ensure all wol registers are fu lly configured. this allows the software to skip reprogramming of the wol regist ers after reboot due to a wol event. the following subsections detail each type of wol event. for additional information on the main system interrupts, refer to section 8.0, "system interrupts," on page 67 . 9.2.12.1 perfect da (destination address) detection when enabled, the perfect da detection mode allows the detection of a frame with t he destination address matching the address stored in the phy x mac receive address a register (phy_rx_addra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x) . the frame must also pass the fcs and packet length check. as an example, the host system must perform the following steps to enable the device to detect a perfect da wol event: 1. set the desired mac address to cause the wake event in the phy x mac receive address a register (phy_rx- _addra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x) . 2. set the perfect da wakeup enable (pfda_en) bit of the phy x wakeup control and status register (phy_wucsr_x) to enable perfect da detection. 3. set bit 8 (wol event indicator) in the phy x interrupt mask regist er (phy_interrupt_mask_x) to enable wol events. when a match is triggered, bit 8 of the phy x interrupt source flags re gister (phy_int errupt_source_x) will be set, and the perfect da frame received (pfda_fr) bit of the phy x wakeup control and status register (phy_wucsr_x) will be set. 9.2.12.2 broadcast detection when enabled, the broadcast detection m ode allows the detection of a frame with the destination address value of ff ff ff ff ff ff. the frame must also pass the fcs and packet length check. as an example, the host system must perform the following st eps to enable the device to detect a broadcast wol event: 1. set the broadcast wakeup enable (bcst_en) bit of the phy x wakeup control and status register (phy_wucsr_x) to enable broadcast detection. 2. set bit 8 (wol event indicator) in the phy x interrupt mask regist er (phy_interrupt_mask_x) to enable wol events.
LAN9354 ds00001926b-page 92 ? 2015 microchip technology inc. when a match is triggered, bit 8 of the phy x interrupt source flags re gister (phy_int errupt_source_x) will be set, and the broadcast frame received (bcast_fr) bit of the phy x wakeup control and status register (phy_wucsr_x) will be set. 9.2.12.3 magic packet detection when enabled, the magic packet detection mode allows the detection of a magic packet frame. a magic packet is a frame addressed to the device - either a unicast to the progr ammed address, or a broadcast - which contains the pattern 48?h ff_ff_ff_ff_ff_ff after the destination and source address field, followed by 16 repet itions of the desired mac address (loaded into the phy x mac receive address a register (phy_rx_addra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x) ) without any breaks or interruptions. in case of a break in th e 16 address repetitions, the logic scans for the 48?h ff_ff_ff_ff_ff_ff pattern again in the incoming frame. the 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. the frame mu st also pass the fcs check and packet length checking. as an example, if the desired address is 00h 11h 22h 33h 44h 55h, then the logic scans for the following data sequence in an ethernet frame: destination address source ad dress ?????ff ff ff ff ff ff 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 ?fcs as an example, the host system must perform the following steps to enable the device to detect a magic packet wol event: set the desired mac address to cause the wake event in the phy x mac receive address a register (phy_rx_ad- dra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x) . set the magic packet enable (mpen) bit of the phy x wakeup control and status register (phy_wucsr_x) to enable magic packet detection. set bit 8 (wol event indicator) in the phy x interrupt mask regist er (phy_interrupt_mask_x) to enable wol events. when a match is triggered, bit 8 of the phy x interrupt source flags re gister (phy_int errupt_source_x) will be set, and the magic packet received (mpr) bit of the phy x wakeup control and status register (phy_wucsr_x) will be set. 9.2.12.4 wakeup frame detection when enabled, the wakeup frame detection mode allows t he detection of a pre-progra mmed wakeup frame. wakeup frame detection provides a wa y for system designers to de tect a customized pattern within a packet via a programma- ble wake-up frame filter. the filter has a 128-bit byte mask that indicates which bytes of the frame should be compared by the detection logic. a crc-16 is calculated over these byte s. the result is then compared with the filter?s respective crc-16 to determine if a match exists. w hen a wake-up pattern is received, the remote wakeup frame received (wufr) bit of the phy x wakeup control and status register (phy_wucsr_x) is set. if enabled, the filter can also incl ude a comparison between the frame?s dest ination address and the address specified in the phy x mac receive address a register (phy_rx_addra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x). the specified address can be a unicast or a multicast. if address matching is enable d, only the programmed unicast or multicast address will be considered a match. non-specific multicast addresses and the broadcast address can be separately enabled. the address matching results are logically or?d (i.e., specific address match result or any multicast result or broadcast result). whether or not the filter is enabled and whether the destination address is checked is determined by configuring the phy x wakeup filter configuration register a (phy_wuf_cfga_x). before enabling the filter , the application program must provide the detection logic with the sample frame and corresponding byte mask. this information is provided by writing the phy x wakeup filter configuration register a (phy_wuf_cfga_x), phy x wakeup filter configuration
? 2015 microchip technology inc. ds00001926b-page 93 LAN9354 register b (phy_wuf_cfgb_x) , and phy x wakeup filter byte mask registers (phy_wuf_mask_x) . the starting offset within the frame and the expected crc -16 for the filter is determined by the filter pattern offset and filter crc- 16 fields, respectively. if remote wakeup mode is enabled, the remote wakeup function checks each frame against the filter and recognizes the frame as a remote wakeup frame if it passes the filter?s address filtering and crc value match. the pattern offset defines the location of the first byte that should be checked in the frame. the byte mask is a 128-bit field that specifies whether or not each of the 128 contiguous bytes within the frame, beginning wit h the pattern offset, should be checked. if bit j in the byte mask is set, the detect ion logic checks the byte (patte rn offset + j) in the frame, otherwise byte (pattern offset + j) is ignored. at the completion of the crc-16 checking process, the c rc-16 calculated using the patt ern offset and byte mask is compared to the expected crc-16 value associated with the f ilter. if a match occurs, a remote wake-up event is sig- naled. the frame must also pass the fcs check and packet length checking. table 9-5 indicates the cases that produce a wake-up even t. all other cases do not generate a wake-up event. as an example, the host system must per form the following steps to enable the device to de tect a wakeup frame wol event: declare pattern: 1. update the phy x wakeup filter byte ma sk registers (phy_wuf_mask_x) to indicate the valid bytes to match. 2. calculate the crc-16 value of valid bytes offline and update the phy x wakeup filter configuration register b (phy_wuf_cfgb_x) . crc-16 is calculated as follows: at the start of a frame, crc-16 is initialized with th e value ffffh. crc-16 is updated when the pattern offset and mask indicate the received byte is part of the checksum calculation. the following algorithm is used to update the crc-16 at that time: let: ^ denote the exclusive or operator. data [7:0] be the received data byte to be included in the checksum. crc[15:0] contain the calc ulated crc-16 checksum. f0 ? f7 be intermediate results, calculated when a data byte is determined to be part of the crc-16. calculate: f0 = crc[15] ^ data[0] f1 = crc[14] ^ f0 ^ data[1] f2 = crc[13] ^ f1 ^ data[2] f3 = crc[12] ^ f2 ^ data[3] f4 = crc[11] ^ f3 ^ data[4] f5 = crc[10] ^ f4 ^ data[5] table 9-5: wakeup generation cases filter enabled frame type crc matches address match enabled any mcast enabled bcast enabled frame address matches yes unicast yes no x x x yes unicast yes yes x x yes yes multicast yes x yes x x yes multicast yes yes no x yes yes broadcast yes x x yes x
LAN9354 ds00001926b-page 94 ? 2015 microchip technology inc. f6 = crc[09] ^ f5 ^ data[6] f7 = crc[08] ^ f6 ^ data[7] the crc-32 is updated as follows: crc[15] = crc[7] ^ f7 crc[14] = crc[6] crc[13] = crc[5] crc[12] = crc[4] crc[11] = crc[3] crc[10] = crc[2] crc[9] = crc[1] ^ f0 crc[8] = crc[0] ^ f1 crc[7] = f0 ^ f2 crc[6] = f1 ^ f3 crc[5] = f2 ^ f4 crc[4] = f3 ^ f5 crc[3] = f4 ^ f6 crc[2] = f5 ^ f7 crc[1] = f6 crc[0] = f7 3. determine the offset pattern with offset 0 being the first byte of the destination addre ss. update the offset in the filter pattern offset field of the phy x wakeup f ilter configuration regist er a (phy_wuf_cfga_x). determine address ma tching conditions: 4. determine the address matching scheme based on table 9-5 and update the filter broadcast enable , filter any multicast enable , and address match enable bits of the phy x wakeup filter configuration register a (phy_wuf_cfga_x) accordingly. 5. if necessary (see step 4), set the desired mac address to cause the wake event in the phy x mac receive address a register (phy_rx_addra_x) , phy x mac receive address b register (phy_rx_addrb_x) , and phy x mac receive address c register (phy_rx_addrc_x) . 6. set the filter enable bit of the phy x wakeup filter configuration register a (phy_wuf_cfga_x) to enable the filter. enable wakeup frame detection: 7. set the wakeup frame enable (wuen) bit of the phy x wakeup control and status register (phy_wucsr_x) to enable wakeup frame detection. 8. set bit 8 (wol event indicator) in the phy x interrupt mask regist er (phy_interrupt_mask_x) to enable wol events. when a match is triggered, the remote wakeup frame received (wufr) bit of the phy x wakeup control and status register (phy_wucsr_x) will be set. to provide additional visibility to software, the filter triggered bit of the phy x wakeup filter configuration register a (phy_wuf_cfga_x) will be set.
? 2015 microchip technology inc. ds00001926b-page 95 LAN9354 9.2.13 resets in addition to the chip-level hardware reset ( rst# ) and power-on reset (p or), the phy supports three block specific resets. these are discussed in the following sections. for detailed information on all device resets and the reset sequence refer to section 6.2, "resets," on page 38 . 9.2.13.1 phy software reset via reset_ctl the phys can be reset via the reset control register (reset_ctl) . these bits are self clearing after approximately 102 us. this reset does not reload the config uration strap values into the phy registers. 9.2.13.2 phy software re set via phy_basic_ctrl_x the phy can also be reset by setting the soft reset (phy_srst) bit of the phy x basic control register (phy_ba- sic_control_x) . this bit is self clearing and will return to 0 after the reset is comp lete. this reset does not reload the configuration strap values into the phy registers. 9.2.13.3 phy power-down reset after the phy has returned from a power-down state, a rese t of the phy is automatically generated. the phy power- down modes do not reload or reset the phy registers. refer to section 9.2.10, "phy power-down modes," on page 90 for additional information. 9.2.14 link integrity test the device performs the lin k integrity test as outlined in the ieee 802.3u (c lause 24-15) link moni tor state diagram. the link status is multiplexed with the 10 mbps link status to form the link status bit in the phy x basic status register (phy_basic_status_x) and to drive the link led functions. the dsp indicates a valid mlt-3 waveform present on the rxpx and rxnx signals as defin ed by the ansi x3.263 tp- pmd standard, to the link monitor state-machine, us ing the internal data_valid signal. when data_valid is asserted, the control logic moves into a link-ready state and waits for an enable from the auto-negotiation block. when received, the link-up state is entered, and the transmit and receive logic blocks become active. should auto-negoti- ation be disabled, the link integrity logic moves immediat ely to the link-up state when the data_valid is asserted. to allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time data_valid is asserted until the link-ready state is entered. should the data_valid input be negat ed at any time, this logic will immediately negate the link signal and enter the link-down state. when the 10/100 digital blo ck is in 10base-t mode, the link status is derived from the 10base-t receiver logic. 9.2.15 cable diagnostics the phys provide cable diagnostics which allow for open/shor t and length detection of the ethernet cable. the cable diagnostics consist of two primary modes of operation: ? time domain reflectometry (tdr) cable diagnostics tdr cable diagnostics enable the detection of open or shor ted cabling on the tx or rx pair, as well as cable length estimation to the open/short fault. ? matched cable diagnostics matched cable diagnostics enable cable length estimation on 100 mbps-linked cables. refer to the following sub-sections for details on proper operation of each cable diagnostics mode. note: only a hardware reset ( rst# ) or power-on reset (por) will automatically reload the configuration strap values into the phy registers. the digital reset (digital_rst) bit in the reset control regi ster (reset_ctl) does not reset the phys. the digital reset (digital_rst) bit will cause the eeprom loader to reload the configuration strap values into the phy register s and to reset all other phy regist ers to their default values. an eeprom reload command via the eeprom command register (e2p_cmd) also has the same effect. for all other phy resets, phy registers will need to be manually configured via software. note: cable diagnostics are not used for 100base-fx mode.
LAN9354 ds00001926b-page 96 ? 2015 microchip technology inc. 9.2.15.1 time domain reflectometry (tdr) cable diagnostics the phys provide tdr cable diagnostics which enable the detecti on of open or shorted cabli ng on the tx or rx pair, as well as cable length estimation to the open/short faul t. to utilize the tdr cable diagnostics, auto-mdix and auto negotiation must be disabled, and the phy must be forced to 100 mbps full-duplex mode. these actions must be per- formed before setting the tdr enable bit in the phy x tdr control/status register (phy_tdr_control_stat_x) . with auto-mdix disabled, the tdr will test the tx or rx pair selected by register bit 27.13 ( auto-mdix state (amdix- state) ). proper cable testing should include a test of each pair. tdr cable diagnostics is not app ropriate for 100base- fx mode. when tdr testing is complete, prior register settings may be restored. figure 9-5 provides a flow diagram of proper tdr usage. figure 9-5: tdr usage flow diagram disable amdix and force mdi (or mdix) write phy reg 27: 0x8000 (mdi) - or - write phy reg 27: 0xa000 (mdix) tdr channel status complete? disable aneg and force 100mb full- duplex write phy reg 0: 0x2100 enable tdr write phy reg 25: 0x8000 no reg 25.8 == 0 yes reg 25.8 == 1 check tdr control/status register read phy reg 25 save: tdr channel type (reg 25.10:9) tdr channel length (reg 25.7:0) mdix case tested? yes repeat testing in mdix mode done start
? 2015 microchip technology inc. ds00001926b-page 97 LAN9354 the tdr operates by transmitting puls es on the selected twisted pair within the ethernet cable (tx in mdi mode, rx in mdix mode). if the pair being tested is open or shorted, the resulting impedance discontinuity results in a reflected signal that can be detected by the phy. the phy measures the time between the transmitted signal and received reflec- tion and indicates the results in the tdr channel length field of the phy x tdr control/status register (phy_tdr_- control_stat_x) . the tdr channel length field indicates the ?electrical? length of the cable, and can be multiplied by the appropriate propagation constant in ta b l e 9 - 6 to determine the approximate physical distance to the fault. since the tdr relies on the reflected signal of an improperly terminated cable, there are se veral factors that can affect the accuracy of the physical length estimate. these include: 1. cable type (cat 5, cat5e, cat6): the electrical length of each cable type is slightly different due to the twists- per-meter of the internal signal pairs and differences in signal prop agation speeds . if the cable type is known, the length estimate can be calculated more accurately by using the propagation constant appropriate for the cable type (see ta b l e 9 - 6 ). in many real-world applications the cable type is unknown, or may be a mix of different cable types and lengths. in this case, use the prop agation constant for the ?unknown? cable type. 2. tx and rx pair: for each cable type, the eia standards specify different twis t rates (twists-per-meter) for each signal pair within the ethernet cable. this result s in different measurements for the rx and tx pair. 3. actual cable length: the difference between the estimated cable le ngth and actual cable length grows as the physical cable length increases, with the most accurate results at less than approximately 100 m. 4. open/short case: the open and shorted cases will return diff erent tdr channel length values (electrical lengths) for the same physical distance to the fault. comp ensation for this is achieved by using different propa- gation constants to calculate th e physical length of the cable. for the open case, the estimated distance to the fault can be calculated as follows: distance to open fault in meters ?? tdr channel length * p open where: p open is the propagation c onstant selected from ta b l e 9 - 6 for the shorted case, the estimated distance to the fault can be calculated as follows: distance to open fault in meters ? tdr channel length * p short where: p short is the propagation constant selected from table 9-6 the typical cable length measurement margin of error for open and shorted cases is dependent on the selected cable type and the distance of the open/short from the device. ta b l e 9 - 7 and table 9-8 detail the typical measurement error for open and shorted cases, respectively. note: the tdr function is typically used when the link is inoperable. however, an active link will drop when oper- ating the tdr. table 9-6: tdr propagation constants tdr propagation constant cable type unknown cat 6 cat 5e cat 5 p open 0.769 0.745 0.76 0.85 p short 0.793 0.759 0.788 0.873 table 9-7: typical measurement error for open cable (+/- meters) physical distance to fault selected propagation constant p open = unknown p open = cat 6 p open = cat 5e p open = cat 5 cat 6 cable, 0-100 m 96 cat 5e cable, 0-100 m 5 5
LAN9354 ds00001926b-page 98 ? 2015 microchip technology inc. 9.2.15.2 matched cable diagnostics matched cable diagnostics enable cable length estimation on 10 0 mbps-linked cables of up to 120 meters. if there is an active 100 mb link, the approximate distance to the link partner can be estimated using the phy x cable length register (phy_cable_len_x) . if the cable is properly terminat ed, but there is no active 100 mb link (the link partner is disabled, nonfunctional, the link is at 10 mb, etc.), the cable length cannot be estimated and the phy x cable length register (phy_cable_len_x) should be ignored. the estimated distance to the link partner can be determined via the cable length (cbln) field of the phy x cable length register (phy_cable_len_x) using the lookup table provided in table 9-9 . the typical cable length measurement margin of erro r for a matched cable case is +/- 20 m. the matched cable length margin of error is consistent for all cable types from 0 to 120 m. cat 5 cable, 0-100 m 13 3 cat 6 cable, 101-160 m 14 6 cat 5e cable, 101-160 m 8 6 cat 5 cable, 101-160 m 20 6 table 9-8: typical measurement error for shorted cable (+/- meters) physical distance to fault selected propagation constant p short = unknown p short = cat 6 p short = cat 5e p short = cat 5 cat 6 cable, 0-100 m 85 cat 5e cable, 0-100 m 5 5 cat 5 cable, 0-100 m 11 2 cat 6 cable, 101-160 m 14 6 cat 5e cable, 101-160 m 7 6 cat 5 cable, 101-160 m 11 3 table 9-9: match case estimated cable length (cbln) lookup cbln field value estimated cable length 0 - 3 0 46 517 627 738 849 959 10 70 11 81 table 9-7: typical measurement error for open cable (+/- meters)
? 2015 microchip technology inc. ds00001926b-page 99 LAN9354 9.2.16 loopback operation the phys may be configured for near-end loopback and connector loopback. these loopback modes are detailed in the following subsections. 9.2.16.1 near-end loopback near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indi- cated by the blue arrows in figure 9-6 . the near-end loopback mode is enabled by setting the loopback (phy_loop- back) bit of the phy x basic control regist er (phy_basic_control_x) to ?1?. a large percentage of the digital circuitry is operational in near-end loopback mode becaus e data is routed through the pcs and pma layers into the pmd sublayer before it is looped back. the col signal will be inactive in this mode, unless collision test mode (phy_col_test) is enabled in the phy x basic control register (phy_basic_control_x) . the transmitters are powered down regardless of the state of the internal mii txen signal. 12 91 13 102 14 113 15 123 note: for a properly terminated cable (match case), t here is no reflected signal. in this case, the tdr channel length field is invalid and should be ignored. figure 9-6: near-end loopback block diagram table 9-9: match case estimated cable length (cbln) lookup 10/100 ethernet mac cat-5 xfmr digital rxd txd analog rx tx x x
LAN9354 ds00001926b-page 100 ? 2015 microchip technology inc. 9.2.16.2 connector loopback the device maintains reliable transmission over very short cables and can be tested in a connector loopback as shown in figure 9-7 . an rj45 loopback cable can be used to route the trans mit signals from the output of the transformer back to the receiver inputs. the loopback works at both 10 and 100 mbps. 9.2.17 100base-fx operation when set for 100base-fx operati on, the scrambler and mtl-3 blocks are disa ble and the analog rx and tx pins are changed to differential lvpecl pins and connect through extern al terminations to the external fiber transceiver. the differential lvpecl pins support a signal voltage range compatible with sff (lvpecl) and sfp (reduced lvpecl) type transceivers. while in 100base-fx operation, the quality of the receive sign al is provided by the exter nal transceiver as either an open-drain, cmos level, loss of signal (sfp) or a lvpecl signal detect (sff). 9.2.17.1 100base-fx far end fault indication since auto-negotiation is not specifi ed for 100base-fx, its remote fault capabi lity is unavailabl e. instead, 100base- fx provides an optional far-end fault function. when no signal is being received, the far-end fault feature transmits a specia l far-end fault indication to its far-end peer. the far-end fault indication is sent only when a physical error condition is sensed on the receive channel. the far-end fault i ndication is comprised of three or more repeating cycles, ea ch of 84 ones followed by a single zero. this signal is sent in-band and is readily detectable but is constructed so as to not satisfy the 100base-x carrier sense criterion. far-end fault is implemented through the far-end fault g enerate, far-end fault detect, and the link monitor pro- cesses. the far-end fault generate process is responsible for sensing a receive channel failure (signal_status=off) and transmitting the far-end fault indication in response. the transmission of the far-end fault indication may start or stop at any time depending only on signal_status. the far- end fault detect process continuously monitors the rx pro- cess for the far-end fault indication. dete ction of the far-end fault indication di sables the station by causing the link monitor process to de-assert link_status, which in turn causes the station to source idles. far-end fault is enabled by default while in 100base-fx mode via the far end fault indicati on enable (fefi_en) of the phy x special control/status indication register (phy _special_control_stat_ind_x) . 9.2.17.2 100base-fx enable and los/sd selection 100base-fx operation is enabled by the use of the fx mode straps ( fx_mode_strap_1 and fx_mode_strap_2 ) and is reflected in the 100base-fx mode (fx_mode) bit in the phy x special modes regist er (phy_special_modes_x) . loss of signal mode is selected for both phys by the three level fxlosen strap input pin. the three levels correspond to loss of signal mode for a) neither phy (less than 1 v (typ.)), b) phy a (greater than 1 v (t yp.) but less than 2 v (typ.)) or c) both phys (greater than 2 v (t yp.)). it is not possible to select loss of signal mode for only phy b. figure 9-7: connection loopback block diagram 10/100 ethernet mac xfmr digital rxd txd analog rx tx 1 2 3 4 5 6 7 8 rj45 loopback cable. created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6.
? 2015 microchip technology inc. ds00001926b-page 101 LAN9354 if loss of signal mode is not sele cted, then signal detect mode is selected, independently, by the fxsdena or fxs- denb strap input pin. when greater than 1 v (typ.), signal detect mode is enabled, when less than 1 v (typ.), copper twisted pair is enabled. table 9-10 and ta b l e 9 - 11 summarize the selections. 9.2.18 required ethernet magn etics (100base-tx and 10base-t) the magnetics selected for use with the device should be an auto-mdix style magnetic, which is widely available from several vendors. please review the smsc/microchip appl ication note 8.13 ?suggested m agnetics? for the latest quali- fied and suggested magnetics. a list of vendors and part numbers are provided within the application note. 9.2.19 external pin access timing requirements when accessed externally via the mdio / mdc pins, the following timing applies. note: the fxsdena strap input pin is shared with the fxsda pin and the fxsdenb strap input pin is shared with the fxsdb pin. as such, the lvpecl levels ensure that the input is gr eater than 1 v (typ.) and that signal detect mode is selected. when tp copper is desired, the signal detect input function is not required and the pin should be set to 0 v. care must be taken such that an non-powered or disa bled transceiver does not load the signal detect input below the valid lvpecl level. table 9-10: 100base-fx los, sd and tp copper selection phy a fxlosen fxsdena phy mode <1 v (typ.) <1 v (typ.) tp copper >1 v (typ.) 100base-fx signal detect >1 v (typ.) n/a 100base-fx los table 9-11: 100base-fx los, sd and tp copper selection phy b fxlosen fxsdenb phy mode <1 v (typ.) <1 v (typ.) tp copper >1 v (typ.) 100base-fx signal detect >2 v (typ.) n/a 100base-fx los
LAN9354 ds00001926b-page 102 ? 2015 microchip technology inc. note 6: the physical phy design changes ou tput data a nominal 4 clocks ( 25mhz) maximum and a nominal 2 clocks (25mhz) minimum follow ing the rising edge of mdc. note 7: the physical phy design samples input data using the rising edge of mdc. 9.2.20 physical phy registers the physical phys a and b are comparable in functionality and have an identical set of non-memory mapped registers. these registers are indirectly accessed through the phy management interface a ccess register (pmi_access) and phy management interface data register (pmi_data) or through the external mi i management interface pins. because physical phy a and b registers are functionally i dentical, their register descriptions have been consolidated. a lowercase ?x? has been appended to the end of each phy regi ster name in this section, where ?x? hold be replaced with ?a? or ?b? for the phy a or phy b registers respectively . in some instances, a ?1? or a ?2? may be appropriate instead. a list of the mii serial accessible control and status regist ers and their corresponding register index numbers is included in ta b l e 9 - 1 3 . each individual phy is assigned a unique phy address as detailed in section 9.1.1, "phy addressing," on page 77 . in addition to the mii serial accessible control and status re gisters, a set of indirectly ac cessible registers provides sup- port for the ieee 802.3 section 45.2 mdio manageable device (mmd) registers . a list of these registers and their cor- responding register index numbers is included in table 9-19 . figure 9-8: physical ph y external access timing table 9-12: physical phy external access timing values symbol description min max units notes t clkp mdc period 400 - ns t clkh mdc high time 160 (80%) - ns t clkl mdc low time 160 (80%) - ns t val mdio output valid from rising edge of mdc - 300 ns note 6 t ohold mdio output hold from rising edge of mdc 10 - ns note 6 t su mdio input setup time to rising edge of mdc 10 - ns note 7 t ihold mdio input hold time after rising edge of mdc 5 - ns note 7 mdc mdio t clkh t clkl t clkp t ohold mdio t su t ihold (data-out) (data-in) t ohold t val
? 2015 microchip technology inc. ds00001926b-page 103 LAN9354 note: the digital reset (digital_rst) bit will cause the eeprom loader to reload the configuration strap val- ues into the phy registers and to reset all other phy registers to t heir default values. an eeprom reload command via the eeprom command register (e2p_cmd) also has the same effect. control and status registers table 9-13 provides a list of supported registers. register details , including bit definitions, are provided in the following subsections. unless otherwise specified, reserved fields must be written with zeros if the register is written. table 9-13: physical phy a and b mii ser ially accessible co ntrol and status registers index register name (symbol) group 0 phy x basic control regist er (phy_basic_control_x) basic 1 phy x basic status register (phy_basic_status_x) basic 2 phy x identification msb register (phy_id_msb_x) extended 3 phy x identification lsb register (phy_id_lsb_x) extended 4 phy x auto-negotiation advertisement register (phy_an_adv_x) extended 5 phy x auto-negotiation link partner base page ability register (phy_an_lp_base_ability_x) extended 6 phy x auto-negotiation expa nsion register (phy_an_exp_x) extended 7 phy x auto negotiation next page tx register (phy_an_np_tx_x) extended 8 phy x auto negotiation next page rx register (phy_an_np_rx_x) extended 13 phy x mmd access control register (phy_mmd_access) extended 14 phy x mmd access address/data register (phy_mmd_addr_data) extended 16 phy x edpd nlp / crossover time / eee co nfiguration register (phy_edpd_cfg_x) vendor- specific 17 phy x mode control/status regist er (phy_mode_control_status_x) vendor- specific 18 phy x special modes register (phy_special_modes_x) vendor- specific 24 phy x tdr patterns/delay control register (phy_tdr_pat_delay_x) vendor- specific 25 phy x tdr control/status regi ster (phy_tdr_control_stat_x) vendor- specific 26 phy x symbol error counter register vendor- specific 27 phy x special control/status indi cation register (phy_special_con- trol_stat_ind_x) vendor- specific 28 phy x cable length register (phy_cable_len_x) vendor- specific 29 phy x interrupt source flags r egister (phy_interrupt_source_x) vendor- specific
LAN9354 ds00001926b-page 104 ? 2015 microchip technology inc. 30 phy x interrupt mask register (phy_interrupt_mask_x) vendor- specific 31 phy x special control/status regi ster (phy_special_control_status_x) vendor- specific table 9-13: physical phy a and b mii serially accessi ble control and status registers (continued) index register name (symbol) group
? 2015 microchip technology inc. ds00001926b-page 105 LAN9354 9.2.20.1 phy x basic control register (phy_basic_control_x) this read/write register is used to configure the phy. index (decimal): 0 size: 16 bits bits description type default 15 soft reset (phy_srst) when set, this bit resets all the phy r egisters to their default state, except those marked as nasr type. this bit is self clearing. 0: normal operation 1: reset r/w sc 0b 14 loopback (phy_loopback) this bit enables/disables the loopback mode. when enabled, transmissions are not sent to network. instead, they are looped back into the phy. 0: loopback mode disabled (normal operation) 1: loopback mode enabled r/w 0b 13 speed select lsb (phy_speed_sel_lsb) this bit is used to set the speed of the phy when the auto-negotiation enable (phy_an) bit is disabled. 0: 10 mbps 1: 100 mbps r/w note 8 12 auto-negotiation enable (phy_an) this bit enables/disables auto-n egotiation. when enabled, the speed select lsb (phy_speed_sel_lsb) and duplex mode (phy_duplex) bits are overridden. this bit is forced to a 0 if the 100base-fx mode (fx_mode) bit of the phy x special modes register (phy_special_modes_x) is a high. 0: auto-negotiation disabled 1: auto-negotiation enabled r/w note 9 11 power down (phy_pwr_dwn) this bit controls the power down mode of the phy. 0: normal operation 1: general power down mode r/w 0b 10 reserved ro - 9 restart auto-negotiation (phy_rst_an) when set, this bit restarts the auto-negotiation process. 0: normal operation 1: auto-negotiation restarted r/w sc 0b
LAN9354 ds00001926b-page 106 ? 2015 microchip technology inc. note 8: the default value of this bit is determined by the logical or of the auto-negotiation strap ( autoneg_strap_1 for phy a, autoneg_strap_2 for phy b) and the speed select strap ( speed_strap_1 for phy a, speed_strap_2 for phy b). essentially, if the au to-negotiation strap is set, t he default value is 1, otherwise the default is determined by the value of the speed select strap. refer to section 7.0, "configuration straps," on page 54 for more information. in 100base-fx mode, the default value of this bit is a 1. note 9: the default is the value of the auto-negotiation strap ( autoneg_strap_1 for phy a, autoneg_strap_2 for phy b). refer to section 7.0, "configuration straps," on page 54 for more information. in 100base-fx mode, the default value of this bit is a 0. note 10: the default value of this bit is determined by the logi cal and of the negation of the auto-negotiation strap ( autoneg_strap_1 for phy a, autoneg_strap_2 for phy b) and the duplex select strap ( duplex_strap_1 for phy a, duplex_strap_2 for phy b). essentially, if the auto-negotia tion strap is set, the default value is 0, otherwise the default is determined by the va lue of the duplex select strap. refer to section 7.0, "configu- ration straps," on page 54 for more information. in 100base-fx mode, the auto-negotiati on strap is not considered and the default of this bit is the value of the duplex select strap. 8 duplex mode (phy_duplex) this bit is used to set the duplex when the auto-negotiation enable (phy_an) bit is disabled. 0: half duplex 1: full duplex r/w note 10 7 collision test mode (phy_col_test) this bit enables/disables the collision test mode of the phy. when set, the collision signal is active during transmission. it is recommended that this fea- ture be used only in loopback mode. 0: collision test mode disabled 1: collision test mode enabled r/w 0b 6:0 reserved ro - bits description type default
? 2015 microchip technology inc. ds00001926b-page 107 LAN9354 9.2.20.2 phy x basic status r egister (phy_basic_status_x) this register is used to monitor the status of the phy. index (decimal): 1 size: 16 bits bits description type default 15 100base-t4 this bit displays the status of 100base-t4 compatibility. 0: phy not able to perform 100base-t4 1: phy able to perform 100base-t4 ro 0b 14 100base-x full duplex this bit displays the status of 100base-x full duplex compatibility. 0: phy not able to perf orm 100base-x full duplex 1: phy able to perfor m 100base-x full duplex ro 1b 13 100base-x half duplex this bit displays the status of 100base-x half duplex compatibility. 0: phy not able to perform 100base-x half duplex 1: phy able to perform 100base-x half duplex ro 1b 12 10base-t full duplex this bit displays the status of 10base-t full duplex compatibility. 0: phy not able to perform 10base-t full duplex 1: phy able to perform 10base-t full duplex ro 1b 11 10base-t half duplex (typ.) this bit displays the status of 10base-t half duplex compatibility. 0: phy not able to perform 10base-t half duplex 1: phy able to perform 10base-t half duplex ro 1b 10 100base-t2 full duplex this bit displays the status of 100base-t2 full duplex compatibility. 0: phy not able to perform 100base-t2 full duplex 1: phy able to perform 100base-t2 full duplex ro 0b 9 100base-t2 half duplex this bit displays the status of 100base-t2 half duplex compatibility. 0: phy not able to perform 100base-t2 half duplex 1: phy able to perform 100base-t2 half duplex ro 0b 8 extended status this bit displays whether extended status information is in register 15 (per ieee 802.3 clause 22.2.4). 0: no extended status information in register 15 1: extended status information in register 15 ro 0b
LAN9354 ds00001926b-page 108 ? 2015 microchip technology inc. 7 unidirectional ability this bit indicates whether the phy is able to transmit regardless of whether the phy has determined that a valid link has been established. 0: can only transmit when a valid link has been established 1: can transmit regardless ro 0b 6 mf preamble suppression this bit indicates whether the phy accepts management frames with the pre- amble suppressed. 0: management frames with preamble suppressed not accepted 1: management frames with preamble suppressed accepted ro 0b 5 auto-negotiation complete this bit indicates the status of the auto-negotiation process. 0: auto-negotiation process not completed 1: auto-negotiation process completed ro 0b 4 remote fault this bit indicates if a remote fault condition has been detected. 0: no remote fault condition detected 1: remote fault condition detected ro/lh 0b 3 auto-negotiation ability this bit indicates the phy?s auto-negotiation ability. 0: phy is unable to perform auto-negotiation 1: phy is able to pe rform auto-negotiation ro 1b 2 link status this bit indicates the status of the link. 0: link is down 1: link is up ro/ll 0b 1 jabber detect this bit indicates the status of the jabber condition. 0: no jabber condition detected 1: jabber condition detected ro/lh 0b 0 extended capability this bit indicates whether extended register capability is supported. 0: basic register set capabilities only 1: extended register set capabilities ro 1b bits description type default
? 2015 microchip technology inc. ds00001926b-page 109 LAN9354 9.2.20.3 phy x identification msb register (phy_id_msb_x) this read/write register contains the m sb of the organizationally unique identifier (oui) for the phy. the lsb of the phy oui is cont ained in the phy x identification lsb register (phy_id_lsb_x) . index (decimal): 2 size: 16 bits bits description type default 15:0 phy id this field is assigned to the 3rd through 18th bits of the oui, respectively (oui = 00800fh). r/w 0007h
LAN9354 ds00001926b-page 110 ? 2015 microchip technology inc. 9.2.20.4 phy x identification lsb register (phy_id_lsb_x) this read/write register contains the l sb of the organizationally unique identifi er (oui) for the phy. the msb of the phy oui is cont ained in the phy x identification msb register (phy_id_msb_x) . index (decimal): 3 size: 16 bits bits description type default 15:10 phy id this field is assigned to the 19th through 24th bits of the phy oui, respec- tively. (oui = 00800fh). r/w c140h 9:4 model number this field contains the 6-bit manufacturer?s model number of the phy. r/w 3:0 revision number this field contain the 4-bit manufacturer?s revision number of the phy. r/w note: the default value of the revision number field may vary dependent on the silicon revision number.
? 2015 microchip technology inc. ds00001926b-page 111 LAN9354 9.2.20.5 phy x auto-negotiation advertisement register (phy_an_adv_x) this read/write register contains the advertised ability of the phy and is used in the auto-negotiation process with the link partner. index (decimal): 4 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable r/w 0b 14 reserved ro - 13 remote fault this bit determines if remote fault indication will be advertised to the link part- ner. 0: remote fault indication not advertised 1: remote fault indication advertised r/w 0b 12 extended next page note: this bit should be written as 0. r/w 0b 11 asymmetric pause this bit determines the advertised asymmetric pause capability. 0: no asymmetric pause toward link partner advertised 1: asymmetric pause toward link partner advertised r/w note 11 10 symmetric pause this bit determines the advertised symmetric pause capability. 0: no symmetric pause toward link partner advertised 1: symmetric pause toward link partner advertised r/w note 11 9 reserved ro - 8 100base-x full duplex this bit determines the advertised 100base-x full d uplex capability. 0: 100base-x full duplex ability not advertised 1: 100base-x full duplex ability advertised r/w 1b 7 100base-x half duplex this bit determines the advertised 100base-x half duplex capability. 0: 100base-x half duplex ability not advertised 1: 100base-x half duplex ability advertised r/w 1b 6 10base-t full duplex this bit determines the advertised 10base-t full duplex capability. 0: 10base-t full duplex ability not advertised 1: 10base-t full duplex ability advertised r/w note 12 table 9-14
LAN9354 ds00001926b-page 112 ? 2015 microchip technology inc. note 11: the default values of the a symmetric pause and symmetric pause bits are determined by the manual flow control enable strap ( manual_fc_strap_1 for phy a, manual_fc_strap_2 for phy b). when the manual flow control enable strap is 0, th e symmetric pause bit defaults to 1 and the asymmetric pause bit defaults to the setting of the full-duplex flow control enable strap ( fd_fc_strap_1 for phy a, fd_fc_strap_2 for phy b). when the manual flow control enable strap is 1, both bits default to 0. refer to section 7.0, "con- figuration straps," on page 54 for more information. in 100base-fx mode, the default valu e of these bits is 0. note 12: the default value of this bit is determined by the logical or of the auto-negotiation enable strap ( autoneg_strap_1 for phy a, autoneg_strap_2 for phy b) with the logical and of the negated speed select strap ( speed_strap_1 for phy a, speed_strap_2 for phy b) and the duplex select strap ( duplex_strap_1 for phy a, duplex_strap_2 for phy b). table 9-14 defines the default behavior of this bit. refer to section 7.0, "configuration straps," on page 54 for more information. in 100base-fx mode, th e default value of this bit is a 0. note 13: the default value of this bit is determined by the logical or of the auto-negotiation strap ( autoneg_strap_1 for phy a, autoneg_strap_2 for phy b) and the negated speed select strap ( speed_strap_1 for phy a, speed_strap_2 for phy b). ta b l e 9 - 1 5 defines the default behavior of this bit. refer to section 7.0, "config- uration straps," on page 54 for more information. in 100base-fx mode, the default value of this bit is a 0. 5 10base-t half duplex this bit determines the advertised 10base-t half duplex capability. 0: 10base-t half duplex ability not advertised 1: 10base-t half duplex ability advertised r/w note 13 table 9-15 4:0 selector field this field identifies the type of message being sent by auto-negotiation. 00001: ieee 802.3 r/w 00001b table 9-14: 10base-t full duplex advertisement default value autoneg_strap_x speed_strap_x duplex_strap_x default 10base-t full duplex (bit 6) value 000 0 001 1 010 0 011 0 1xx 1 table 9-15: 10base-t half duplex advertisement bit default value autoneg_strap_x speed_strap_x default 10base-t half duplex (bit 5) value 00 1 01 0 10 1 11 1 bits description type default
? 2015 microchip technology inc. ds00001926b-page 113 LAN9354 9.2.20.6 phy x auto-negot iation link partner ba se page ability register (phy_an_lp_base_ability_x) this read-only register contai ns the advertised ability of the link partner?s phy and is used in the auto-negotiation pro- cess between the link partner and the phy. index (decimal): 5 size: 16 bits bits description type default 15 next page this bit indicates the link partner phy page capability. 0: link partner phy does not ad vertise next page capability 1: link partner phy advertises next page capability ro 0b 14 acknowledge this bit indicates whether the link code word has been received from the partner. 0: link code word not yet received from partner 1: link code word received from partner ro 0b 13 remote fault this bit indicates whether a remote fault has been detected. 0: no remote fault 1: remote fault detected ro 0b 12 extended next page 0: link partner phy does not advertise extended next page capability 1: link partner phy advertises extended next page capability ro 0b 11 asymmetric pause this bit indicates the link partner phy asymmetric pause capability. 0: no asymmetric pause toward link partner 1: asymmetric pause toward link partner ro 0b 10 pause this bit indicates the link part ner phy symmetric pause capability. 0: no symmetric pause toward link partner 1: symmetric pause toward link partner ro 0b 9 100base-t4 this bit indicates t he link partner phy 10 0base-t4 capability. 0: 100base-t4 ability not supported 1: 100base-t4 ability supported ro 0b 8 100base-x full duplex this bit indicates the link partner phy 100base- x full duplex capability. 0: 100base-x full duplex ability not supported 1: 100base-x full duplex ability supported ro 0b
LAN9354 ds00001926b-page 114 ? 2015 microchip technology inc. 7 100base-x half duplex this bit indicates the link partner phy 100base-x half duplex capability. 0: 100base-x half duplex ability not supported 1: 100base-x half duplex ability supported ro 0b 6 10base-t full duplex this bit indicates the link partner phy 10base-t full duplex capability. 0: 10base-t full duplex ability not supported 1: 10base-t full duplex ability supported ro 0b 5 10base-t half duplex this bit indicates the link partner phy 10base-t half duplex capability. 0: 10base-t half duplex ability not supported 1: 10base-t half duplex ability supported ro 0b 4:0 selector field this field identifies the type of message being sent by auto-negotiation. 00001: ieee 802.3 ro 00001b bits description type default
? 2015 microchip technology inc. ds00001926b-page 115 LAN9354 9.2.20.7 phy x au to-negotiation expansi on register (phy_an_exp_x) this read/write register is used in the auto-negotiation process between the link partner and the phy. index (decimal): 6 size: 16 bits bits description type default 15:7 reserved ro - 6 receive next page location able 0 = received next page storage location is not specified by bit 6.5 1 = received next page storage lo cation is specified by bit 6.5 ro 1b 5 received next page storage location 0 = link partner next pages are stored in the phy x auto-negotiation link partner base page ability regi ster (phy_an_lp_base_ability_x) (phy register 5) 1 = link partner next pages are stored in the phy x auto negotiation next page rx register (phy_an_np_rx_x) (phy register 8) ro 1b 4 parallel detection fault this bit indicates whether a paralle l detection fault has been detected. 0: a fault hasn?t been detected via the parallel detection function 1: a fault has been detected vi a the parallel de tection function ro/lh 0b 3 link partner next page able this bit indicates whether the link partner has next page ability. 0: link partner does not contain next page capability 1: link partner contains next page capability ro 0b 2 next page able this bit indicates whether the local device has next page ability. 0: local device does not contain next page capability 1: local device contains next page capability ro 1b 1 page received this bit indicates the reception of a new page. 0: a new page has not been received 1: a new page has been received ro/lh 0b 0 link partner auto -negotiation able this bit indicates the auto-negotiation ability of the link partner. 0: link partner is not auto-negotiation able 1: link partner is auto-negotiation able ro 0b
LAN9354 ds00001926b-page 116 ? 2015 microchip technology inc. 9.2.20.8 phy x auto negotiation next page tx register (phy_an_np_tx_x) index (in decimal): 7 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable r/w 0b 14 reserved ro - 13 message page 0 = unformatted page 1 = message page r/w 1b 12 acknowledge 2 0 = device cannot co mply with message. 1 = device will comply with message. r/w 0b 11 toggle 0 = previous value was high. 1 = previous value was low. ro 0b 10:0 message code message/unformatted code field r/w 000 0000 0001b
? 2015 microchip technology inc. ds00001926b-page 117 LAN9354 9.2.20.9 phy x auto negotiation next page rx register (phy_an_np_rx_x) index (in decimal): 8 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable ro 0b 14 acknowledge 0 = link code word not yet received from partner 1 = link code word received from partner ro 0b 13 message page 0 = unformatted page 1 = message page ro 0b 12 acknowledge 2 0 = device cannot comply with message. 1 = device will comply with message. ro 0b 11 toggle 0 = previous value was high. 1 = previous value was low. ro 0b 10:0 message code message/unformatted code field ro 000 0000 0000b
LAN9354 ds00001926b-page 118 ? 2015 microchip technology inc. 9.2.20.10 phy x mmd access cont rol register (phy_mmd_access) this register in conjunction with the phy x mmd access address/data register (phy_mmd_addr_data) provides indirect access to the mdio manageable device (mmd) registers. refer to the mdio manageable device (mmd) reg- isters on page 136 for additional details. index (in decimal): 13 size: 16 bits bits description type default 15:14 mmd function this field is used to select the desired mmd function: 00 = address 01 = data, no post increment 10 = reserved 11 = reserved r/w 00b 13:5 reserved ro - 4:0 mmd device address (devad) this field is used to select the desired mmd device address. (3 = pcs, 7 = auto-negotiation) r/w 0h
? 2015 microchip technology inc. ds00001926b-page 119 LAN9354 9.2.20.11 phy x mmd access address/da ta register (phy_mmd_addr_data) this register in conjunction with the phy x mmd access control register (phy_mmd_access) provides indirect access to the mdio manageable device (mmd) registers. refer to the mdio manageable device (mmd) registers on page 136 for additional details. index (in decimal): 14 size: 16 bits bits description type default 15:0 mmd register address/data if the mmd function field of the phy x mmd access control register (phy_mmd_access) is ?00?, this field is used to indicate the mmd register address to read/write of the device specified in the mmd device address (devad) field. otherwise, this register is used to read/write data from/to the previously specified mmd address. r/w 0000h
LAN9354 ds00001926b-page 120 ? 2015 microchip technology inc. 9.2.20.12 phy x edpd nlp / crossover time / eee configuration register (phy_edpd_cfg_x) this register is used to enable eee f unctionality and control nl p pulse generation and the auto-mdix crossover time of the phy. index (decimal): 16 size: 16 bits bits description type default 15 edpd tx nlp enable enables the generation of a normal link pulse (nlp) with a selectable inter- val while in energy detect power-down. 0=disabled, 1=enabled. the energy detect power-down (edpwrdown) bit in the phy x mode control/status register (phy_mode_control_status_x) needs to be set in order to enter energy detect power-down mode and the phy needs to be in the energy detect power-down state in order for this bit to generate the nlp. the edpd tx nlp independent mode bit of this register also needs to be set when setting this bit. r/w nasr note 14 0b 14:13 edpd tx nlp inte rval timer select specifies how often a nlp is transmitted while in the energy detect power- down state. 00b: 1 s 01b: 768 ms 10b: 512 ms 11b: 256 ms r/w nasr note 14 00b 12 edpd rx single nlp wake enable when set, the phy will wake upon the reception of a single normal link pulse. when clear, the phy requires two link pluses, within the interval spec- ified below, in order to wake up. single nlp wake mode is recommended when connecting to ?green? net- work devices. r/w nasr note 14 0b 11:10 edpd rx nlp max interval detect select these bits specify the maximum time between two consecutive normal link pulses in order for them to be considered a valid wake up signal. 00b: 64 ms 01b: 256 ms 10b: 512 ms 11b: 1 s r/w nasr note 14 00b 9:4 reserved ro - 3 edpd tx nlp independent mode when set, each phy port independently detects power down for purposes of the edpd tx nlp function (via the edpd tx nlp enable bit of this register). when cleared, both ports need to be in a power-down state in order to gener- ate tx nlps during energy detect power-down. normally set this bit when setting edpd tx nlp enable . r/w nasr note 14 0b
? 2015 microchip technology inc. ds00001926b-page 121 LAN9354 note 14: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. note 15: the default value of this bit is a 0 if in 100base-fx mode, otherwise the default value of this bit is deter- mined by the energy efficient ethernet enable strap ( eee_enable_strap_1 for phy a, eee_en- able_strap_2 for phy b). refer to section 7.0, "configuration straps," on page 54 for more information. 2 phy energy efficient et hernet enable (phyeeeen) when set, enables energy efficient et hernet (eee) operation in the phy. when cleared, eee operation is disabled. refer to section 9.2.11, "energy efficient ethernet," on page 90 for additional information. r/w nasr note 14 note 15 1 edpd extend crossover when in energy detect power-down (edpd) mode ( energy detect power- down (edpwrdown) = 1), setting this bit to 1 extends the crossover time by 2976 ms. 0 = crossover time extension disabled 1 = crossover time extension enabled (2976 ms) r/w nasr note 14 0b 0 extend manual 10/100 auto-mdix crossover time when auto-negotiation is disabled, setting this bit extends the auto-mdix crossover time by 32 sample times (32 * 62 ms = 1984 ms). this allows the link to be established with a partner phy that has auto-negotiation enabled. when auto-negotiation is enabled, this bit has no affect. it is recommended that this bit is set when disabling an with auto-mdix enabled. r/w nasr note 14 1b bits description type default
LAN9354 ds00001926b-page 122 ? 2015 microchip technology inc. 9.2.20.13 phy x mode control/status register (phy_mode_ control_status_x) this read/write register is us ed to control and monitor various phy configuration options. note 16: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (decimal): 17 size: 16 bits bits description type default 15:14 reserved ro - 13 energy detect power-down (edpwrdown) this bit controls the energy detect power-down mode. 0: energy detect power-down is disabled 1: energy detect power-down is enabled note: when in edpd mode, the device?s nlp characteristics can be modified via the phy x edpd nlp / crossover time / eee configuration register (phy_edpd_cfg_x) . r/w 0b 12:7 reserved ro - 6 altint alternate interrupt mode: 0 = primary interrupt system enabled (default) 1 = alternate interrupt system enabled refer to section 9.2.9, "phy interrupts," on page 87 for additional informa- tion. r/w nasr note 16 0b 5:2 reserved ro - 1 energy on (energyon) indicates whether energy is detected. this bit transitions to ?0? if no valid energy is detected within 256 ms (1500 ms if auto-negotiation is enabled). it is reset to ?1? by a hardware reset and by a software reset if auto-negotiation was enabled or will be enabled via strapping. refer to section 9.2.10.2, "energy detect power-down," on page 90 for additional information. ro 1b 0 reserved ro -
? 2015 microchip technology inc. ds00001926b-page 123 LAN9354 9.2.20.14 phy x special modes register (phy_special_modes_x) this read/write register is used to control the special modes of the phy. note 17: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. note 18: the default value of this bit is determined by the fiber enable strap ( fx_mode_strap_1 for phy a, fx_- mode_strap_2 for phy b). note 19: the default value of this field is determined by a combination of the configur ation straps autoneg_strap_x, speed_strap_x, and duplex_strap_x. if the autoneg_strap_x is 1, then t he default mode[2:0] value is 111b. else, the default value of this field is de termined by the remain ing straps. mode[2]=0, mode[1]=( speed_strap_1 for phy a, speed_strap_2 for phy b), and mode[0]=( duplex_strap_1 for phy a, duplex_strap_2 for phy b). refer to section 7.0, "configuration straps," on page 54 for more information. in 100base-fx mode, the default value of these bits is 010b or 011b. depending on the duplex configuration strap. note 20: the default value of this field is determined per section 9.1.1, "phy addressing," on page 77 . index (decimal): 18 size: 16 bits bits description type default 15:11 reserved ro - 10 100base-fx mode (fx_mode) this bit enables 100base-fx mode note: fx_mode cannot properly be changed with this bit. this bit must always be written with its current value. device st rapping must be used to set the desired mode. r/w nasr note 17 note 18 9:8 reserved ro - 7:5 phy mode (mode[2:0]) this field controls the phy mode of operation. refer to table 9-16 for a defi- nition of each mode. note: this field should be written with its read value. r/w nasr note 17 note 19 4:0 phy address (phyadd) the phy address field determines the mmi address to which the phy will respond and is also used for initialization of the cipher (scrambler) key. each phy must have a unique address. refer to section 9.1.1, "phy addressing," on page 77 for additional information. note: no check is performed to ensure that this address is unique from the other phy addresses (phy a, phy b, and the virtual phy). r/w nasr note 17 note 20 table 9-16: mode[2:0] definitions mode[2:0] mode definitions 000 10base-t half duplex. auto-negotiation disabled. 001 10base-t full duplex. auto-negotiation disabled.
LAN9354 ds00001926b-page 124 ? 2015 microchip technology inc. 010 100base-tx or 100base-fx half duplex. au to-negotiation disabled. crs is active during transmit & receive. 011 100base-tx or 100base-fx full duplex. auto-negotiation disabled. crs is active during receive. 100 100base-tx full duplex is ad vertised. auto-negoti ation enabled. crs is active during receive. 101 reserved 110 power down mode. 111 all capable. auto-negotiation enabled. table 9-16: mode[2:0] definitions (continued) mode[2:0] mode definitions
? 2015 microchip technology inc. ds00001926b-page 125 LAN9354 9.2.20.15 phy x tdr patte rns/delay control regist er (phy_tdr_pat_delay_x) note 21: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 24 size: 16 bits bits description type default 15 tdr delay in 0 = line break time is 2 ms. 1 = the device uses tdr line break counter to increase the line break time before starting tdr. r/w nasr note 21 1b 14:12 tdr line break counter when tdr delay in is 1, this field specifies the increase in line break time in increments of 256 ms, up to 2 seconds. r/w nasr note 21 001b 11:6 tdr pattern high this field specifies the data patter n sent in tdr mode for the high cycle. r/w nasr note 21 101110b 5:0 tdr pattern low this field specifies the data pattern sent in tdr mode for the low cycle. r/w nasr note 21 011101b
LAN9354 ds00001926b-page 126 ? 2015 microchip technology inc. 9.2.20.16 phy x tdr control/status register (phy_tdr_control_stat_x) note 22: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 25 size: 16 bits bits description type default 15 tdr enable 0 = tdr mode disabled 1 = tdr mode enabled note: this bit self clears when tdr completes ( tdr channel status goes high) r/w nasr sc note 22 0b 14 tdr analog to digital filter enable 0 = tdr analog to digital filter disabled 1 = tdr analog to digital filter enabled (reduces noise spikes during tdr pulses) r/w nasr note 22 0b 13:11 reserved ro - 10:9 tdr channel cable type indicates the cable type de termined by the tdr test. 00 = default 01 = shorted cable condition 10 = open cable condition 11 = match cable condition r/w nasr note 22 00b 8 tdr channel status when high, this bit indicates that the tdr operation has completed. this bit will stay high until reset or the tdr operation is restarted ( tdr enable = 1) r/w nasr note 22 0b 7:0 tdr channel length this eight bit value indicates the tdr channel length during a short or open cable condition. refer to section 9.2.15.1, "time domain reflectometry (tdr) cable diagnostics," on page 96 for additional information on the usage of this field. note: this field is not valid during a match cable condition. the phy x cable length register (phy_cable_len_x) must be used to determine cable length during a no n-open/short (match) condition. refer to section 9.2.15, "cable diagnostics," on page 95 for additional information. r/w nasr note 22 00h
? 2015 microchip technology inc. ds00001926b-page 127 LAN9354 9.2.20.17 phy x symbol error counter register index (in decimal): 26 size: 16 bits bits description type default 15:0 symbol error coun ter (sym_err_cnt) this 100base-tx receiver-based error counter increments when an invalid code symbol is received, including idle symbols. the counter is incre- mented only once per packet, even when the received packet contains more than one symbol error. this field counts up to 65,536 and rolls over to 0 if incremented beyond its maximum value. note: this register is cleared on reset, but is not cleared by reading the register. it does not increment in 10base-t mode. ro 0000h
LAN9354 ds00001926b-page 128 ? 2015 microchip technology inc. 9.2.20.18 phy x special control/status indication register (phy_special_cont rol_stat_ind_x) this read/write register is used to control various options of the phy. index (decimal): 27 size: 16 bits bits description type default 15 auto-mdix contro l (amdixctrl) this bit is responsible for determinin g the source of au to-mdix control for port x. when set, the manual mdix and auto mdix straps ( manual_mdix- _strap_1 / auto_mdix_strap_1 for phy a, manual_mdix_strap_2 / auto_mdix- _strap_2 for phy b) are overridden, and auto-mdix functions are controlled using the amdixen and amdixstate bits of this register. when cleared, auto-mdix functionality is controlled by the manual mdix and auto mdix straps by default. refer to section 7.0, "configuration straps," on page 54 for configuration st rap definitions. 0: port x auto-mdix determined by strap inputs ( table 9-18 ) 1: port x auto-mdix determined by bits 14 and 13 note: the values of auto_mdix_strap_1 and auto_mdix_strap_2 are indicated in the amdix_en strap state port a and the amdix_en strap state port b bits of the hardware configuration register (hw_cfg) . r/w nasr note 23 0b 14 auto-mdix enable (amdixen) when the amdixctrl bit of this register is set, this bit is used in conjunction with the amdixstate bit to control the port x auto-mdix functionality as shown in table 9-17 . auto-mdix is not appropriate and should not be enabled for 100base-fx mode. r/w nasr note 23 0b 13 auto-mdix state (amdixstate) when the amdixctrl bit of this register is set, this bit is used in conjunction with the amdixen bit to control the po rt x auto-mdix functionality as shown in ta b l e 9 - 1 7 . r/w nasr note 23 0b 12 reserved ro - 11 sqe test disable (sqeoff) this bit controls the disabling of th e sqe test (heartbeat). sqe test is enabled by default. 0: sqe test enabled 1: sqe test disabled r/w nasr note 23 0b 10:6 reserved ro - 5 far end fault indication enable (fefi_en) this bit enables far end fault generation and detection. see section 9.2.17.1, "100base-fx far end fault indication," on page 100 for more information. r/w note 24
? 2015 microchip technology inc. ds00001926b-page 129 LAN9354 note 23: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. note 24: the default value of this bit is a 1 if in 100base-fx mode, otherwise the default is a 0. 4 10base-t polarity state (xpol) this bit shows the polarity state of the 10base-t. 0: normal polarity 1: reversed polarity ro 0b 3:0 reserved ro - table 9-17: auto-mdix enable and auto-mdix state bit functionality auto-mdix enable auto-mdix state mode 0 0 manual mode, no crossover 0 1 manual mode, crossover 1 0 auto-mdix mode 1 1 reserved (do not use this state) table 9-18: mdix strap functionality auto_mdix_strap_x manual_mdix_strap_x mode 0 0 manual mode, no crossover 0 1 manual mode, crossover 1 x auto-mdix mode bits description type default
LAN9354 ds00001926b-page 130 ? 2015 microchip technology inc. 9.2.20.19 phy x cable length register (phy_cable_len_x) index (in decimal): 28 size: 16 bits bits description type default 15:12 cable length (cbln) this four bit value indicates the cable length. refer to section 9.2.15.2, "matched cable diagnostics," on page 98 for additional information on the usage of this field. note: this field indicates cable leng th for 100base-tx linked devices that do not have an open/short on the cable. to determine the open/short status of the cable, the phy x tdr patterns/delay control register (phy_tdr_pat_delay_x) and phy x tdr control/status register (phy_tdr_control_stat_x) must be used. cable length is not supported for 10base-t links. refer to section 9.2.15, "cable diagnostics," on page 95 for additional information. ro 0000b 11:0 reserved - write as 100000000000b, ignore on read r/w -
? 2015 microchip technology inc. ds00001926b-page 131 LAN9354 9.2.20.20 phy x interrupt source flags register (phy_interrupt_source_x) this read-only register is used to determine to source of va rious phy interrupts. all interrupt source bits in this register are read-only and latch high upon detection of the corresponding interrupt (if enabled). a read of this register clears the interrupts. these interrupts are enabled or masked via the phy x interrupt mask register (phy_inter- rupt_mask_x) . index (decimal): 29 size: 16 bits bits description type default 15:9 reserved ro - 9 int9 this interrupt source bit indicates a link up (link status asserted). 0: not source of interrupt 1: link up (link status asserted) ro/lh 0b 8 int8 0: not source of interrupt 1: wake on lan (wol) event detected ro/lh 0b 7 int7 this interrupt source bit indicates when the energy on (energyon) bit of the phy x mode control/status r egister (phy_mode_control_sta- tus_x) has been set. 0: not source of interrupt 1: energyon generated ro/lh 0b 6 int6 this interrupt source bit indicates auto-negotiation is complete. 0: not source of interrupt 1: auto-negotia tion complete ro/lh 0b 5 int5 this interrupt source bit indicate s a remote fault has been detected. 0: not source of interrupt 1: remote fault detected ro/lh 0b 4 int4 this interrupt source bit indicates a link down (link status negated). 0: not source of interrupt 1: link down (link status negated) ro/lh 0b 3 int3 this interrupt source bit indicates an auto-negotiation lp acknowledge. 0: not source of interrupt 1: auto-negotiation lp acknowledge ro/lh 0b
LAN9354 ds00001926b-page 132 ? 2015 microchip technology inc. 2 int2 this interrupt source bit indicates a parallel detection fault. 0: not source of interrupt 1: parallel detection fault ro/lh 0b 1 int1 this interrupt source bit indicates an auto-negotiation page received. 0: not source of interrupt 1: auto-negotiation page received ro/lh 0b 0 reserved ro - bits description type default
? 2015 microchip technology inc. ds00001926b-page 133 LAN9354 9.2.20.21 phy x interrupt mask register (phy_interrupt_mask_x) this read/write register is used to enable or mask the various phy interrupts and is used in conjunction with the phy x interrupt source flags regist er (phy_interrupt_source_x) . index (decimal): 30 size: 16 bits bits description type default 15:10 reserved ro - 9 int9_mask this interrupt mask bit enables/masks the link up (link status asserted) inter- rupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 8 int8_mask this interrupt mask bit enabl es/masks the wol interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 7 int7_mask this interrupt mask bit enables /masks the energyon interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 6 int6_mask this interrupt mask bi t enables/masks the auto -negotiation interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 5 int5_mask this interrupt mask bi t enables/masks the remo te fault interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 4 int4_mask this interrupt mask bit en ables/masks the link down (link status negated) interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 3 int3_mask this interrupt mask bit enables/masks the auto-negotiation lp acknowledge interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b
LAN9354 ds00001926b-page 134 ? 2015 microchip technology inc. 2 int2_mask this interrupt mask bit en ables/masks the parallel de tection fault interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 1 int1_mask this interrupt mask bit enables/masks the auto-negotiation page received interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 0 reserved ro - bits description type default
? 2015 microchip technology inc. ds00001926b-page 135 LAN9354 9.2.20.22 phy x special cont rol/status register (phy _special_control_status_x) this read/write register is used to control and monitor various options of the phy. index (decimal): 31 size: 16 bits bits description type default 15:13 reserved ro - 12 autodone this bit indicates the status of the auto-negotiation on the phy. 0: auto-negotiation is not complete d, is disabled, or is not active 1: auto-negotiation is completed ro 0b 11:5 reserved - write as 00 00010b, ignore on read r/w 0000010b 4:2 speed indication this field indicates the current phy speed configuration. ro xxxb 1:0 reserved ro 0b state description 000 reserved 001 10base-t half-duplex 010 100base-tx half-duplex 011 reserved 100 reserved 101 10base-t full-duplex 110 100base-tx full-duplex 111 reserved
LAN9354 ds00001926b-page 136 ? 2015 microchip technology inc. mdio manageable d evice (mmd) registers the device mmd registers adhere to the ieee 802.3-2008 45.2 mdio interface registers specification. the mmd reg- isters are not memory mapped. these r egisters are accessed indirectly via the phy x mmd access control register (phy_mmd_access) and phy x mmd access address/data register (phy_mmd_addr_data) . the supported mmd device addresses are 3 (pcs), 7 (auto- negotiation), and 30 (vendor specific). table 9-19, "mmd registers" details the supported registers within each mmd device. table 9-19: mmd registers mmd device address (in decimal) index (in decimal) register name 3 (pcs) 0 phy x pcs control 1 register (phy_pcs_ctl1_x) 1 phy x pcs status 1 register (phy_pcs_stat1_x) 5 phy x pcs mmd devices present 1 register (phy_pcs_mmd_pre- sent1_x) 6 phy x pcs mmd devices present 2 register (phy_pcs_mmd_pre- sent2_x) 20 phy x eee capability register (phy_eee_cap_x) 22 phy x eee wake error register (phy_eee_wake_err_x) 32784 phy x wakeup control and status register (phy_wucsr_x) 32785 phy x wakeup filter configurat ion register a (phy_wuf_cfga_x) 32786 phy x wakeup filter configurat ion register b (phy_wuf_cfgb_x) 32801 phy x wakeup filter byte mask registers (phy_wuf_mask_x) 32802 32803 32804 32805 32806 32807 32808 32865 phy x mac receive address a register (phy_rx_addra_x) 32866 phy x mac receive address b register (phy_rx_addrb_x) 32867 phy x mac receive address c register (phy_rx_addrc_x) 7 (auto-negotiation) 5 phy x auto-negotiation mmd devices present 1 register (phy_an_mmd_present1_x) 6 phy x auto-negotiation mmd devices present 2 register (phy_an_mmd_present2_x) 60 phy x eee advertisement register (phy_eee_adv_x) 61 phy x eee link partne r advertisement register (phy_eee_lp_ad- v_x)
? 2015 microchip technology inc. ds00001926b-page 137 LAN9354 to read or write an mmd register, the following procedure must be observed: 1. write the phy x mmd access control register (phy_mmd_access) with 00b (address) for the mmd function field and the desired mmd device (3 for pcs, 7 for auto-negotiation) for the mmd device address (devad) field. 2. write the phy x mmd access address/data register (phy_mmd_addr_data) with the 16-bit address of the desired mmd register to read/write within the previous ly selected mmd device (pcs or auto-negotiation). 3. write the phy x mmd access control register (phy_mmd_access) with 01b (data) for the mmd function field and choose the previously selected mmd device (3 for pcs, 7 for auto-negotiation) for the mmd device address (devad) field. 4. if reading, read the phy x mmd access address/data register (phy_mmd_addr_data) , which contains the selected mmd register contents. if writing, write the phy x mmd access address/data register (phy_m- md_addr_data) with the register contents intended for the previously selected mmd register. unless otherwise specified, reserved fields must be written with zeros if the register is written. 30 (vendor specific) 2 phy x vendor specific mmd 1 device id 1 register (phy_vend_spec_mmd1_devid1_x) 3 phy x vendor specific mmd 1 device id 2 register (phy_vend_spec_mmd1_devid2_x) 5 phy x vendor specific mmd 1 devices present 1 register (phy_vend_spec_mmd1_present1_x) 6 phy x vendor specific mmd 1 devices present 2 register (phy_vend_spec_mmd1_present2_x) 8 phy x vendor specific mmd 1 status register (phy_vend_spec_mmd1_stat_x) 14 phy x vendor specific mmd 1 package id 1 register (phy_vend_spec_mmd1_pkg_id1_x) 15 phy x vendor specific mmd 1 package id 2 register (phy_vend_spec_mmd1_pkg_id2_x) table 9-19: mmd registers (continued) mmd device address (in decimal) index (in decimal) register name
LAN9354 ds00001926b-page 138 ? 2015 microchip technology inc. 9.2.20.23 phy x pcs control 1 register (phy_pcs_ctl1_x) index (in decimal): 3.0 size: 16 bits bits description type default 15:11 reserved ro - 10 clock stop enable 0 = the phy cannot stop the clock during low power idle (lpi) 1 = the phy may stop the clock during lpi note: this bit has no affect since the device does not support this mode. r/w 0b 9:0 reserved ro -
? 2015 microchip technology inc. ds00001926b-page 139 LAN9354 9.2.20.24 phy x pcs status 1 register (phy_pcs_stat1_x) index (in decimal): 3.1 size: 16 bits bits description type default 15:12 reserved ro - 11 tx lpi received 0 = tx pcs has not received lpi 1 = tx pcs has received lpi ro/lh 0b 10 rx lpi received 0 = rx pcs has not received lpi 1 = rx pcs has received lpi ro/lh 0b 9 tx lpi indication 0 = tx pcs is not currently receiving lpi 1 = tx pcs is currently receiving lpi ro 0b 8 rx lpi indication 0 = rx pcs is not currently receiving lpi 1 = rx pcs is currently receiving lpi ro 0b 7 reserved ro - 6 clock stop capable 0 = the mac cannot stop the clock during low power idle (lpi) 1 = the mac may stop the clock during lpi note: the device does not support this mode. ro 0b 5:0 reserved ro -
LAN9354 ds00001926b-page 140 ? 2015 microchip technology inc. 9.2.20.25 phy x pcs mmd devices present 1 register (phy_p cs_mmd_present1_x) index (in decimal): 3.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b
? 2015 microchip technology inc. ds00001926b-page 141 LAN9354 9.2.20.26 phy x pcs mmd devices present 2 register (phy_pcs_mmd_present2_x) index (in decimal): 3.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro -
LAN9354 ds00001926b-page 142 ? 2015 microchip technology inc. 9.2.20.27 phy x eee capabilit y register (phy_eee_cap_x) note 25: the default value of this field is determined by the value of the phy energy efficient ethernet enable (phy- eeeen) of the phy x edpd nlp / crossover time / eee conf iguration register (phy_edpd_cfg_x) on page 120 . if phy energy efficient ethernet enable (phyeeeen) is 0b, this field is 0b and 100base-tx eee capability is no t supported. if phy energy efficient ethernet enable (phyeeeen) is 1b, then this field is 1b and 100base-tx eee ca pability is supported. index (in decimal): 3.20 size: 16 bits bits description type default 15:7 reserved ro - 6 10gbase-kr eee 0 = eee is not support ed for 10gbase-kr 1 = eee is supported for 10gbase-kr note: the device does not support this mode. ro 0b 5 10gbase-kx4 eee 0 = eee is not support ed for 10gbase-kx4 1 = eee is supported for 10gbase-kx4 note: the device does not support this mode. ro 0b 4 10gbase-kx eee 0 = eee is not support ed for 10gbase-kx 1 = eee is supported for 10gbase-kx note: the device does not support this mode. ro 0b 3 10gbase-t eee 0 = eee is not support ed for 10gbase-t 1 = eee is supported for 10gbase-t note: the device does not support this mode. ro 0b 2 1000base-t eee 0 = eee is not support ed for 1000base-t 1 = eee is supporte d for 1000base-t note: the device does not support this mode. ro 0b 1 100base-tx eee 0 = eee is not support ed for 100base-tx 1 = eee is supported for 100base-tx ro note 25 0 reserved ro -
? 2015 microchip technology inc. ds00001926b-page 143 LAN9354 9.2.20.28 phy x eee wake error register (phy_eee_wake_err_x) index (in decimal): 3.22 size: 16 bits bits description type default 15:0 eee wake error counter this counter is cleared to zeros on read and is held to all ones on overflow. ro/rc 0000h
LAN9354 ds00001926b-page 144 ? 2015 microchip technology inc. 9.2.20.29 phy x wakeup control and status register (phy_wucsr_x) note 26: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32784 size: 16 bits bits description type default 15:9 reserved ro - 8 wol configured this bit may be set by software after the wol registers are configured. this sticky bit (and all other w ol related register bits) is reset only via a power cycle or a pin reset, allowing software to skip programming of the wol regis- ters in response to a wol event. note: refer to section 9.2.12, "wake on lan (wol)," on page 91 for additional information. r/w/ nasr note 26 0b 7 perfect da frame received (pfda_fr) the mac sets this bit upon receiving a valid frame with a destination address that matches the physical address. r/wc/ nasr note 26 0b 6 remote wakeup frame received (wufr) the mac sets this bit upon receiving a valid remote wakeup frame. r/wc/ nasr note 26 0b 5 magic packet received (mpr) the mac sets this bit upon receiving a valid magic packet. r/wc/ nasr note 26 0b 4 broadcast frame received (bcast_fr) the mac sets this bit upon receiving a valid broadcast frame. r/wc/ nasr note 26 0b 3 perfect da wakeup enable (pfda_en) when set, remote wakeup mode is enabled and the mac is capable of wak- ing up on receipt of a frame with a de stination address that matches the physical address of the device. the physical address is stored in the phy x mac receive address a register (phy_rx_addra_x) , phy x mac receive address b register (phy_rx_addrb_x) and phy x mac receive address c register (phy_rx_addrc_x) . r/w/ nasr note 26 0b 2 wakeup frame enable (wuen) when set, remote wakeup mode is enabled and the mac is capable of detecting wakeup frames as programmed in the wakeup filter. r/w/ nasr note 26 0b 1 magic packet enable (mpen) when set, magic packet wakeup mode is enabled. r/w/ nasr note 26 0b 0 broadcast wakeup enable (bcst_en) when set, remote wakeup mode is enabled and the mac is capable of wak- ing up from a broadcast frame. r/w/ nasr note 26 0b
? 2015 microchip technology inc. ds00001926b-page 145 LAN9354 9.2.20.30 phy x wakeup filter configuration register a (phy_wuf_cfga_x) note 27: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32785 size: 16 bits bits description type default 15 filter enable 0 = filter disabled 1 = filter enabled r/w/ nasr note 27 0b 14 filter triggered 0 = filter not triggered 1 = filter triggered r/wc/ nasr note 27 0b 13:11 reserved ro - 10 address match enable when set, the destination address must match the programmed address. when cleared, any unicast packet is accepted. refer to section 9.2.12.4, "wakeup frame detection," on page 92 for additional information. r/w/ nasr note 27 0b 9 filter any multicast enable when set, any multicast packet other than a broadcast will cause an address match. refer to section 9.2.12.4, "wakeup frame detection," on page 92 for additional information. note: this bit has priority over bit 10 of this register. r/w/ nasr note 27 0b 8 filter broadcast enable when set, any broadcast frame will cause an address match. refer to sec- tion 9.2.12.4, "wakeup frame detection," on page 92 for additional informa- tion. note: this bit has priority over bit 10 of this register. r/w/ nasr note 27 0b 7:0 filter pattern offset specifies the offset of the first by te in the frame on which crc checking begins for wakeup frame recognition. offset 0 is the first byte of the incom- ing frame?s destination address. r/w/ nasr note 27 00h
LAN9354 ds00001926b-page 146 ? 2015 microchip technology inc. 9.2.20.31 phy x wakeup filter configuration register b (phy_wuf_cfgb_x) note 28: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32786 size: 16 bits bits description type default 15:0 filter crc-16 this field specifies the expe cted 16-bit crc value for the filter that should be obtained by using the pattern offset and the byte mask programmed for the fil- ter. this value is compared against the crc calculated on the incoming frame, and a match indicates t he reception of a wakeup frame. r/w/ nasr note 28 0000h
? 2015 microchip technology inc. ds00001926b-page 147 LAN9354 9.2.20.32 phy x wakeup filter byte mask re gisters (phy_wuf_mask_x) index (in decimal): 3.32801 size: 16 bits bits description type default 15:0 wakeup filter byte mask [127:112] r/w/ nasr note 29 0000h index (in decimal): 3.32802 size: 16 bits bits description type default 15:0 wakeup filter byte mask [111:96] r/w/ nasr note 29 0000h index (in decimal): 3.32803 size: 16 bits bits description type default 15:0 wakeup filter byte mask [95:80] r/w/ nasr note 29 0000h index (in decimal): 3.32804 size: 16 bits bits description type default 15:0 wakeup filter byte mask [79:64] r/w/ nasr note 29 0000h
LAN9354 ds00001926b-page 148 ? 2015 microchip technology inc. note 29: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32805 size: 16 bits bits description type default 15:0 wakeup filter byte mask [63:48] r/w/ nasr note 29 0000h index (in decimal): 3.32806 size: 16 bits bits description type default 15:0 wakeup filter byte mask [47:32] r/w/ nasr note 29 0000h index (in decimal): 3.32807 size: 16 bits bits description type default 15:0 wakeup filter byte mask [31:16] r/w/ nasr note 29 0000h index (in decimal): 3.32808 size: 16 bits bits description type default 15:0 wakeup filter byte mask [15:0] r/w/ nasr note 29 0000h
? 2015 microchip technology inc. ds00001926b-page 149 LAN9354 9.2.20.33 phy x mac receive addr ess a register (phy_rx_addra_x) note 30: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32865 size: 16 bits bits description type default 15:0 physical address [47:32] r/w/ nasr note 30 ffffh
LAN9354 ds00001926b-page 150 ? 2015 microchip technology inc. 9.2.20.34 phy x mac receive addr ess b register (phy_rx_addrb_x) note 31: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32866 size: 16 bits bits description type default 15:0 physical address [31:16] r/w/ nasr note 31 ffffh
? 2015 microchip technology inc. ds00001926b-page 151 LAN9354 9.2.20.35 phy x mac receive addr ess c register (phy_rx_addrc_x) note 32: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy x basic control regist er (phy_basic_control_x) is set. index (in decimal): 3.32867 size: 16 bits bits description type default 15:0 physical address [15:0] r/w/ nasr note 32 ffffh
LAN9354 ds00001926b-page 152 ? 2015 microchip technology inc. 9.2.20.36 phy x auto-negotiation mmd devices present 1 register (phy_an_mmd_present1_x) index (in decimal): 7.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b
? 2015 microchip technology inc. ds00001926b-page 153 LAN9354 9.2.20.37 phy x auto-negotiation mmd devices present 2 register (phy_an_mmd_present2_x) index (in decimal): 7.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro -
LAN9354 ds00001926b-page 154 ? 2015 microchip technology inc. 9.2.20.38 phy x eee advertisement regist er (phy_eee_adv_x) note 33: this bit is read/write (r/w). however, the user must not set this bit if eee is disabled. note 34: the default value of this field is determined by the value of the phy energy efficient ethernet enable (phy- eeeen) of the phy x edpd nlp / crossover time / eee conf iguration register (phy_edpd_cfg_x) on page 120 . if phy energy efficient ethernet enable (phyeeeen) is 0b, this field is 0b and 100base-tx eee capability is not advertised. if phy energy efficient ethernet enable (phyeeeen) is 1b, then this field is 1b and 100base-tx eee capability is advertised. index (in decimal): 7.60 size: 16 bits bits description type default 15:2 reserved ro - 1 100base-tx eee 0 = do not advertise eee capability for 100base-tx. 1 = advertise eee capability for 100base-tx. note 33 note 34 0 reserved ro -
? 2015 microchip technology inc. ds00001926b-page 155 LAN9354 9.2.20.39 phy x eee link partner adve rtisement register (phy_eee_lp_adv_x) index (in decimal): 7.61 size: 16 bits bits description type default 15:7 reserved ro - 6 10gbase-kr eee 0 = link partner does not advertise eee capability for 10gbase-kr. 1 = link partner advertises eee capability for 10gbase-kr. note: this device does not support this mode. ro 0b 5 10gbase-kx4 eee 0 = link partner does not advertise eee capability for 10gbase-kx4. 1 = link partner advertises eee capability for 10gbase-kx4. note: this device does not support this mode. ro 0b 4 10gbase-kx eee 0 = link partner does not advertise eee capability for 10gbase-kx. 1 = link partner advertises eee capability for 10gbase-kx. note: this device does not support this mode. ro 0b 3 10gbase-t eee 0 = link partner does not advertise eee capability for 10gbase-t. 1 = link partner advertises eee capability for 10gbase-t. note: this device does not support this mode. ro 0b 2 1000base-t eee 0 = link partner does not advertise eee capability for 1000base-t. 1 = link partner advertises eee capability for 1000base-t. note: this device does not support this mode. ro 0b 1 100base-tx eee 0 = link partner does not advertise eee capability for 100base-tx. 1 = link partner advertises eee capability for 100base-tx. ro 0b 0 reserved ro -
LAN9354 ds00001926b-page 156 ? 2015 microchip technology inc. 9.2.20.40 phy x vendor specific mmd 1 device id 1 register (phy_ vend_spec_mmd1_ devid1_x) index (in decimal): 30.2 size: 16 bits bits description type default 15:0 reserved ro 0000h
? 2015 microchip technology inc. ds00001926b-page 157 LAN9354 9.2.20.41 phy x vendor specific mmd 1 device id 2 register (phy_vend_spec_mmd1_devid2_x) index (in decimal): 30.3 size: 16 bits bits description type default 15:0 reserved ro 0000h
LAN9354 ds00001926b-page 158 ? 2015 microchip technology inc. 9.2.20.42 phy x vendor specific mmd 1 devices present 1 register (phy_vend_spec_mmd1_present1_x) index (in decimal): 30.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b
? 2015 microchip technology inc. ds00001926b-page 159 LAN9354 9.2.20.43 phy x vendor specific mmd 1 devices present 2 register (phy_vend_spec_mmd1_present2_x) index (in decimal): 30.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro -
LAN9354 ds00001926b-page 160 ? 2015 microchip technology inc. 9.2.20.44 phy x vendor specific mmd 1 status register (phy_vend_spec_mmd1_stat_x) index (in decimal): 30.8 size: 16 bits bits description type default 15:14 device present 00 = no device responding at this address 01 = no device responding at this address 10 = device responding at this address 11 = no device responding at this address ro 10b 13:0 reserved ro -
? 2015 microchip technology inc. ds00001926b-page 161 LAN9354 9.2.20.45 phy x vendor specific mmd 1 package id 1 register (phy_vend_spec_mmd1_pkg_id1_x) index (in decimal): 30.14 size: 16 bits bits description type default 15:0 reserved ro 0000h
LAN9354 ds00001926b-page 162 ? 2015 microchip technology inc. 9.2.20.46 phy x vendor specific mmd 1 package id 2 register (phy_vend_spec_mmd1_pkg_id2_x) index (in decimal): 30.15 size: 16 bits bits description type default 15:0 reserved ro 0000h
? 2015 microchip technology inc. ds00001926b-page 163 LAN9354 9.3 virtual phy the virtual phy provides a basic mii management interfac e (mdio) per eee 802.3 (clause 22) so that a mac with an unmodified driver can be supported as if it was attached to a single port phy. this functionality is designed to allow easy and quick integration of the device into designs with minimal driver modifications. the virtual phy provides a full bank of registers which comply with the ieee 802.3 specification. this enables the virtual phy to provide various status and control bits similar to those provided by a real phy. th ese include the output of speed se lection, duplex, loopback, iso- late, collision test, and auto-negotiation status. for a list of all virtual phy registers and related bit descriptions, refer to section 9.3.5, "virtual phy registers," on page 167 . 9.3.1 virtual phy auto-negotiation the purpose of the auto-negotiation function is to automati cally configure the virtual ph y to the optimum link parame- ters based on the capabilities of its link partner. because th e virtual phy has no actual li nk partner, the auto-negotiation process is emulated with deterministic results. auto-negotiation is enabled by setting the auto-negotiation (vphy_an) bit of the virtual phy basic control register (vphy_basic_ctrl) and is restarted by the occurrence of any of the following events: ? power-on reset (por) ? hardware reset ( rst# ) ? phy software reset (via the virtual phy reset (vphy_rst) bit of the reset control register (reset_ctl) or the reset (vphy_rst) bit of the virtual phy basic control register (vphy_basic_ctrl) ) ? setting the virtual phy basic control register (vphy_basic_ctrl) , restart auto-negotiation (vphy_rst_an) bit high ? digital reset (via the digital reset (digital_rst) bit of the reset control register (reset_ctl) ) ? issuing an eeprom loade r reload command ( section 12.4, "eeprom loader," on page 332 ) note: auto-negotiation is also restarted af ter the eeprom loader updates the straps. the emulated auto-negotiation process is much simpler than the real process and can be ca tegorized into three steps: 1. the auto-negotiation complete bit is set in the virtual phy basic status r egister (vphy_basic_status) . 2. the page received bit is set in the virtual phy auto-negotiation ex pansion register (vphy_an_exp) . 3. the auto-negotiation result (speed, duplex and pause) is determined and registered. the auto-negotiation result (speed and duplex) is dete rmined using the highest common denominator (hcd) of the virtual phy auto-negotiation adve rtisement register (vphy_an_adv) and virtual phy auto-negotiation link partner base page ability register (vphy_an_lp_base_ability) as specified in the ieee 802.3 standard. the technology ability bits of these registers are anded, and if there are multiple bits in common , the priority is determined as follows: ? 100mbps full duplex (highest priority) ? 100mbps half duplex ? 10mbps full duplex ? 10mbps half duplex (lowest priority) for example, if the full capabilities of the virtual phy ar e advertised (100mbps, full duplex), and if the link partner is capable of 10mbps and 100mbps, then auto-negotiation se lects 100mbps as the highest performance mode. if the link partner is capable of half and full-duplex modes, then auto -negotiation selects full-duplex as the highest performance operation. in the event t hat there are no bits in common, an emulated parallel detection is used. the virtual phy auto-negotiation advert isement register (vphy_an_adv) defaults to having all four ability bits set. these values can be reconfigured via software. once t he auto-negotiation is complete, any change to the virtual phy auto-negotiation advertisement register (vphy_an_adv) only takes affect when the auto-negotiation process is re- run. the emulated link partner defaul t advertised abilities in the virtual phy auto-negotiation link partner base page ability register (vphy_an_lp_base_ability) are dependent on the duplex_strap_0 and speed_strap_0 configuration straps as described in ta b l e 9 - 2 3 of section 9.3.5.6, "virtual phy auto-negotiation link partner base page ability reg- ister (vphy_an_lp_base_ability)," on page 176 . note: the duplex_strap_0 and speed_strap_0 inputs are considered to be static. auto-negotiation is not automat- ically re-evaluated if these inputs are changed. neither the virtual phy or the emulated link partner sup port next page capability, remote faults, or 100base-t4.
LAN9354 ds00001926b-page 164 ? 2015 microchip technology inc. if there is at least one common select ion between the emulated link partner and the virtual phy advertised abilities, then the auto-negotiation succeeds, the link partner auto-negotiation able bit of the virtual phy auto-negotiation expansion register (vphy_an_exp) is set, and the technology ability bits in the virtual phy auto-negotiation link partner base page ability register (vphy_an_lp_base_ability) are set to indicate the emulated link partners abil- ities. note: for the virtual phy, the auto-negotiation register bi ts (and management of such) are used by the mac driver, so the perception of local and link partner is reversed. the local device is the mac, while the link partner is the switch fabric. this is consis tent with the intention of the virtual phy. 9.3.1.1 parallel detection in the event that there are no common bits between the ad vertised ability and the emulated link partners ability, auto- negotiation fails and emulated parallel detect is used. in this case, the link partner auto-negotiation able bit in the vir- tual phy auto-negotiation expa nsion register (vphy_an_exp) will be cleared, and the communication set to half- duplex. the speed is determined by the speed_strap_0 configuration strap. only one of the technology ability bits in the virtual phy auto-negotiation li nk partner base page ability register (vphy_an_lp_base_ability) will be set, indi- cating the emulated parallel detect result. 9.3.1.2 disabling auto-negotiation auto-negotiation can be disabled in the virtual phy by clearing the auto-negotiation (vphy_an) bit of the virtual phy basic control register (vphy_basic_ctrl) . the virtual phy will then force its spee d of operation to reflect the speed ( speed select lsb (vphy_speed_sel_lsb) ) and duplex ( duplex mode (vphy_duplex) ) of the virtual phy basic control register (vphy_basic_ctrl) . the speed and duplex bits in the virtual phy basic control register (vphy_basic_ctrl) are ignored when auto-negotiation is enabled. 9.3.1.3 virtual phy pause flow control the virtual phy supports pause flow co ntrol per the ieee 802.3 sp ecification. the virtual phy?s advertised pause flow control abilities are set via the symmetric pause and asymmetric pause bits of the virtual phy auto-n egotiation adver- tisement register (vphy_an_adv) . this allows the virtual phy to advertise its flow control abilities and auto-negoti- ate the flow control settings with the emulated link partne r. the default values of these bits are as shown in section 9.3.5.5, "virtual phy auto-n egotiation advertisement regist er (vphy_an_adv)," on page 174 . the symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised pause flow control abilities of the virtual phy as indicated in the symmetric pause and asymmetric pause bits of the virtual phy auto- negotiation advertisement register (vphy_an_adv) . thus, the emulated link partner always accommodates the asymmetric/symmetric pause ability settings re quested by the virtual phy, as shown in table 9-22, ?emulated link part- ner pause flow control ability default values,? on page 177 . the pause flow control settings may also be manually set via the port 0 manual flow control register (manual_f- c_0) . this register allows the switch fabric port flow contro l settings to be manually set when auto-negotiation is dis- abled or the port 0 full-duplex manual flow control select (manual_fc_0) is set. the currently enabled duplex and flow control settings can also be monitored via this register. the flow control values in the virtual phy auto-negotiation advertisement register (vphy_an_adv) are not affected by the values of th e manual flow control register. refer to section 10.5.1, "flow control enable logic," on page 205 for additional information. 9.3.2 virtual phy in mac modes in the mac modes of operation, an external phy is connecte d to the mii interface. because there is an external phy present, the virtual phy is not needed for external configuration. however, the switch fabric mac still requires the proper duplex and flow control settings. the rmii interface also requires the proper speed setting. note: in mac modes, the virtual phy registers are accessible through their memory mapped registers via the smi or i 2 c serial management interfaces only. the virtual phy registers are not accessible through mii man- agement. 9.3.2.1 duplex in the mac modes of operation, if the auto-negotiati on (vphy_an) of the virtual phy basic control register (vphy_basic_ctrl) is set, the duplex is based on the p0_duplex pin and duplex_pol_strap_0 configuration strap. if these signals are equal, the switch fabric mac is configured for full-duplex, other wise it is set for half-duplex. the p0_- duplex pin is typically connected to the duplex indication of the external phy. the duplex is not latched since the auto- negotiation process is not used.
? 2015 microchip technology inc. ds00001926b-page 165 LAN9354 the duplex can be manually selected by clearing the auto-negotiation (vphy_an) bit and controlling the duplex mode (vphy_duplex) bit in the virtual phy basic control register (vphy_basic_ctrl) . 9.3.2.2 speed in the rmii mac mode of operation, if the auto-negotiation (vphy_an) of the virtual phy basic control register (vphy_basic_ctrl) is set, the speed is based on the p0_speed pin and speed_pol_strap_0 configuration strap. if these signals are equal, the switch fabric is configur ed for 100mbps, otherwise it is set for 10mbps. the p0_speed pin is typically connected to the speed indication of the exte rnal phy. the speed is not latched since the auto-negotiation process is not used. the speed can be manually selected by clearing the auto-negotiation (vphy_an) bit and controlling the speed select lsb (vphy_speed_sel_lsb) bit in the virtual phy basic control register (vphy_basic_ctrl) . 9.3.2.3 full-duplex flow control in the mac modes of operation, full-duplex flow contro l should be controlled manually by the host via the port 0 manual flow control register (manual_fc_0) , based on the external phys auto-negotiation results. 9.3.3 virtual phy resets in addition to the chip-level hardware reset ( rst# ) and power-on reset (por), block specific resets are supported. these are is discussed in the following sections. for detailed information on all device resets, refer to section 6.2, "resets," on page 38 . 9.3.3.1 virtual phy softwa re reset via reset_ctl the virtual phy can be reset via the reset control register (reset_ctl) by setting the virtual phy reset (vphy_rst) bit. this bit is self clearing after approximately 102 us. 9.3.3.2 virtual phy software reset via vphy_basic_ctrl the virtual phy can also be reset by setting the reset (vphy_rst) bit 15 of the virtual phy basic control register (vphy_basic_ctrl) . this bit is self clearing and will retu rn to 0 after the reset is complete. 9.3.4 virtual phy timing requirements figure 9-9: virtual phy timing mdc mdio t clkh t clkl t clkp t ohold mdio t su t ihold (data-out) (data-in) t ohold t val
LAN9354 ds00001926b-page 166 ? 2015 microchip technology inc. note 35: the virtual phy design changes output data a nominal 4 clocks (100mhz) maximum and a nominal 2 clocks (100mhz) minimum following the rising edge of mdc . note 36: the virtual phy design samples input data using the rising edge of mdc . table 9-20: virtual phy timing values symbol description min max units notes t clkp mdc period 400 - ns t clkh mdc high time 160 (80%) - ns t clkl mdc low time 160 (80%) - ns t val mdio output valid from rising edge of mdc - 300 ns note 6 t ohold mdio output hold from rising edge of mdc 10 - ns note 6 t su mdio input setup time to rising edge of mdc 10 - ns note 7 t ihold mdio input hold time after rising edge of mdc 5-ns note 7
? 2015 microchip technology inc. ds00001926b-page 167 LAN9354 9.3.5 virtual phy registers this section details the virtual phy system csrs. these regi sters provide status and control information similar to that of a real phy while maintaining ieee 802.3 compatibility. the virtual phy registers are addressable via the memory map, as described in table 5-1, ?system control and status registers,? on page 31 , as well as serially via the mii man- agement protocol (ieee 802.3 clause 22). when accessed se rially, these registers are ac cessed through the mii man- agement pins (in phy modes only) via the mii serial ma nagement protocol specified in ieee 802.3 clause 22. see section 2.0, "general description," on page 8 for a detailed description of the various device modes. when being accessed serially, the virtual phy will respond when the phy address equals the address assigned by the phy_addr_sel_strap configuration strap, as defined in section 9.1.1, "phy addressing," on page 77 . a list of all virtual phy register inde xes for serial access can be seen in ta b l e 9 - 2 1 . for virtual phy functionality and operation informa- tion, see section 9.3, "virtual phy," on page 163 . note: all virtual phy registers follow th e ieee 802.3 (clause 22.2 .4) specified mii managem ent register set. all functionality and bit definitions comply with these standa rds. the ieee 802.3 spec ified register index (in decimal) is included under the memory mapped offset of each virtual phy register as a reference. for addi- tional information, refer to the ieee 802.3 specification. note: when serially accessed, the virtual phy registers are only 16-bits wide, as is standard for mii management of phys. table 9-21: virtual phy mii seria lly addressable register index address (direct) index # (indirect) register name (symbol) 1c0h 0 virtual phy basic control register (vphy_basic_ctrl) 1c4h 1 virtual phy basic status register (vphy_basic_status) 1c8h 2 virtual phy identification msb register (vphy_id_msb) 1cch 3 virtual phy identification lsb register (vphy_id_lsb) 1d0h 4 virtual phy auto-negotiation advertisement register (vphy_an_adv) 1d4h 5 virtual phy auto-negotiation link partner base page ability register (vphy_an_lp_base_ability) 1d8h 6 virtual phy auto-negotiation ex pansion register (vphy_an_exp) 1dch 31 virtual phy special control/status register (vphy_special_control_sta- tus)
LAN9354 ds00001926b-page 168 ? 2015 microchip technology inc. 9.3.5.1 virtual phy basic control regist er (vphy_basic_ctrl) this read/write register is us ed to configure the virtual phy. offset: 1c0h size: 32 bits index (decimal): 0 16 bits bits description type default 31:16 reserved (see note 37 ) ro - 15 reset (vphy_rst) when set, this bit resets the virtual phy registers to their default state. this bit is self clearing. 0: normal operation 1: reset r/w sc 0b 14 loopback (vphy_loopback) this bit enables/disables the loopback mode. when enabled, transmissions from the external mac are not sent to the switch fabric. instead, they are looped back onto the receive path. 0: loopback mode disabled (normal operation) 1: loopback mode enabled r/w 0b 13 speed select lsb (vphy_speed_sel_lsb) this bit is used to set the speed of the virtual phy when the auto-negotia- tion (vphy_an) bit is disabled. 0: 10 mbps 1: 100/200 mbps r/w 0b 12 auto-negotiation (vphy_an) this bit enables/disables auto-n egotiation. when enabled, the speed select lsb (vphy_speed_sel_lsb) and duplex mode (vphy_duplex) bits are overridden. 0: auto-negotiation disabled 1: auto-negotiation enabled this bit is also used when in external mac modes to override the duplex and speed (for rmii mac mode) indication from the external phy. when this bit is set, the duplex and speed are determined by the input pins. when this bit is cleared, the duplex is determined by the duplex mode (vphy_duplex) bit and the speed is determined by the speed select lsb (vphy_- speed_sel_lsb) bit. r/w 1b 11 power down (vphy_pwr_dwn) this bit is not used by the virtual phy and has no effect. r/w 0b
? 2015 microchip technology inc. ds00001926b-page 169 LAN9354 note 37: the reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a dword bound- ary. when accessed serially (through the mii mana gement protocol), the r egister is 16-bits wide. note 38: the isolation does not apply to the mii management pins ( mdio ). 10 isolate (vphy_iso) this bit controls the rmii input/output pins. when set and in rmii phy mode, the output pins are not driven, pull-ups and pull-downs are disabled and the input pins are powered down and ignored. when in mac mode, this bit is ignored and has no effect. ( note 38 ) 0: non-isolated (normal operation) 1: isolated r/w 0b 9 restart auto-negotiation (vphy_rst_an) when set, this bit updates the emulated auto-negotiation results. 0: normal operation 1: auto-negotiation restarted r/w sc 0b 8 duplex mode (vphy_duplex) this bit is used to set the duplex when the auto-negotiation (vphy_an) bit is disabled. 0: half duplex 1: full duplex r/w 0b 7 collision test (vphy_col_test) this bit is not used by the virtual phy and has no effect. r/w 0b 6 speed select msb (vphy_speed_sel_msb) this bit is not used by the virtual phy and has no effect. the value returned is always 0. ro 0b 5:0 reserved ro - bits description type default
LAN9354 ds00001926b-page 170 ? 2015 microchip technology inc. 9.3.5.2 virtual phy ba sic status register (vphy_basic_status) this register is used to monito r the status of the virtual phy. offset: 1c4h size: 32 bits index (decimal): 1 16 bits bits description type default 31:16 reserved (see note 39 ) ro - 15 100base-t4 this bit displays the status of 100base-t4 compatibility. 0: phy not able to perform 100base-t4 1: phy able to perform 100base-t4 ro 0b note 40 14 100base-x full duplex this bit displays the status of 100base-x full duplex compatibility. 0: phy not able to perf orm 100base-x full duplex 1: phy able to perfor m 100base-x full duplex ro 1b 13 100base-x half duplex this bit displays the status of 100base-x half duplex compatibility. 0: phy not able to perform 100base-x half duplex 1: phy able to perform 100base-x half duplex ro 1b 12 10base-t full duplex this bit displays the status of 10base-t full duplex compatibility. 0: phy not able to perform 10base-t full duplex 1: phy able to perfor m 10base-t full duplex ro 1b 11 10base-t half duplex this bit displays the status of 10base-t half duplex compatibility. 0: phy not able to perform 10base-t half duplex 1: phy able to perform 10base-t half duplex ro 1b 10 100base-t2 full duplex this bit displays the status of 100base-t2 full duplex compatibility. 0: phy not able to perform 100base-t2 full duplex 1: phy able to perform 100base-t2 full duplex ro 0b note 40 9 100base-t2 half duplex this bit displays the status of 100base-t2 half duplex compatibility. 0: phy not able to perform 100base-t2 half duplex 1: phy able to perform 100base-t2 half duplex ro 0b note 40 8 extended status this bit displays whether extended status information is in register 15 (per ieee 802.3 clause 22.2.4). 0: no extended status information in register 15 1: extended status information in register 15 ro 0b note 41
? 2015 microchip technology inc. ds00001926b-page 171 LAN9354 note 39: the reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a dword bound- ary. when accessed serially (through the mii mana gement protocol), the r egister is 16-bits wide. note 40: the virtual phy supports 100base-x (half and full duplex) and 10base-t (half and full duplex) only. all other modes will always return as 0 (unable to perform). note 41: the virtual phy does not support register 15 or 1000 mb /s operation. thus this bi t is always returned as 0. note 42: the auto-negotiation complete bit is first cleared on a reset, but set shortly after (when the auto-negotiation process is run). refer to section 9.3.1, "virtual ph y auto-negotiation," on page 163 for additional details. note 43: the virtual phy never has remote faults, its li nk is always up, and does not detect jabber. note 44: the virtual phy supports basic and some extended regi ster capability. the virtual phy supports registers 0-6 (per the ieee 802 .3 specification). 7 reserved ro - 6 mf preamble suppression this bit indicates whether the virtua l phy accepts management frames with the preamble suppressed. 0: management frames with preamble suppressed not accepted 1: management frames with preamble suppressed accepted ro 0b 5 auto-negotiation complete this bit indicates the status of the auto-negotiation process. 0: auto-negotiation process not completed 1: auto-negotiation process completed ro 1b note 42 4 remote fault this bit indicates if a remote fault condition has been detected. 0: no remote fault condition detected 1: remote fault condition detected ro 0b note 43 3 auto-negotiation ability this bit indicates the status of the virtual phy?s auto-negotiation. 0: virtual phy is unable to perform auto-negotiation 1: virtual phy is able to perform auto-negotiation ro 1b 2 link status this bit indicates the status of the link. 0: link is down 1: link is up ro 1b note 43 1 jabber detect this bit indicates the status of the jabber condition. 0: no jabber condition detected 1: jabber condition detected ro 0b note 43 0 extended capability this bit indicates whether extended register capability is supported. 0: basic register set capabilities only 1: extended register set capabilities ro 1b note 44 bits description type default
LAN9354 ds00001926b-page 172 ? 2015 microchip technology inc. 9.3.5.3 virtual phy identificati on msb register (vphy_id_msb) this read/write register contains the msb of the virtual phy organizationally uniq ue identifier (oui). the lsb of the virtual phy oui is contained in the virtual phy identification lsb register (vphy_id_lsb) . note 45: the reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a dword bound- ary. when accessed serially (through the mii mana gement protocol), the r egister is 16-bits wide. note 46: ieee allows a value of zero in each of the 32-bits of the phy identifier. offset: 1c8h size: 32 bits index (decimal): 2 16 bits bits description type default 31:16 reserved (see note 45 ) ro - 15:0 phy id this field contains the msb of the virtual phy oui ( note 46 ). r/w 0000h
? 2015 microchip technology inc. ds00001926b-page 173 LAN9354 9.3.5.4 virtual phy identificati on lsb register (vphy_id_lsb) this read/write register contains the lsb of the virtual phy organizationally unique ident ifier (oui). the msb of the virtual phy oui is contained in the virtual phy identification msb register (vphy_id_msb) . note 47: the reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a dword bound- ary. when accessed serially (through the mii mana gement protocol), the r egister is 16-bits wide. note 48: ieee allows a value of zero in each of the 32-bits of the phy identifier. offset: 1cch size: 32 bits index (decimal): 3 16 bits bits description type default 31:16 reserved (see note 47 ) ro - 15:10 phy id this field contains the lower 6-bits of the virtual phy oui ( note 48 ). r/w 000000b 9:4 model number this field contains the 6-bit manufactu rer?s model number of the virtual phy ( note 48 ). r/w 000000b 3:0 revision number this field contain the 4-bit manufactur er?s revision number of the virtual phy ( note 48 ). r/w 0000b
LAN9354 ds00001926b-page 174 ? 2015 microchip technology inc. 9.3.5.5 virtual phy auto-negotiation advertisement register (vphy_an_adv) this read/write regist er contains the advertised ability of the virtual phy and is used in the auto-negotiation process with the link partner. offset: 1d0h size: 32 bits index (decimal): 4 16 bits bits description type default 31:16 reserved (see note 49 ) ro - 15 next page this bit determines the advertised next page capability and is always 0. 0: virtual phy does not adve rtise next page capability 1: virtual phy advertises next page capability ro 0b note 50 14 reserved ro - 13 remote fault this bit is not used since there is no physical link partner. ro 0b note 51 12 reserved ro - 11 asymmetric pause this bit determines the advertised asymmetric pause capability. 0: no asymmetric pause toward link partner advertised 1: asymmetric pause toward link partner advertised r/w note 52 10 symmetric pause this bit determines the advertised symmetric pause capability. 0: no symmetric pause toward link partner advertised 1: symmetric pause toward link partner advertised r/w note 52 9 100base-t4 this bit determines the advertised 1 00base-t4 capability and is always 0. 0: 100base-t4 ability not advertised 1: 100base-t4 ability advertised ro 0b note 53 8 100base-x full duplex this bit determines the advertised 100base-x full d uplex capability. 0: 100base-x full duplex ability not advertised 1: 100base-x full duplex ability advertised r/w 1b 7 100base-x half duplex this bit determines the advertised 100base-x half duplex capability. 0: 100base-x half duplex ability not advertised 1: 100base-x half duplex ability advertised r/w 1b
? 2015 microchip technology inc. ds00001926b-page 175 LAN9354 note 49: the reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a dword bound- ary. when accessed serially (through the mii mana gement protocol), the r egister is 16-bits wide. note 50: the virtual phy does not support next page capability. this bit value will always be 0. note 51: the remote fault bit is not useful since there is no actual link partner to send a fault to. note 52: the symmetric pause and asymmetric pause bits default to 1 if the manua l_fc_strap_0 configuration strap is low (both symmetric and asymmetric are advertised) , and 0 if the manual_fc_st rap_0 configuration strap is high. note 53: virtual 100base-t4 is not supported. note 54: the virtual phy supports only ieee 802.3. only a value of 00001b should be used in this field. 6 10base-t full duplex this bit determines the advertised 10base-t full duplex capability. 0: 10base-t full duplex ability not advertised 1: 10base-t full duplex ability advertised r/w 1b 5 10base-t half duplex this bit determines the advertise d 10base-t half duple x capability. 0: 10base-t half duplex ability not advertised 1: 10base-t half duplex ability advertised r/w 1b 4:0 selector field this field identifies the type of message being sent by auto-negotiation. 00001: ieee 802.3 r/w 00001b note 54 bits description type default
LAN9354 ds00001926b-page 176 ? 2015 microchip technology inc. 9.3.5.6 virtual phy auto-negotiation link partner base page ability register (vphy_an_lp_base_ability) this read-only register contai ns the advertised ability of the link partner?s phy and is used in the auto-negotiation pro- cess with the virtual phy. because the virtual phy does not ph ysically connect to an actual link partner, the values in this register are emulated as described below. offset: 1d4h size: 32 bits index (decimal): 5 16 bits bits description type default 31:16 reserved (see note 55 ) ro - 15 next page this bit indicates the emulated link part ner phy next page capability and is always 0. 0: link partner phy does not ad vertise next page capability 1: link partner phy advertises next page capability ro 0b note 56 14 acknowledge this bit indicates whether the link code word has been received from the partner and is always 1. 0: link code word not yet received from partner 1: link code word received from partner ro 1b note 56 13 remote fault since there is no physical link partner, this bit is not used and is always returned as 0. ro 0b note 56 12 reserved ro - 11 asymmetric pause this bit indicates the emulated link partner phy asymmetric pause capability. 0: no asymmetric pause toward link partner 1: asymmetric pause toward link partner ro note 57 10 pause this bit indicates the emulated link pa rtner phy symmetric pause capability. 0: no symmetric pause toward link partner 1: symmetric pause toward link partner ro note 57 9 100base-t4 this bit indicates the emulated link pa rtner phy 100base-t4 capability. this bit is always 0. 0: 100base-t4 ability not supported 1: 100base-t4 ability supported ro 0b note 56 8 100base-x full duplex this bit indicates the emulated link partner phy 100base-x full duplex capa- bility. 0: 100base-x full duplex ability not supported 1: 100base-x full duplex ability supported ro note 58
? 2015 microchip technology inc. ds00001926b-page 177 LAN9354 note 55: the reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a dword bound- ary. when accessed serially (through the mii mana gement protocol), the r egister is 16-bits wide. note 56: the emulated link partner does not support next page, always instantly sends its link code word, never sends a fault, and does not su pport 100base-t4. note 57: the emulated link partner?s asymme tric/symmetric pause ability is based upon the values of the asymmetric pause and symmetric pause bits of the virtual phy auto-negotiation advertisement register (vphy_an_adv) . thus the emulated link partner always accomm odates the request of the virtual phy, as shown in ta b l e 9 - 2 2 . the link partner pause ability bits are determined when auto-negotiation is complete. changing the virtual phy auto-negotiation advertis ement register (vphy_an_adv) will have no affect until the auto-negotia- tion process is re-run. if the local device advertises both sy mmetric and asymmetric pause, the result is determined based on the fd_fc_strap_0 configuration strap. this allows the user the choi ce of network emulation. if fd_f- c_strap_0 = 1, then the result is symmetrical, else asymmetrical. see section 9.3.1, "virtual phy auto- negotiation," on page 163 for additional information. 7 100base-x half duplex this bit indicates the emulated link partner phy 100base-x half duplex capability. 0: 100base-x half duplex ability not supported 1: 100base-x half duplex ability supported ro note 58 6 10base-t full duplex this bit indicates the emulated link pa rtner phy 10base-t full duplex capa- bility. 0: 10base-t full duplex ability not supported 1: 10base-t full duplex ability supported ro note 58 5 10base-t half duplex this bit indicates the emul ated link partner phy 10 base-t half duplex capa- bility. 0: 10base-t half duplex ability not supported 1: 10base-t half duplex ability supported ro note 58 4:0 selector field this field identifies the type of message being sent by auto-negotiation. 00001: ieee 802.3 ro 00001b table 9-22: emulated link partner pause flow control ability default values vphy symmetric pause (register 4.10) vphy asymmetric pause (register 4.11) fd_fc_strap_0 link partner symmetric pause (register 5.10) link partner asymmetric pause (register 5.11) no flow control enabled 00 x 00 symmetric pause 1 0 x 1 0 bits description type default
LAN9354 ds00001926b-page 178 ? 2015 microchip technology inc. note 58: the emulated link partner?s ability is based on t he duplex_strap_0 and speed_strap_0, as well as on the auto-negotiati on success. table 9-23 defines the default capabilities of the emulated link partner as a func- tion of these signals. for more information on the virtual phy auto-negotiation, see section 9.3.1, "virtual phy auto-negotiation," on page 163 . asymmetric pause towards switch 01 x 11 asymmetric pause towards mac 11 0 01 symmetric pause 1 1 1 1 1 table 9-23: emulated link partner default advertised ability duplex_strap_0 speed_strap_0 advertised link partner ability (bits 8,7,6,5) 1 0 10base-t full-duplex (0010) 1 1 100base-x full-duplex (1000) 0 0 10base-t half-duplex (0001) 0 1 100base-x half-duplex (0100) table 9-22: emulated link partner pause flow control ability default values vphy symmetric pause (register 4.10) vphy asymmetric pause (register 4.11) fd_fc_strap_0 link partner symmetric pause (register 5.10) link partner asymmetric pause (register 5.11)
? 2015 microchip technology inc. ds00001926b-page 179 LAN9354 9.3.5.7 virtual phy auto -negotiation expansion register (vphy_an_exp) this register is used in the auto-negotiation process. note 59: the reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a dword bound- ary. when accessed serially (through the mii mana gement protocol), the r egister is 16-bits wide. note 60: since the virtual phy link partner is emulated, there is never a parallel detection fault and this bit is always 0. note 61: next page ability is not supported by the virtual phy or emulated link partner. note 62: the page received bit is clear when read. it is first cleared on reset, but set shortly thereafter when the auto-negotiation process is run. note 63: the emulated link partner will show auto-negotiation able unless auto-negotiation fails (no common bits between the advertised ability and the link partner ability). offset: 1d8h size: 32 bits index (decimal): 6 16 bits bits description type default 31:16 reserved (see note 59 ) ro - 15:5 reserved ro - 4 parallel detection fault this bit indicates whether a parallel detection fault has been detected. this bit is always 0. 0: a fault hasn?t been detected via the parallel detection function 1: a fault has been detected vi a the parallel de tection function ro 0b note 60 3 link partner next page able this bit indicates whether the link partner has next page ability. this bit is always 0. 0: link partner does not contain next page capability 1: link partner contains next page capability ro 0b note 61 2 local device next page able this bit indicates whether the local device has next page ability. this bit is always 0. 0: local device does not contain next page capability 1: local device contains next page capability ro 0b note 61 1 page received this bit indicates the reception of a new page. 0: a new page has not been received 1: a new page has been received ro/lh 1b note 62 0 link partner auto -negotiation able this bit indicates the auto-negotiation ability of the link partner. 0: link partner is not auto-negotiation able 1: link partner is auto-negotiation able ro 1b note 63
LAN9354 ds00001926b-page 180 ? 2015 microchip technology inc. 9.3.5.8 virtual phy special cont rol/status register (vphy_special_control_status) this read/write register contains a current link speed/duplex indicator and sqe control. offset: 1dch size: 32 bits index (decimal): 31 16 bits bits description type default 31:16 reserved (see note 64 ) ro - 15 mode[2] see mode[1:0] below. ro note 65 14 switch loopback when set, transmissions from the switch fabric mac are not sent to the external mii port. instead, they are looped back into the switch engine. from the mac viewpoint, this is effectively a far loopback. if loopback is enabled during ha lf-duplex operat ion, then the enable receive own transmit bit in the port x mac receive configuration register (mac_rx_cfg_x) must be set for the port. otherwise, the switch fabric will ignore receive activity when transmitting in half-duplex mode. note: this mode works even if the isolate (vphy_iso) bit of the virtual phy basic control regi ster (vphy_basic_ctrl) is set. r/w 0b 13:11 reserved ro - 10 reserved ro - 9:8 mode[1:0] this field combined with mode[2] indicates the operating mode of the port. 000: reserved 001: reserved 010: rmii mac mode 011: rmii phy mode 100: reserved note: when operating in rmii modes, the drive strength of the rmii output clock is selected using the rmii clock strength bit. ro note 65 7 switch collision test when set, the collision signal to the sw itch fabric is active during transmis- sion from the switch engine. note: it is recommended that this bit be used only when using loopback mode. r/w 0b 6 rmii clock direction 0: selects px_refclk as an input 1: selects px_refclk as an output r/w nasr note 69 note 66 5 rmii clock strength for rmii mac and phy modes, a low selects 12 ma drive while a high selects a 16 ma drive. r/w nasr note 69 note 67
? 2015 microchip technology inc. ds00001926b-page 181 LAN9354 note 64: the reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a dword bound- ary. when accessed serially (through the mii mana gement protocol), the r egister is 16-bits wide. note 65: the default value of this fi eld is determined via the p0_mode_strap[1:0] configuration straps. refer to sec- tion 7.2, "hard-straps," on page 63 for additional information. note 66: the default value of this field is determined via the p0_rmii_clock_dir_strap configuration strap. refer to section 7.2, "hard-straps," on page 63 for additional information. note 67: the default value of this field is determined via the p0_clock_strength_strap configuration strap. refer to section 7.2, "hard-straps," on page 63 for additional information. note 68: the default value of this field is the resu lt of the auto-negotiation process if the auto-negotiation (vphy_an) bit of the virtual phy basic control r egister (vphy_basic_ctrl) is set. otherwise, this field reflects the speed select lsb (vphy_speed_sel_lsb) and duplex mode (vphy_duplex) bit settings of the virtual phy basic control register (vphy_basic_ctrl) . refer to section 9.3.1, "virtual phy auto- negotiation," on page 163 for information on the auto-negotiation determination process of the virtual phy. note 69: register bits designated as nasr are reset wh en the virtual phy reset is generated via the reset control register (reset_ctl) . the nasr designation is only applicable when the reset (vphy_rst) bit of the virtual phy basic control re gister (vphy_basic_ctrl) is set. 4:2 current speed/duplex indication this field indicates the current speed and duplex of the virtual phy link. ro note 68 1:0 reserved ro - bits description type default [4] [3] [2] speed duplex 0 0 0 reserved 0 0 1 10mbps half-duplex 0 1 0 100mbps half-duplex 0 1 1 reserved 1 0 0 reserved 1 0 1 10mbps full-duplex 1 1 0 100mbps full-duplex 1 1 1 reserved
-page 182 ? 2015 microchip technology inc. 10.0 switch fabric 10.1 functional overview the switch fabric contains a 3-port vlan layer 2 switch engine that supports untagged, vlan tagged and priority tagged frames. the switch fabric provi des an extensive feature set which includes spanning tree protocol support, mul- ticast packet filtering and quality of service (qos) packet pr ioritization by vlan tag, dest ination address, port default value or diffserv/tos, allowing for a range of prioritization implementations. 32k of buffer ram allows for the storage of multiple packets while forwarding operations are comple ted and a 512 entry forwarding table provides room for mac address forwarding tables. each port is allocated a cluster of 4 dynamic qos queues which allow each queue size to grow and shrink with traffic, effectivel y utilizing all available memory. this memory is managed dynamically via the buffer manager block within the switch fabric. all aspects of the switch fabric are managed via the switch fabric configura- tion and status registers (csr), whic h are indirectly accessible via the system control and status registers. the switch fabric consists of these major blocks: ? switch fabric control and status registers - these registers provide access to various switch fabric parameters for configuration and monitoring. ? 10/100 ethernet mac - a total of three macs are included in the switch fabric which provide basic 10/100 ether- net functionality for each switch fabric port. ? switch engine (swe) - this block is the core of the switch fabric and provides vlan layer 2 switching for all three switch ports. ? buffer manager (bm) - this block provides control of the free buffer space, transmit queues and scheduling. ? switch fabric interface logic - this block provides some auxil iary registers and interfaces the switch fabric con- trol and status registers to the rest of the device. it also enables the flow control functions based on various set- tings and port conditions. refer to figure 2-1: internal block diagram on page 9 for details on the interconnection of the switch fabric blocks within the device. 10.2 10/100 ethernet mac the switch fabric contains three 10/100 mac blocks, one fo r each switch port (0,1,2). the 10/100 mac provides the basic 10/100 ethernet functionality, in cluding transmission deferral and collision back-off/retry, receive/transmit fcs checking and generation, receive/transmit pause flow control and transmit back pressure. the 10/100 mac also includes rx and tx fifos and per port statistic counters. 10.2.1 receive mac the receive mac (ieee 802.3) su blayer decomposes ethernet packets acquired via the internal mii interface by strip- ping off the preamble sequence and start of frame delimiter (sfd). the receiv e mac checks the fcs, the mac control type and the byte count against the dr op conditions. the packet is stored in the rx fifo as it is received. the receive mac determines the validity of each received packet by checking the type field, fcs and oversize or undersize conditions. all bad packets will be either imm ediately dropped or marked (at the end) as bad packets. oversized packets are normally truncated at 1519 or 1523 (vlan tagged) octets and marked as erroneous. the mac can be configured to accept packets up to 2048 octets (inclu sive), in which case the over size packets are truncated at 2048 bytes and marked as erroneous. undersized packets are defined as packets with a length less than the minimum packet size. the minimum packet size is defined to be 64 bytes, exclusive of preamble seq uence and sfd, regardless of the occurrence of a vlan tag. the fcs and length/type fields of the frame are checked to detect if the packet has a valid mac control frame. when the mac receives a mac control frame with a valid fcs and determines the operation code is a pause command (flow control frame), the mac will load its internal pause counter with the number_of_slots variable from the mac control frame just received. anytime the internal pause counter is zero, the transmit mac will be allowed to transmit (xon). if the internal pause counter is not zero, the receive mac will not allow the transmit mac to transmit (xoff). when the transmit mac detects an xoff conditi on it will continue to transmit the current packet, terminating transmission after the current packet has been transmitted until receiving the xon condition from the receive mac. the pause counter will begin to decrement at the end of the current transmission or immediately if no transmission is underway. if another pause command is received while the transmitter is already in pause, the new pause time indicated by the flow control
? 2015 microchip technology inc. -page 183 packet will be loaded into the pause counter. the pause function is enabled by either auto-negotiation or manually as discussed in section 10.5.1, "flow control enable logic," on page 205 . pause frames are consumed by the mac and are not sent to the switch engi ne. non-pause control frames are optionally filtered or forwarded. note: to meet the ieee 802.1 filterin g database requirements, the mac address of 01-80-c 2-00-00-01 should be added into the alr address table as filtering entr ies by either eeprom sequence or by software. when the receive fifo is full and additional data continue s to be received, an overrun condition occurs and the frame is discarded (fifo space recovered) or marked as a bad frame. the receive mac can be disabled from receiving all frames by clearing the rx enable (rxen) bit of the port x mac receive configuration register (mac_rx_cfg_x) . for information on mac eee f unctionality, refer to section 10.2.3, "ieee 802.3az energy efficient ethernet," on page 184 . 10.2.1.1 rece ive counters the receive mac gathers statistics on each packet and increments the related counter registers. the following receive counters are supported for each switch fabric port. refer to table 10-9, ?indirectly accessi ble switch control and status registers,? on page 225 and section 10.7.2.3 through section 10.7.2.22 for detailed descriptions of these counters. ? total undersized packets ( section 10.7.2.3, on page 240 ) ? total packets 64 bytes in size ( section 10.7.2.4, on page 240 ) ? total packets 65 through 127 bytes in size ( section 10.7.2.5, on page 241 ) ? total packets 128 through 255 bytes in size ( section 10.7.2.6, on page 241 ) ? total packets 256 through 511 bytes in size ( section 10.7.2.7, on page 242 ) ? total packets 512 through 1023 bytes in size ( section 10.7.2.8, on page 242 ) ? total packets 1024 through maximum bytes in size ( section 10.7.2.9, on page 243 ) ? total oversized packets ( section 10.7.2.10, on page 243 ) ? total ok packets ( section 10.7.2.11, on page 244 ) ? total packets with crc errors ( section 10.7.2.12, on page 244 ) ? total multicast packets ( section 10.7.2.13, on page 245 ) ? total broadcast packets ( section 10.7.2.14, on page 245 ) ? total mac pause packets ( section 10.7.2.15, on page 246 ) ? total fragment packets ( section 10.7.2.16, on page 246 ) ? total jabber packets ( section 10.7.2.17, on page 247 ) ? total alignment errors ( section 10.7.2.18, on page 247 ) ? total bytes received from all packets ( section 10.7.2.19, on page 248 ) ? total bytes received from good packets ( section 10.7.2.20, on page 248 ) ? total packets with a symbol error ( section 10.7.2.21, on page 249 ) ? total mac control packets ( section 10.7.2.22, on page 249 ) ? total number of rx lpis received ( section 10.7.2.23, on page 250 ) ? total time in rx lpi state ( section 10.7.2.24, on page 250 ) 10.2.2 transmit mac the transmit mac generates an ethernet mac frame from tx fifo data. this includes generating the preamble and sfd, calculating and appending the frame checksum value, optionally padding undersize packets to meet the minimum packet requirement size (64 bytes) and maintaining a standard inter-frame gap time during transmit. the transmit mac can operate at 10/100mbps, half or full-dup lex and with or without flow control depending on the state of the transmission. in half-duplex m ode, the transmit mac meets csma/cd ieee 802.3 requirements. the transmit mac will re-transmit if collisions occur during the first 64 by tes (normal collisions) or will discard the packet if collisions occur after the first 64 bytes (late collisions). the transm it mac follows the standard tr uncated binary exponential back- off algorithm, collision and jamming procedures. the transmit mac pre-pends the standar d preamble and sfd to every packet from the fifo. the transmit mac also follows, as default, the standard inter-f rame gap (ifg). the default ifg is 96 bit times and can be adjusted via the ifg config field of the port x mac transmit configur ation register (mac_tx_cfg_x) .
-page 184 ? 2015 microchip technology inc. packet padding and cyclic redundant code (fcs) calculation may be optionally performed by the transmit mac. the auto-padding process automatically adds enough zeros to packets shorter than 64 bytes. the auto-padding and fcs generation is controlled via the tx pad enable bit of the port x mac transmit configur ation register (mac_tx_cf- g_x) . when in full-duplex mode, the transmit mac uses the flow-control algorithm sp ecified in ieee 802.3. mac pause frames are used primarily for flow control packets, which pass si gnaling information between stations. mac pause frames have a unique type of 8808h and a pause op-code of 0001h. the mac pause frame contains the pause value in the data field. the flow control manager will auto-adapt the procedure based on traffic volume and speed to avoid packet loss and unnecessary pause periods. when in half-duplex mode, the mac uses a back pressure al gorithm. the back pressure algorithm is based on a forced collision and an aggressive back-off algorithm. for information on mac eee f unctionality, refer to section 10.2.3, "ieee 802.3az energy efficient ethernet," on page 184 . 10.2.2.1 transm it counters the transmit mac gathers statistics on each packet and increm ents the related counter regi sters. the following transmit counters are supported for each switch fabric port. refer to table 10-9, ?indirectly accessi ble switch control and status registers,? on page 225 and section 10.7.2.29 through section 10.7.2.46 for detailed descriptions of these counters. ? total packets deferred ( section 10.7.2.29, on page 255 ) ? total pause packets ( section 10.7.2.30, on page 255 ) ? total ok packets ( section 10.7.2.31, on page 256 ) ? total packets 64 bytes in size ( section 10.7.2.32, on page 256 ) ? total packets 65 through 127 bytes in size ( section 10.7.2.33, on page 257 ) ? total packets 128 through 255 bytes in size ( section 10.7.2.34, on page 257 ) ? total packets 256 through 511 bytes in size ( section 10.7.2.35, on page 258 ) ? total packets 512 through 1023 bytes in size ( section 10.7.2.36, on page 258 ) ? total packets 1024 through maximum bytes in size ( section 10.7.2.37, on page 259 ) ? total undersized packets ( section 10.7.2.38, on page 259 ) ? total bytes transmitted from all packets ( section 10.7.2.39, on page 260 ) ? total broadcast packets ( section 10.7.2.40, on page 260 ) ? total multicast packets ( section 10.7.2.41, on page 261 ) ? total packets with a late collision ( section 10.7.2.42, on page 261 ) ? total packets with excessive collisions ( section 10.7.2.43, on page 261 ) ? total packets with a single collision ( section 10.7.2.44, on page 262 ) ? total packets with multiple collisions ( section 10.7.2.45, on page 262 ) ? total collision count ( section 10.7.2.46, on page 262 ) ? total number of tx lpis generated ( section 10.7.2.47, on page 263 ) ? total time in tx lpi state ( section 10.7.2.48, on page 263 ) 10.2.3 ieee 802.3az energy efficient ethernet the device supports energy efficient ethernet (eee) in 100 mbps mode as defined in the most recent version of the ieee 802.3az standard. 10.2.3.1 tx lpi generation the process of when the mac should indicate lpi re quests to the phy is divided into two sections: ? client lpi requests to mac ? mac lpi request to phy
? 2015 microchip technology inc. -page 185 client lpi requests to mac when the tx fifo is empty for a ti me (in microseconds) specified in port x eee tx lpi re quest delay register (eee_tx_lpi_req_delay_x) , a tx lpi request is asserted to the mac. a setting of 0 us is possible for this time. if the tx fifo becomes not empty while the timer is running, th e timer is reset (i.e . empty time is not cumulative). once tx lpi is requested and the tx fifo become s not empty, the tx lpi request is negated. the tx fifo empty timer is reset if energy efficient ethernet (eee_enable) in the port x mac transmit configuration register (mac_tx_cfg_x) is cleared. tx lpi requests are asserted only if the energy efficient ethernet (eee_enable) bit is set, and when appropriate, if the current speed is 100 mbps, the current duplex is full and t he auto-negotiation result indicates that both the local and partner device support eee 100 mbps. in or der to prevent an unstable link conditi on, the phy link status also must indi- cate ?up? for one second before lpi is requested. these tests for the allowance of tx lpi are done in the switch fabric interface logic block. see section 10.5.2, "eee enable logic," on page 207 for further details. tx lpi requests are asserted even if the tx enable (txen) bit in the port x mac transmit configuration register (mac_tx_cfg_x) is cleared. mac lpi request to phy lower power idle (lpi) is requested by the mac to the phy using the mii value of txen=0, txer=1, txd[3:0]=4?b0001. the mac always finishes the current packet before signaling tx lpi to the phy. the mac will generate tx lpi requests to the phy even if the tx enable (txen) bit in the port x mac transmit con- figuration register (mac_tx_cfg_x) is cleared. 802.3az specifies the usage of a simplified full duplex mac with carrier sense deferral. ba sically this means that once the tx lpi request to the phy is de-asserted , the mac will defer the time specified in port x eee time wait tx system register (eee_tw_tx_sys_x) in addition to the normal ipg before sending a frame. tx lpi counters the mac maintains a counter, eee tx lpi transitions , that counts the number of times that tx lpi request to the phy changes from de-asserted to asserted. the counter is not wr itable and does not clear on read. the counter is reset if the energy efficient ethernet (eee_enable) bit in the port x mac transmit configuration register (mac_tx_cfg_x) is low. the mac maintains a counter, eee tx lpi time , that counts (in microseconds) the amount of time that tx lpi request to the phy is asserted. note that this counte r does not include the time specified in the port x eee time wait tx system register (eee_tw_tx_sys_x) . the counter is not writable and does not clear on read. the counter is reset if the energy efficient ethernet (eee_enable) bit in the port x mac transmit configur ation register (mac_tx_cfg_x) is low. 10.2.3.2 rx lpi detection receive lower power idle (lpi) is indicated by the ph y to the mac using the mii value of rxdv=0, rxer=1, txd[3:0]=4?b0001. decoding lpi the mac will decode the lpi indication only when energy efficient ethernet (eee_enable) is set in the port x mac transmit configuration register (mac_tx_cfg_x) , and when appropriate, the curr ent speed is 100mbs, the current duplex is full and the auto-negotiation result indicates that both the local and partner de vice supports eee at 100mbs. in order to prevent an unstable link condition, the phy link status also must indicate ?up? for one second before lpi is decoded. these tests for the allowance of tx lpi are done in the switch fabric interface logic block. see section 10.5.2, "eee enable logic," on page 207 for further details. the mac will decode the lpi indication even if rx enable (rxen) in the port x mac receive configuration register (mac_rx_cfg_x) is cleared.
-page 186 ? 2015 microchip technology inc. rx lpi counters the mac maintains a counter, eee rx lpi transitions , that counts the number of time s that the lpi indication from the phy changes from de-asserted to asserted. the counter is not writable and does not clear on read. the counter is reset if the energy efficient ethernet (eee_enable) bit in the port x mac transmit configuration register (mac_tx_cf- g_x) is low. the mac maintains a counter, eee rx lpi time , that counts (in microseconds) the am ount of time that the phy indi- cates lpi. the counter is not writable and does not clear on read. the counter is reset if the energy efficient ethernet (eee_enable) bit in the port x mac transmit configuration register (mac_tx_cfg_x) is low. 10.3 switch engine (swe) the switch engine (swe) is a vlan layer 2 (link layer) switching engine supporting 3 ports. the swe supports the following types of frame formats: untagged frames, vlan t agged frames and priority tagged frames. the swe supports both the 802.3 and ether net ii frame formats. the swe provides the control for all forwarding/filtering rule s. it handles the address learning and aging and the desti- nation port resolution based upon the mac address and vlan of the packet. the swe implements the standard bridge port states for spanning tree and provides packet metering for input rate control. it also implements port mirroring, broad- cast throttling and multicast pruning and filtering. packet priorities are suppor ted based on the ipv4 tos bits and ipv6 traffic class bits using a diffserv table mapping, the non-diffserv mapped ipv4 precedence bits, vlan priority using a per port priority regeneration tabl e, da based static priority and traffi c class mapping to one of 4 qos transmit priority queues. the following sections detail the va rious features of the switch engine. 10.3.1 mac address lookup table the address logic resolution (alr) maintains a 512 entry mac address table. the alr searches the table for the destination mac address. if the search finds a match, the as sociated data is returned indicating the destination port or ports, whether to filter the packet, the packet?s priority (u sed if enabled) and whether to override the ingress and egress spanning tree port state. figure 10-1 displays the alr table entry structure. refer to the switch engine alr write data 0 register (swe_alr_wr_dat_0) and the switch engine alr write data 1 register (swe_alr_wr_dat_1) for detailed descriptions of these bits. 10.3.1.1 learning/aging/migration the alr adds new mac addresses upon ingress along with the associated receive port. if the source mac address already exists, the entry is refreshed. this action se rves two purposes. fi rst, if the source port has changed due to a network reconfiguration (migrati on), it is updated. second, each instance the entry is refreshed, the age status bits are set, keeping the ent ry active. learning can be disabled per port via the enable learn- ing on ingress field of the switch engine port ingress configurat ion register (swe_port_ingrss_cfg) . during each aging period, the alr scans the learned mac addresses. for entries which have an age status greater than 0, the alr decrements the age. as mentioned above, if a mac address is subsequent ly refreshed, the age status bits will be set again and the process would repeat. if a le arned entry already had its age status bits decremented to 0 (by previous scans), the alr will instead remove the learne d entry. four scans need to occur for a mac address to be aged and removed. since the first scan could occur immediately following the add or refresh of an entry, an entry will be aged and removed after a minimum of 3 age periods and a maximum of 4 age periods. the minimum aging time is programmable using the aging time field of the switch engine alr configuration register (swe_alr_cfg) in 1 second increments from 1 second to approx imately 69 minutes. the maximum aging time is 33% higher. figure 10-1: alr table entry structure 57 age 1 / override valid 58 static 56 age 0 / filter 55 priority port 50 49 48 mac address 47 0 ... bit 53 52 51 54 priority enable
? 2015 microchip technology inc. -page 187 the alr age test bit in the switch engine alr configuration register (swe_alr_cfg) changes the aging time from seconds to milliseconds. aging can be disabled by clearing the alr age enable field of the switch engine alr configuration register (swe_al- r_cfg) . 10.3.1.2 static entries if a mac address entry is manually added by the host cpu, it can be (and typically is) marked as static . static entries are not subjected to the aging process. static entries also cannot be changed by the learning process (including migra- tion). 10.3.1.3 multicast pruning the destination port that is re turned as a result of a destination mac addr ess lookup may be a single port or any com- bination of ports. the latter is used to setup multicast address groups. an entry with a multicast mac address would be entered manually by the host cpu with the appr opriate destination port(s). typically, the static bit should also be set to prevent automatic aging of the entry. 10.3.1.4 broadcast entries if desired, the host cpu can manually add the broadcast a ddress of 0xffffffffffff. this feature is enabled by set- ting the allow broadcast entries field of the switch engine alr configurat ion register (swe_alr_cfg) . typically, the static bit should also be set in the alr entry to prevent automatic aging of the entry. 10.3.1.5 addres s filtering filtering can be performed on a destination mac address. su ch an entry would be entered manually by the host cpu with the filter bit active. typically, the static bit should also be set to prev ent automatic aging of the entry. note: to meet the ieee 802.1 filteri ng database requirements, the mac addresses of 01-80-c2-00-00-01 through 01-80-c2-00-00-0f should be added into t he alr address table as filtering entries by either eeprom sequence or by software. the mac address of 01-80-c2-00-00 -00 is typically added as a for- warding entry to direct bpdu frames to the host cpu. 10.3.1.6 spanning tree port state override a special spanning tree port state override setting can be applied to mac address entries. when the host cpu manually adds an entry with both the static and age 1/override bits set, packets with a matching destination address will bypass the spanning tree port state (except the di sabled state) and will be forwarded. this feature is typically used to allow the reception of the bpdu packets while a port is in the non-forwarding state. refer to section 10.3.5, "spanning tree sup- port," on page 193 for additional details. 10.3.1.7 mac destination address lookup priority if enabled, globally via the da highest priority field in the switch engine global ingress configuration register (swe_- global_ingrss_cfg) along with the, per entry, priority enable bi t, the transmit priority for mac address entries is taken from the associated data of that entry. 10.3.1.8 alr result override results from the alr destination mac lookup can be overridden on a per port basis. this feature is enabled by setting the appropriate alr override enable bit in the switch engine alr override register (swe_alr_override) . when enabled, the destination port from the al r destination mac address lookup is re placed with the appropriate alr over- ride destination field in the switch engine alr override register (swe_alr_override) . the alr spanning tree override, static, filter and priority results for the destination mac address are still used. note: forwarding rules described in section 10.3.2 are still followed. 10.3.1.9 host access note: refer to section 10.7.3.1, on page 265 through section 10.7.3.6, on page 272 for detailed definitions of the registers. add, delete, and modify entries
-page 188 ? 2015 microchip technology inc. the alr contains a learning engine that is used by the host cpu to add, delete and modify the mac address table. this engine is accessed by using the switch engine alr command register (swe_alr_cmd) , the switch engine alr command status register (swe_alr_cmd_sts) , the switch engine alr write data 0 register (swe_al- r_wr_dat_0) and the switch engine alr write data 1 register (swe_alr_wr_dat_1) . the following procedure should be followed in or der to add, delete and modify the alr entries: 1. write the switch engine alr write data 0 register (swe_alr_wr_dat_0) and the switch engine alr write data 1 register (swe_alr_wr_dat_1) with the desired mac address and control bits. an entry can be deleted by setting the valid bit to 0. 2. set the make entry bit in the switch engine alr command register (swe_alr_cmd) . 3. poll the operation pending bit in the switch engine alr command status register (swe_alr_cmd_sts) until it is cleared. read entries the alr contains a search engine that is used by the host to read the mac address table. this engine is accessed by using the switch engine alr command register (swe_alr_cmd) , the switch engine alr command status regis- ter (swe_alr_cmd_sts) , switch engine alr read data 0 register (swe_alr_rd_dat_0) and the switch engine alr read data 1 register (swe_alr_rd_dat_1) . note: the entries read are not necessarily in the same order as they were learned or manually added. the following procedure should be followed in order to read the alr entries: 1. set the get first entry bit in the switch engine alr command register (swe_alr_cmd) . 2. poll the operation pending bit in the switch engine alr command status register (swe_alr_cmd_sts) until it is cleared. 3. if the valid bit in the switch engine alr read data 0 register (swe_alr_rd_dat_0) is set, then the entry is valid and the data from the switch engine alr read data 0 register (swe_alr_rd_dat_0) and the switch engine alr read data 1 register (swe_alr_rd_dat_1) can be stored. 4. if the end of table bit in the switch engine alr read data 0 register (swe_alr_rd_dat_0) is set, then exit. 5. set the get next entry bit in the switch engine alr command register (swe_alr_cmd) . 6. go to step 3. 10.3.2 forwarding rules upon ingress, packets are filtered or forwarded based on the following rules: ? if the destination port equals the source port (local traffic), the packet is filtered. (this rule is for a destination mac address which is found in the alr table and the alr result indicates a single destination port.) ? if the source port is in the disabled state, via the switch engine port state register (swe_port_state) , the packet is filtered. ? if the source port is in the learning or listening / blocking state, via the switch engine port state register (swe_port_state) , the packet is filtered (unless the spanning tree port state override is in effect). ? if the packet is a multicast packet and it is identified as a igmp or mld packet and igmp/mld monitoring is enabled (respectively), via the switch engine global ingress configuration register (swe_global_in- grss_cfg) , the packet is redirected to the igmp/mld monitor port(s). this check is not done on special tagged packets from the host cpu port when an alr lookup is not requested. refer to section 10.3.10.1, "packets from the host cpu," on page 199 for additional information. ? if the destination port is in the disabled state, via the switch engine port state register (swe_port_state) , the packet is filtered. (this rule is for a destination mac address which is found in the alr table and the alr result indicates a single destination port. when there are multip le destination ports or when the mac address is not found, the packet is sent to only those ports that are in th e forwarding state. this rule is also suppressed if alr result override is enabled. ? if the destination port is in the learning or listening / blocking state, via the switch engine port state register (swe_port_state) , the packet is filtered (unless the spanning tree port state override is in effect). (this rule is for a destination mac address which is found in the alr table and the alr result indicates a single destination port. when there are multiple destination ports or when the ma c address is not found, the packet is sent to only those ports that are in the forwarding state. this rule is also suppressed if alr result override is enabled.) ?if the age 0/filter bit for the destination address is set in the alr table, the packet is filtered. ? if the packet has a unicast destination mac address which is not found in the alr table and the drop unknown field in the switch engine global ingress configurat ion register (swe_global_ingrss_cfg) is set, the
? 2015 microchip technology inc. -page 189 packet is filtered. ? if the packet has a multicast destination mac addres s which is not found in the alr table and the filter multicast field in the switch engine global ingress configuration register (swe_global_ingrss_cfg) is set, the packet is filtered. ? if the packet has a broadcast destination mac address an d the broadcast storm control level has been reached, the packet is discarded. ?if the drop on yellow field in the buffer manager configuration register (bm_cfg) is set, the packet is colored yellow and randomly selected, it is discarded. ?if the drop on red field in the buffer manager configuration register (bm_cfg) is set and the packet is colored red, it is discarded. ? if the destination address was not found in the alr tabl e (an unknown or a broadcast) and the broadcast buffer level is exceeded, the packet is discarded. ? if there is insufficient buffer space, the packet is discarded. ? if the destination address was not found in the alr table (an unknown or a broadcast) or the destination address was found in the alr table with the alr result indicating multiple destination ports and the port forward states resulted in zero valid destination ports, the packet is filtered. ? for cases where the packet is not filtered, the alr override enable bit in the switch engine alr override regis- ter (swe_alr_override) is checked for the source port and, if set, the packet is redirected to the specified override destination. when the switch is enabled for vlan support, these following rules also apply: ? if the packet is untagged or priority tagged and the admit only vlan field in the switch engine admit only vlan register (swe_admt_only_vlan) for the ingress port is set, the packet is filtered. ? if the packet is tagged and has a vid equal to fffh, it is filtered. ?if enable membership checking field in the switch engine port ingress conf iguration register (swe_port_in- grss_cfg) is set, admit non member field in the switch engine admit non member register (swe_ad- mt_n_member) is cleared and the source port is not a member of the incoming vlan, the packet is filtered. ?if enable membership checking field is set and the destination port is not a member of the incoming vlan, the packet is filtered. (this rule is for a destination mac address which is found in the alr table and the alr result indicates a single destination port. wh en there are multiple destination ports or when the mac address is not found, the packet is sent to only those ports that are members of the vlan. this rule is also suppressed if alr result override is enabled.) ? if the destination address was not found in the alr ta ble (an unknown or broadcast) or the destination address was found in the alr table with the alr result indicati ng multiple destination ports and the vlan broadcast domain containment resulted in zero valid destination ports, the packet is filtered. ? for the last three cases, if the vid is not in the vlan table, the vlan is considered foreign and the membership result is null. a null membership will result in the packet being filtered if enable membership checking is set. a null membership will also result in the packet being filt ered if the destination address is not found in the alr table (since the packet would have no destinations). 10.3.3 transmit prio rity queue selection the transmit priority queue may be select ed from five options. as shown in figure 10-2 , the priority may be based on: ? the static value for the destination address in the alr table ? the precedence bits in the ipv4 tos octet ? the diffserv mapping table indexed by the ipv4 tos octet or the ipv6 traffic class octet ? the vlan tag priority field using the per port priority regeneration table ? the port default with separate values for packet s with or without a broadca st destination address.
-page 190 ? 2015 microchip technology inc. all options are sent through the traffic class table which ma ps the selected priority to one of the four output queues. the transmit queue priority is based on the packet type and device configuration as shown in figure 10-3 . refer to sec- tion 10.7.3.17, "swit ch engine global ingress configuration register (swe_global_ingrss_cfg)," on page 283 for definitions of the configuration bits. figure 10-2: switch engine transmit queue selection priority calculation programmable diffserv table programmable port default table programmable priority regeneration table per port 3b 3b 3b 2b 6b 3b 3b static da override packet is tagged vl higher priority packet is ipv4 packet is ip use precedence use ip alr priority enable bit ipv4(tos) ipv6(tc) da highest priority priority queue source port alr priority vlan priority ipv4 precedence 2b 3b use tag packet is from host programmable traffic class table packet is broadcast programmable port default bc table 3b
? 2015 microchip technology inc. -page 191 figure 10-3: switch engine transmit queue calculation da highest priority alr priority enable bit y y resolved priority = priority regen[vlan priority] n packet is ipv4/v6 & use ip resolved priority = ip precedence y use precedence y n resolved priority = diffserv[tc] n n y use tag & packet is tagged y n resolved priority = default priority[source port] wait for alr result queue = traffic class[resolved priority] packet is ipv4 resolved priority = diffserv[tos] y n get queue done vl higher priority use tag & packet is tagged n y get queue packet from host n y resolved priority = alr priority resolved priority = default bc priority[source port] packet is broadcast n n y
-page 192 ? 2015 microchip technology inc. 10.3.3.1 port default priority as detailed in figure 10-3 , the default priority is based on the ingress port?s priority bits in its port vid value. separate values exist for packets with or without a broadcast desti nation address. the pvid table is read and written by using the switch engine vlan command register (swe_vlan_cmd) , the switch engine vlan write data register (swe_vlan_wr_data) , the switch engine vlan read data register (swe_vlan_rd_data) and the switch engine vlan command status register (swe_vlan_cmd_sts) . refer to section 10.7.3.9, on page 276 through section 10.7.3.12, on page 281 for detailed vlan register descriptions. 10.3.3.2 ip precedence based priority the transmit priority queue can be chosen based on the precedenc e bits of the ipv4 tos octet. this is supported for tagged and non-tagged packets for both type field and length field encapsulations. the precedence bits are the three most significant bits of the ipv4 tos octet. 10.3.3.3 diffserv based priority the transmit priority queue can be chosen based on the di ffserv usage of the ipv4 tos or ipv6 traffic class octet. this is supported for tagged and non-tagged packets for both type field and length field encapsulations. the diffserv table is used to determine the packet priority from the 6-bit differentiated services (ds) field. the ds field is defined as the six most significant bits of the ipv4 tos octet or the ipv6 traffic class octet and is used as an index into the diffserv table. the output of the diffserv table is then used as the priority. this priority is then passed through the traffic class table to select the transmit priority queue. note: the diffserv table is not initialized upon reset or power-up. if diffserv is enabled, then the full table must be initialized by the host. the diffserv table is read and written by using the switch engine diffserv table command register (swe_diff- serv_tbl_cfg) , the switch engine diffserv table write data register (swe_diffserv_tbl_wr_data) , the switch engine diffserv table read data register (swe_diffserv_tbl_rd_data) and the switch engine diff- serv table command status register (swe_diffserv_tbl_cmd_sts) . refer to section 10.7.3.13, on page 281 through section 10.7.3.16, on page 282 for detailed diffserv register descriptions. 10.3.3.4 vlan priority as detailed in figure 10-3 , the transmit priority queue can be taken from the priority field of the vlan tag. the vlan priority is sent through a per port priority regeneration table, which is used to map the vlan priority into a user defined priority. the priority regeneration tabl e is programmed by using the switch engine port 0 ingress vlan priority regeneration table register (swe_ingrss_regen_tbl_0) , the switch engine port 1 ingress vlan priority regeneration table register (swe_ingrss_regen_tbl_1) and the switch engine port 2 ingress vlan priority regeneration table register (swe_ingrss_regen_tbl_2) . refer to section 10.7.3.34, on page 296 through section 10.7.3.36, on page 298 for detailed descriptions of these registers. 10.3.4 vlan support the switch engine supports 16 active vlans out of a poss ible 4096. the vlan table contains the 16 active vlan entries, each consisting of t he vid, the port membership and un-tagging instructions. figure 10-4: vlan table entry structure 17 16 15 14 13 12 vid 11 0 ... un-tag mii member mii un-tag port 1 member port 1 un-tag port 2 member port 2
? 2015 microchip technology inc. -page 193 on ingress, if a packet has a vlan tag containing a valid vid (not 000h or fffh), the vid ta ble is searched. if the vid is found, the vlan is considered active and the membership and un-tag instruction is used. if the vid is not found, the vlan is considered foreign and the membership result is null. a null membership will result in the packet being filtered if enable membership checking is set. a null membership will also result in the packet being filtered if the des- tination address is not found in the alr table (since the packet would have no destinations). on ingress, if a packet does not have a vlan tag or if the vlan tag contains vid with a value of 0 (priority tag), the packet is assigned a vlan based on the port default vid (pvid) and priority. the pvid is then used to access the above vlan table. the usage of the pvid can be forced by setting the 802.1q vlan disable field in the switch engine global ingress configuration r egister (swe_global_ingrss_cfg) , in effect creating port based vlans. the vlan membership of the packet is used for ingress and egress checking and for vlan broadcast domain contain- ment. the un-tag instructions are used at egress on ports defined as hybrid ports. refer to section 10.7.3.9, on page 276 through section 10.7.3.12, on page 281 for detailed vlan register descriptions. 10.3.5 spanning tree support hardware support for the spanning tree protocol (stp) an d the rapid spanning tree protocol (rstp) includes a per port state register as well as the override bit in the mac address table entries ( section 10.3.1.6, on page 187 ) and the host cpu port special tagging ( section 10.3.10, on page 199 ). the switch engine port state register (swe_port_state) is used to place a port into one of the modes as shown in table 10-1 . normally only port 1 and port 2 are placed into mo des other than forwarding. po rt 0, which is connected to the host cpu, should normally be left in forwarding mode. table 10-1: spanning tree states port state hardware action software action 11 - disabled received packets on the port are always discarded. transmissions to the port are always blocked. learning on the port is disabled. the host cpu may attempt to send packets to the port in this state, but they will not be transmitted. 01 - blocking received packets on the port are dis- carded unless overridden. transmissions to the port are blocked unless overridden. learning on the port is disabled. the mac address table should be programmed with entries that the host cpu needs to receive (e.g., the bpdu address). the static and age 1/ override bits should be set. the host cpu may send packets to the port in this state. only packets with stp override will be trans- mitted. there is no hardware distinction between the block- ing and listening states. 01 - listening received packets on the port are dis- carded unless overridden. transmissions to the port are blocked unless overridden. learning on the port is disabled. the mac address table should be programmed with entries that the host cpu needs to receive (e.g., the bpdu address). the static and age 1/ override bits should be set. the host cpu may send packets to the port in this state. only packets with stp override will be trans- mitted.
-page 194 ? 2015 microchip technology inc. 10.3.6 ingress flow metering and coloring hardware ingress rate limiting is supported by metering packet streams and marking packets as either green, yellow or red according to th ree traffic parameters: committed information rate (cir) , committed burst size (cbs) and excess burst size (ebs). a packet is marked green if it does not e xceed the cbs, yellow if it exceeds to cbs but not the ebs or red otherwise. ingress flow metering and coloring is enabled via the ingress rate enable field in the switch engine ingress rate con- figuration register (s we_ingrss_rate_cfg) . once enabled, each incoming packet is classified into a stream. streams are defined as per port (3 streams), per priority (8 st reams) or per port & priority (24 streams) as selected via the rate mode field in the switch engine ingress rate configur ation register (swe_ingrss_rate_cfg) . each stream can have a different cir setting. all streams sh are common cbs and ebs settings. cir, cbs and ebs are programmed via the switch engine ingress rate comma nd register (swe_ingrss_rate_cmd) and the switch engine ingress rate write data register (swe_ingrss_rate_wr_data) . each stream is metered according to rfc 2697. at the rate set by the cir, two token buckets are credited per stream. first, the committed burst bucket is incremented up to the maximum set by the cbs. on ce the committed burst bucket is full, the excess burst bucket is incremented up to the ma ximum set by the ebs. the cir rate is specified in time per byte. the value programmed is in approximately 20 ns per byte increments. typical values are listed in table 10-2 . when a port is receiving at 10 mbps, any setting fast er than 39 has the effect of not limiting the rate. 10 - learning received packets on the port are dis- carded unless overridden. transmissions to the port are blocked unless overridden. learning on the port is enabled. the mac address table should be programmed with entries that the host cpu needs to receive (e.g., the bpdu address). the static and age 1/ override bits should be set. the host cpu may send packets to the port in this state. only packets with stp override will be trans- mitted. 00 - forwarding received packets on the port are for- warded normally. transmissions to the port are sent nor- mally. learning on the port is enabled. the mac address table should be programmed with entries that the host cpu needs to receive (e.g., the bpdu address). the static and age 1/ override bits should be set. the host cpu may send packets to the port in this state. table 10-2: typical ingress rate settings cir setting time per byte bandwidth 0-3 80 ns 100 mbps 4 100 ns 80 mbps 5 120 ns 67 mbps 6 140 ns 57 mbps 7 160 ns 50 mbps 9 200 ns 40 mbps 12 260 ns 31 mbps 19 400 ns 20 mbps 39 800 ns 10 mbps table 10-1: spanning tree states (continued) port state hardware action software action
? 2015 microchip technology inc. -page 195 after each packet is received, the bucket is decremented. if t he committed burst bucket has sufficient tokens, it is deb- ited and the packet is colored green. if the committed burst bucket lacks suffic ient tokens for the packet, the excess burst bucket is checked. if the excess burs t bucket has sufficient tokens, it is debited, the packet is colored yellow and is subjected to random discard. if t he excess burst bucket lacks suff icient tokens for the pack et, the packet is colored red and is discarded. note: all of the token buckets are initialized to the default value of 1536. if lower values are programmed into the cbs and ebs parameters, the token buckets will need to be normally depleted below these values before the values have any effect on limiting the maximum value of the token buckets. refer to section 10.7.3.26, on page 291 through section 10.7.3.30, on page 294 for detailed register descriptions. 10.3.6.1 ingress flow calculation based on the flow monitoring mode, an ingress flow definition can include the ingress priority. this is calculated similarly to the transmit queue with the e xception that the traffic class table is not used. as shown in figure 10-2 , the priority can be based on: ? the static value for the destination address in the alr table ? the precedence bits in the ipv4 tos octet ? the diffserv mapping table indexed by the ipv4 tos octet or the ipv6 traffic class octet ? the vlan tag priority field using the per port priority regeneration table ? the port default with separate values for packet s with or without a broadca st destination address. 79 1600 ns 5 mbps 160 3220 ns 2.5 mbps 402 8060 ns 1 mbps 804 16100 ns 500 kbps 1610 32220 ns 250 kbps 4028 80580 ns 100 kbps 8056 161140 ns 50 kbps table 10-2: typical ingress rate settings cir setting time per byte bandwidth
-page 196 ? 2015 microchip technology inc. figure 10-5: switch engine in gress flow priority selection priority calculation programmable diffserv table programmable port default table programmable priority regeneration table per port 3b 3b 3b 2b 6b 3b 3b static da override packet is tagged vl higher priority packet is ipv4 packet is ip use precedence use ip alr priority enable bit ipv4(tos) ipv6(tc) da highest priority flow priority source port alr priority vlan priority ipv4 precedence 3b 3b use tag packet is from host packet is broadcast programmable port default bc table 3b
? 2015 microchip technology inc. -page 197 the ingress flow calculation is based on the packe t type and the device configuration as shown in figure 10-6 . figure 10-6: switch engine ingr ess flow priority calculation da highest priority alr priority enable bit y y flow priority = priority regen[vlan priority] n packet is ipv4/v6 & use ip flow priority = ip precedence y use precedence y n flow priority = diffserv[tc] n n y use tag & packet is tagged y n flow priority = default priority[source port] wait for alr result packet is ipv4 flow priority = diffserv[tos] y n vl higher priority use tag & packet is tagged n y get queue packet from host n y flow priority = alr priority get flow priority done flow priority = default bc priority[source port] packet is broadcast n n y
-page 198 ? 2015 microchip technology inc. 10.3.7 broadcast storm control in addition to ingress rate limiting, the device supports har dware broadcast storm control on a per port basis. this fea- ture is enabled via the switch engine broadcast throttling register (swe_bcst_throt) . the allowed rate per port is specified as the number of bytes mu ltiplied by 64 allowed to be received every 1.72 ms interval. packets that exceed this limit are dropped. typical values are listed in table 10-3 . when a port is receiving at 10 mbps, any setting above 34 has the effect of not limiting the rate. in addition to the rate limit, the buffer manager broadcast buffer level register (bm_bcst_lvl) specifies the maxi- mum number of buffers that can be used by broadcasts, multicasts and unknown unicasts. 10.3.8 ipv4 igmp / ipv6 mld support the device provides internet group m anagement protocol (igmp) and multic ast listener discovery (mld) hardware support using two mechanisms: igmp/ml d monitoring and multicast pruning. on ingress, if the enable igmp monitoring field in the switch engine global ingress configuration register (swe_- global_ingrss_cfg) is set, igmp multicast packets are trapped and redirected to the mld/igmp monitor port (typ- ically set to the port to which the host cpu is connected) . igmp packets are identified as ipv4 packets with a protocol of 2. both ethernet and ieee 802.3 frame forma ts are supported as are vlan tagged packets. on ingress, if the enable mld monitoring field in the switch engine global ingress configuration register (swe_- global_ingrss_cfg) is set, mld multicast packets are trapped and redirected to the mld/igmp monitor port (typ- ically set to the port to which the host cpu is connected) . mld packets are identified as ipv6 packets with a next header value or a hop-by-hop next header value of 58 decimal (icmpv6). optionally, via the enable other mld next headers field in the switch engine global ingress configur ation register (swe _global_ingrss_cfg) , ipv6 next header values or hop-by-hop next header values of 43 (r outing), 44 (fragment), 50 (esp) , 51 (ah) and 60 (destination options) can be enabled. optionally, via the enable any mld hop-by-hop next header field in the switch engine global ingress configuration register (swe_global_ingrss_cfg) , all hop-by-hop next header values can be enabled. both ethernet and ieee 802.3 frame formats are supported as are vlan tagged packets. note: there is a limitation with packets using the ieee 802. 3 frame format. for single and double (such as in the case of a cpu tag and vlan tag) tagged packets, th e hop-by-hop next header value can not be reached within the 64 byte processing limit and therefore would not be detected. once the igmp or mld packets are received by the host cpu, the host software can decide which port or ports need to be members of the multicast group. this group is then added to the alr table as detailed in section 10.3.1.3, "mul- ticast pruning," on page 187 . the host software should also forward the original igmp or mld packet if necessary. table 10-3: typical br oadcast rate settings broadcast throttle level bandwidth 252 75 mbps 168 50 mbps 134 40 mbps 67 20 mbps 34 10 mbps 17 5 mbps 8 2.4 mbps 4 1.2 mbps 3 900 kbps 2 600 kbps 1 300 kbps
? 2015 microchip technology inc. -page 199 normally, packets are never transmitted back to the receiv ing port. for igmp/mld monitoring, this may optionally be enabled via the allow monitor echo field in the switch engine global ingress c onfiguration register (swe_- global_ingrss_cfg) . this function would be used if the monitori ng port wished to participate in the igmp/mld group without the need to perform special handling in the transmit portion of the driver software. note: most forwarding rules are skipped when a packet is mo nitored. however, a packet is still filtered if: ? the source port is in the disabled state. ? the source port is in the learning or listening / blocking state (unless spanning tree port state override is in effect. ? vlans are enabled, the packet is untagged or priority tag ged and the admit only vlan bit for the ingress port is set. ? vlans are enabled and the packet is tagged and had a vid equal to fffh. ? vlans are enabled, enable membership checking on in gress is set, admit non member is cleared and the source port is not a member of the incoming vlan. 10.3.9 port mirroring the device supports port mirroring where packets received or transmitted on a port or ports can also be copied onto another ?sniffer? port. port mirroring is configured using the switch engine port mirroring register (swe_port_mirror) . multiple mirrored ports can be defined, but only one sniffer port can be defined. when receive mirroring is enabled via the enable rx mirroring field, packets that are forwarded from a port designated as a mirrored port are also transmitted by the sniffer port . for example, port 2 is setup to be a mirrored port and port 0 is setup to be the sniffer port. if a packet is received on port 2 with a destination of port 1, it is forwarded to both port 1 and port 0. when transmit mirroring is enabled via the enable tx mirroring field, packets that are fo rwarded to a port designated as a mirrored port are also transmitted by the sniffer port . for example, port 2 is setup to be a mirrored port and port 0 is setup to be the sniffer port. if a packet is received on port 1 with a destination of port 2, it is forwarded to both port 2 and port 0. a packet will never be transmitted out of the receiving port. a re ceive packet is not normally mirro red if it is filtered. this can optionally be enabled via the enable rx mirroring filtered field. 10.3.10 host cpu port special tagging the switch engine ingress port type register (swe_ingrss_port_typ) and the buffer manager egress port type register (bm_egrss_port_type) are used to enable a special vlan tag that is used by the host cpu. this special tag is used to specify the port(s) where packets from t he cpu should be sent and to indicate which port received the packet that was forwarded to the cpu. 10.3.10.1 packets fr om the host cpu the switch engine ingress port type register (swe_ingrss_port_typ) configures t he switch to use the special vlan tag in packets from the host cpu as a destination port indicator. a setting of 11b s hould be used on the port that is connected to the host cpu (typically port 0). a se tting of 00b should be used on the normal network ports. the special vlan tag is a normal vlan tag where the vid field is used as the destination port indicator. vid bit 3 indicates a request for an alr lookup. if vid bit 3 is zero, then bits 0 and 1 s pecify the destination port (0, 1, 2) or broad cast (3). bit 4 is used to specify if th e stp port state should be overridden. when set, the packet will be transmitted, even if the de stination port(s) is (are) in the learning or listening / blocking state. if vid bit 3 is one, then the normal alr lookup is performe d and learning is performed on the source address (if enabled in the switch engine port ingress configur ation register (swe_port_ingrss_cfg) and the port state for the cpu port is set to forwarding or learning). the stp port state override is taken from the alr entry. vid bit 5 indicates a request to calculate the packet prio rity (and egress queue) based on the packet contents. if vid bit 5 is zero, the pri field from t he vlan tag is used as the packet priority. if vid bit 5 is one, the packet priority is calculat ed from the packet contents. the procedure described in section 10.3.3, "transmit priority queue selection," on page 189 is followed with the exception that the special tag is skipped and the vlan priority is taken from the second vlan tag, if it exists.
-page 200 ? 2015 microchip technology inc. vid bit 6 indicates a request to follow vlan rules. if vid bit 6 is zero, a default membership of ?all ports? is assumed and no vlan rules are followed. if vid bit 6 is one, all ingress and egress vlan rules are followed. the procedure described in section 10.3.2, "for- warding rules," on page 188 is followed with the exception that the specia l tag is skipped and the vid is taken from the second vlan tag if it exists. upon egress from the destination port(s), the special tag is removed. if a regular vlan tag needs to be sent as part of the packet, then it should be part of the packet data from the host cpu following the special tag. when specifying port 0 as the destination port, the vid will be set to 0. a vid of 0 is normally considered a priority tagged packet. such a packet will be filtered if admit only vlan is set on the host cpu port. either avoid setting admit only vlan on the host cpu port or set an unused bit in the vid field. note: the maximum size tagged packet that can normally be se nt into a switch port (o n port 0) is 1522 bytes. since the special tag consumes four bytes of the packet length, the out going packet is limited to 1518 bytes, even if it contains a regular vlan tag as part of th e packet data. if a larger outgoing packet is required, the jumbo2k bit in the port x mac receive configuration register (mac_rx_cfg_x) of port 0 should be set. 10.3.10.2 packets to the host cpu the buffer manager egress port type register (bm_egrss_port_type) configures the switch to add the special vlan tag in packets to the host cpu as a source port indica tor. a setting of 11b should be used only on the port that is connected to the host cpu (typically port 0). other se ttings can be used on the normal network ports as needed. the special vlan tag is a normal vlan tag where: ? the priority field indicates the packet? s priority as classified on receive. ? bits 0 and 1 of the vid field specify the source port (0, 1 or 2). ? bit 3 of the vid field indicates the packet was a monitored igmp or mld packet. ? bit 4 of the vid field indicates stp override was set ( static and age 1/override bits set) in the alr entry for the packet?s destination mac address. ? bit 5 of the vid field indicates the static bit was set in the alr entry for the packet?s destination mac address. ? bit 6 of the vid field indicates priority enable was set in the alr entry for th e packet?s destination mac address. ? bits 7, 8 and 9 of the vid field are the priority field in the alr entry for the packet?s destination mac address - these can be used as a tag to identify different pa cket types (ptp, rstp, etc.) when the host cpu adds mac address entries. note: bits 4 through 9 of the vid field will be all zero for destination mac addresses t hat have been learned (i.e., not added by the host) or are not found in the al r table (i.e., not learned or added by the host). upon egress from the host cpu port, the special tag is added. if a regular vlan tag already exists, it is not deleted. instead it will follow the special tag. 10.3.11 counters a counter is maintained per port that c ontains the number of mac address that we re not learned or were overwritten by a different address due to mac address table space limitat ions. these counters are accessible via the following regis- ters: ? switch engine port 0 learn discard count register (swe_lrn_discrd_cnt_0) ? switch engine port 1 learn discard count register (swe_lrn_discrd_cnt_1) ? switch engine port 2 learn discard count register (swe_lrn_discrd_cnt_2) a counter is maintained per port that contains the number of packets filtered at ingress. this count includes packets filtered due to broadcast thro ttling, but does not include packets dropped due to ingress rate limiting. these counters are accessible via the following registers: ? switch engine port 0 ingress filtered count register (swe_filtered_cnt_0) ? switch engine port 1 ingress filtered count register (swe_filtered_cnt_1) ? switch engine port 2 ingress filtered count register (swe_filtered_cnt_2)
? 2015 microchip technology inc. -page 201 10.4 buffer manager (bm) the buffer manager (bm) provides control of the free buffer space, the multiple priority transmit queues, transmission scheduling and packet dropping. vlan tag insertion and removal is also performed by the buffer manager. the follow- ing sections detail the various f eatures of the buffer manager. 10.4.1 packet buffer allocation the packet buffer consists of 32 kb of ram that is dynamica lly allocated in 128 byte blo cks as packets are received. up to 16 blocks may be used per packet, depending on the packet le ngth. the blocks are linked together as the packet is received. if a packet is filtered, dropped or contains a receive error, the buffers are reclaimed. 10.4.1.1 buffer limits and flow control levels the bm keeps track of the amount of buffers used per each ingress port. these counts are used to generate flow control (half-duplex backpressure or full-duplex pause frames) and to limit the amount of buffer space that can be used by any individual receiver (hard drop limit). the flow control and dr op limit thresholds are dynamic and adapt based on the cur- rent buffer usage. based on the number of active receiving ports, the drop level and flow control pause and resume thresholds adjust between fixed settings and two user programmable levels via the buffer manager drop level register (bm_drop_lvl) , the buffer manager flow control pause level register (bm_fc_pause_lvl) and the buffer man- ager flow control resume level register (bm_fc_resume_lvl) respectively. the bm also keeps a count of the number of buffers that are queued for multiple ports (broadcast queue). this count is compared against the buffer manager broadcast buffer level register (bm_bcst_lvl) and if the configured drop level is reached or exceeded, subsequent packets are dropped. 10.4.2 random early discard (red) based on the ingress flow monitoring detailed in section 10.3.6, "ingress flow metering and coloring," on page 194 , packets are colored as green, yellow or red. packets colored red are always discarded if the drop on red bit in the buffer manager configuration register (bm_cfg) is set. if the drop on yellow bit in the buffer manager configuration register (bm_cfg) is set, packets colored yellow are randomly discarded based on the moving average number of buffers used by the ingress port. the probability of a discard is programmable into the random discard weight table via the buffer manager random discard table command register (bm_rndm_dscrd_tbl_cmd) , the buffer manager random discard table write data register (bm_rndm_dscrd_tbl_wdata) and the buffer manager random discard table read data register (bm_rndm_dscrd_tbl_rdata) . the random discard weight table contains sixteen entries, each 10-bits wide. each entry corresponds to a range of the average number of buffers used by the ingress port. entry 0 is for 0 to 15 buffers, entry 1 is for 16 to 31 buffers, etc. the probability fo r each entry is set in 1/1024. for example, a setting of 1 is 1-in-1024 or approximately 0.1%. a setting of all ones (1023) is 1023-in-1024 or approximately 99.9%. refer to section 10.7.4.10, "buffer manag er random discard table command register (bm_rndm_dscrd_t- bl_cmd)," on page 307 for additional details on writing and read ing the random discard weight table. 10.4.3 transmit queues once a packet has been completely received, it is queued fo r transmit. there are four queues per transmit port, one for each level of transmit priority. each queue is virtual (if ther e are no packets for that port/priority, the queue is empty) and dynamic (a queue may have any length if there is enough memory space). when a packet is read from the memory and sent out to the corresponding port, the used buffers are released. 10.4.4 transmit prio rity queue servicing when a transmit queue is non-empty, it is serviced and the packet is read from the buffer ram and sent to the transmit mac. if there are multiple queues that require servicing, one of two methods may be used: fixed priority ordering or weighted round-robin ordering. if the fixed priority queue servicing bit in the buffer manager configuration register (bm_cfg) is set, a strict order, fixed priority is selected. tr ansmit queue 3 has the highest priority, followed by 2, 1 and 0. if the fixed priority queue servicing bit in the buffer manager configuration register (bm_cfg) is cleared, a weighted round-robin order is followed. assuming all four qu eues are non-empty, the servic e is weighted with a 9:4:2:1 ratio (queue 3,2,1,0). the servicing is blended to avoid burstiness (e.g., queue 3, then queue 2, then queue 3, etc.).
-page 202 ? 2015 microchip technology inc. 10.4.5 egress rate limiting (leaky bucket) for egress rate limiting, the leaky bucket algorithm is used on each output priority queue. for each output port, the band- width that is used by each priority qu eue can be limited. if any egress queue rece ives packets faster than the specified egress rate, packets will be accumulated in the packet memory. after the memory is used, packet dropping or flow con- trol will be triggered. egress rate limiting occurs before the transmit priority queue servicing , such that a lower priority queue will be serviced if a higher priority queue is being rate-limited. the egress limiting is enabled per priority queue. after a packet is selected to be sent, its length is recorded. the switch then waits a programmable amount of time, scaled by the pa cket length, before servicin g that queue once again. the amount of time per byte is programmed into the buffer manager egress rate registers (refer to section 10.7.4.14 through section 10.7.4.19 for detailed register definitions). the value pr ogrammed is in approximately 20 ns per byte increments. typical values are listed in table 10-4 . when a port is transmitting at 10 mbps, any setting above 39 has the effect of not limiting the rate. note 1: these are the unlimited max. bandwidths when ifg and preamble are taken into account. 10.4.6 adding, removing and changing vlan tags based on the port configuration and the received packet forma t, a vlan tag can be added to, removed from or modified in a packet. there are four received packet type cases: non-tagged, priority-tagged, normal-tagged and cpu special- tagged. there are also four possible settings for an egress po rt: dumb, access, hybrid and cpu. in addition, each vlan table entry can specify the removal of the vlan tag (the entry?s un-tag bit). the tagging/un-tagging rules are specified as follows: ? dumb port - this port type generally does not change the tag. - when a received packet is non-tagged, priority-tagged or normal-tagged the packet passes untouched. - when a packet is received special-tagged from a cpu port, the special tag is removed. ? access port - this port type generally does not support tagging. - when a received packet is non-tagged, the packet passes untouched. - when a received packet is priority-tagged or normal-tagged, the tag is removed. table 10-4: typical egress rate settings egress rate setting time per byte bandwidth @ 64 byte packet bandwidth @ 512 byte packet bandwidth @ 1518 byte packet 0-3 80 ns 76 mbps ( note 1 )96 mbps ( note 1 ) 99 mbps ( note 1 ) 4 100 ns 66 mbps 78 mbps 80 mbps 5 120 ns 55 mbps 65 mbps 67 mbps 6 140 ns 48 mbps 56 mbps 57 mbps 7 160 ns 42 mbps 49 mbps 50 mbps 9 200 ns 34 mbps 39 mbps 40 mbps 12 260 ns 26 mbps 30 mbps 31 mbps 19 400 ns 17 mbps 20 mbps 20 mbps 39 800 ns 8.6 mbps 10 mbps 10 mbps 78 1580 ns 4.4 mbps 5 mbps 5 mbps 158 3180 ns 2.2 mbps 2.5 mbps 2.5 mbps 396 7940 ns 870 kbps 990 kbps 1 mbps 794 15900 ns 440 kbps 490 kbps 500 kbps 1589 31800 ns 220 kbps 250 kbps 250 kbps 3973 79480 ns 87 kbps 98 kbps 100 kbps 7947 158960 ns 44 kbps 49 kbps 50 kbps
? 2015 microchip technology inc. -page 203 - when a received packet is special-tagged fr om a cpu port, the special tag is removed. ? cpu port - packets transmitted from this port type generally contain a special tag. special tags are described in detail in section 10.3.10, "host cpu port special tagging," on page 199 . ? hybrid port - generally, this port type supports a mix of normal-tagged and non-tagged packets. it is the most complex, but most flexible port type. for clarity, the following details the incoming un-tag instruction. as described in section 10.3.4, "vlan support," on page 192 , the un-tag instruction is the thr ee un-tag bits from the applicable ent ry in the vlan table. the entry in the vlan table is either the vlan from t he received packet or the ingress port?s default vid. when a received packet is non-tagged, a new vlan tag is a dded if two conditions are met. first, the insert tag bit for the egress port in the buffer manager egress port ty pe register (bm_egrss_port_type) must be set. second, the un-tag bit, for the egress port, from the un-tag instruction asso ciated with the ingress port?s default vid, must be cleared. the vlan tag that is added will ha ve a vid taken from either the ingress or egress port?s default vid. the priority of the vlan tag is either the priority calculated on ingress or the egress port?s default. the choice of ingress or egress is determined by th e egress port?s vid/priority select bit in the buffer manager egress port type register (bm_egrss_port_type) . when a received packet is priority-tagged, either the tag is removed or it is modified. if the un-tag bit, for the egress port, from the un-tag instruction associated with the ingress port?s default vid is set, then the tag is removed. otherwise, the tag is modifi ed. the vid of the new vlan tag is ch anged to either the ingress or egress port?s default vid. if the change priority bit in the buffer manager egress port type register (bm_egrss_port_type) for the egress port is set, then the priority field of the new vlan tag is also changed. the priority of the vlan tag is either the priority calculated on ingress or the egress port?s default. the choice of ingress or egress is determined by the egress port?s vid/priority select bit. when a received packet is normal-tagged, either the tag is removed, modified or passed unchanged. if the un-tag bit, for the egress port, from the un-tag instruction associat ed with the vid in the rece ived packet is set, then the tag is removed. else, if the change tag bit in the buffer manager egress port type register (bm_egrss_port_type) for the egress port is clear, the packet passes untouched. else, if both the change vlan id and the change priority bits in the buffer manager egress port ty pe register (bm_egrss_port_- type) for the egress port are clear, the packet passes untouc hed. otherwise, the tag is modified. if the change vlan id bit for the egress port is set, the vid of the new vlan tag is changed to either the ingress or egress port?s default vid. if the change priority bit for the egress po rt is set, the priority field of the new vlan tag is changed to either the priority calculated on ingress or the egress port?s default. the choice of ingress or egress is determined by the egress port?s vid / priority select bit. when a packet is received special-tagged from a cpu port, the special tag is removed.
-page 204 ? 2015 microchip technology inc. hybrid tagging is summarized in figure 10-7 . the default vlan id and priority of each port may be configured via the following registers: ? buffer manager port 0 default vlan id and priority register (bm_vlan_0) ? buffer manager port 1 default vlan id and priority register (bm_vlan_1) ? buffer manager port 2 default vlan id and priority register (bm_vlan_2) figure 10-7: hybrid port tagging and un-tagging insert tag [egress_port] default vid [ingress_port] un-tag bit y non-tagged y add tag vid = default vid [ingress_port or egress port*] priority = ingress priority or default priority [egress_port]* y send packet untouched n priority tagged default vid [ingress_port] un-tag bit y strip tag n normal tagged received vid un-tag bit y strip tag change tag [egress_port] n n send packet untouched y change priority [egress_port] modify tag vid = default vid [ingress_port or egress port*] priority = ingress priority or default priority [egress_port]* n change vlan id [egress_port] change priority [egress_port] change priority [egress_port] y n n modify tag vid = default vid [ingress port or egress_port*] priority = ingress priority or default priority [egress_port]* y modify tag vid = default vid [ingress port or egress_port*] priority = unchanged n y modify tag vid = unchanged priority = ingress priority or default priority [egress_port]* special tagged strip tag modify tag vid = default vid [ingress_port or egress port*] priority = unchanged n receive tag type *choosen by vid / priority select bit *choosen by vid / priority select bit *choosen by vid / priority select bit *choosen by vid / priority select bit *choosen by vid / priority select bit *choosen by vid / priority select bit
? 2015 microchip technology inc. -page 205 10.4.7 counters a counter is maintained per port that co ntains the number of packets dropped due to buffer space limits and ingress rate limit discarding (red and random yellow dropping). these counters are accessible via the following registers: ? buffer manager port 0 drop count register (bm_drp_cnt_src_0) ? buffer manager port 1 drop count register (bm_drp_cnt_src_1) ? buffer manager port 2 drop count register (bm_drp_cnt_src_2) a counter is maintained per port that contains the number of packets dropped due solely to ingress rate limit discarding (red and random yellow dropping). this count value can be subtracted from the drop coun ter, as described above, to obtain the drop counts due solely to buffer space limits. th e ingress rate drop counters are accessible via the following registers: ? buffer manager port 0 ingress rate drop count register (bm_rate_drp_cnt_src_0) ? buffer manager port 1 ingress rate drop count register (bm_rate_drp_cnt_src_1) ? buffer manager port 2 ingress rate drop count register (bm_rate_drp_cnt_src_2) 10.5 switch fabric interface logic 10.5.1 flow cont rol enable logic each switch fabric port (0,1,2) is provided with two flow control enable inputs, one for transmission and one for recep- tion. flow control on transmission allows the transmitter to generate back pressure in half-duplex mode and pause pack- ets in full-duplex. flow control in reception enables the reception of pause packets to pause transmissions. the state of these enables is based on the state of the port?s duplex and auto-ne gotiation settings and results, provided by the attached phy. for port 0, the phy is the virtual phy. for port 1, the ph y is physical phy a. for port 2, the phy is physical phy b. the phys? advertised pause flow contro l abilities are set via the symmetric pause and asymmetric pause bits of the phys? auto-negotiation advertisement register. this allows the phy to advertise its flow control abil- ities and auto-negotiate the flow control settings with its li nk partner. the link partners? advertised pause flow control abilities are returned via the symmetric pause and asymmetric pause bits of the phys? auto-negotiation link partner base ability register. the pause flow control settings may also be ma nually set via the manual flow control registers ( port 1 manual flow control register (manual_fc_1) , port 2 manual flow control register (manual_fc_2) or port 0 manual flow con- trol register (manual_fc_0) ). table 10-5 details the switch fabric flow control enable logic. these registers allow the switch fabric ports flow control settings to be manually se t when auto-negotiation is disabled or the respective manual flow control select bit is set. the currently enabled duplex a nd flow control settings can al so be monitored via these reg- isters. when in half-duplex mode, the transmit flow control (back pressure) enable is determined directly by the bp_en_x bit of the port?s manual flow control register. when auto-negotia tion is disabled or the manual_fc_x bit of the port?s man- ual flow control register is set, the switch port flow c ontrol enables during full-duplex are determined by the tx_fc_x and rx_fc_x bits of the port?s manual flow control register. when auto-negotiation is enabled and the manual_fc_x bit is cleared, the switch port flow control enables during full-duplex are determined by auto-negotiation. note: the flow control values in the phys? auto-negotiation advertisement register are not affected by the values of the manual flow control register.
-page 206 ? 2015 microchip technology inc. note 2: if auto-negotiation is enabled and complete, but the link partner is not auto-negotiation capable, half-duplex is forced via the parallel detect function. note 3: these are the bits from the phys? auto-negotiation advertisement and auto-negotiation link partner base ability registers. if a switch fabric port is connec ted to a virtual phy, these are the local/partner swapped outputs from the virtual phy?s auto-negotiation ad vertisement and auto-negotiation link partner base ability registers. refer to the virtual phy au to-negotiation section for more information. per ta b l e 1 0 - 5 , the following cases are possible: ? case 1 - auto-negotiation is still in progress. since the resu lt is not yet established, flow control is disabled. ? case 2 - auto-negotiation is enabled and unsuccessful (link partner not auto-negotiation capable). the link part- ner ability is undefined, effectively a don? t-care value, in this case. the duplex setting will default to half-duplex in this case. flow control is determined by the bp_en_x bit. ? case 3 - auto-negotiation is enabled and successful with half -duplex as a result. the link partner ability is unde- fined since it only applies to full-duplex operatio n. flow control is determined by the bp_en_x bit. ? cases 4-11 -auto-negotiation is enabled and successful with full- duplex as the result. in these cases, the adver- tisement registers a nd the link partner ability cont rols the rx and tx enables. these cases match ieee 802.3 annex 28b.3. - cases 4,5,6,8,10 - no flow control enabled - case 7 - asymmetric pause towards partner (away from switch port) - case 9 - symmetric pause table 10-5: switch fabric flow control enable logic case manual_fc_x an enable an complete lp an able duplex an pause advertisement ( note 3 ) an asym pause advertisement ( note 3 ) lp pause ability ( note 3 ) lp asym pause ability ( note 3 ) rx flow control enable tx flow control enable -1xxxhalf xxxx0 bp_en_x -x0xxhalf xxxx0 bp_en_x -1xxxfull xxxx rx_fc_x tx_fc_x -x0xxfull xxxx rx_fc_x tx_fc_x 1010x x xxxx0 0 20 1 1 0half ( note 2 ) xxxx0 bp_en_x 30111half xxxx0 bp_en_x 40 1 1 1 full 0 0 x x 0 0 50 1 1 1 full 0 1 0 x 0 0 60111full 011000 70111full 011101 80 1 1 1 full 1 0 0 x 0 0 90111full 1x1x11 100111 full 1 1 0 0 0 0 110111 full 1 1 0 1 1 0
? 2015 microchip technology inc. -page 207 - case 11 - asymmetric pause from partner (towards switch port) 10.5.2 eee enable logic each switch fabric port (0,1,2) is provided with an inpu t which permits the generation and decoding of eee lpi signal- ing. these signals are in addition to the switch fabric ports? energy efficient ethernet (eee_enable) bits and are used to check various port conditions such as speed, duplex and mode. normally, in order to permit eee function s, the port must be in internal phy mode or mii mac mode, the port speed must be 100 mbps, the current duplex must be full and the auto -negotiation result must indica te that both the local and partner device support eee 100 mbps. in order to prevent an uns table link cond ition, the phy link stat us also must indi- cate ?up? for one second. 10.5.2.1 port 0 port 0 does not perform eee function s when in rmii mac or phy modes. 10.5.2.2 port 1 the port speed, duplex, link status and auto- negotiation result come from physical phy a. 10.5.2.3 port 2 the port speed, duplex, link status and auto- negotiation result come from physical phy b. 10.5.3 switch fabric csr interface the switch fabric csrs provid e register level access to th e various parameters of the switch fabric. switch fabric related registers can be classi fied into two main categories based upon their method of access: direct and indirect. the directly accessible switch fabr ic registers are part of the main system csrs and are detailed in section 10.6, "switch fabric interface logic registers," on page 210 . these registers provide switch fabric manual flow control (ports 0-2), data/command registers (for access to the indi rect switch fabric register s) and switch mac address con- figuration. the indirectly accessible switch fabric registers reside within the switch fabric and must be accessed indirectly via the switch fabric csr interface da ta register (switch_csr_data) and the switch fabric csr interface command register (switch_csr_cmd) or the set of switch fabric csr interface direct data registers (switch_csr_di- rect_data) . the indirectly accessible switch fabric csrs provid e full access to the many configurable parameters of the switch engine, buffer manager and each swit ch port. the switch fabric csrs are detailed in section 10.7, "switch fabric control and st atus registers," on page 225 . 10.5.4 switch fabric csr writes to perform a write to an individual switch fabric regi ster, the desired data must first be written into the switch fabric csr interface data register (switch_csr_data) . the write cycle is initiated by performing a single write to the switch fabric csr interface co mmand register (switch_csr_cmd) with the csr busy (csr_busy) bit set, the csr address (csr_addr[15:0]) field set to the desired register address, the read/write (r_nw) bit cleared, the auto increment (auto_inc) and auto decrement (auto_dec) fields cleared and the desired csr byte enable (csr_be[3:0]) bits selected. the completion of the write cycle is indicated by the clearing of the csr busy (csr_busy) bit. a second write method may be used which utilizes the auto increment/decrement function of the switch fabric csr interface command regi ster (switch_csr_cmd) for writing sequential register addresses. when using this method, the switch fabric csr interface co mmand register (switch_csr_cmd) must first be written with the auto incre- ment (auto_inc) or auto decrement (auto_dec) bit set, the csr address (csr_addr[15:0]) field written with the desired register address, the read/write (r_nw) bit cleared and the desired csr byte enable bits selected (typically all set). the write cycles are then initiate d by writing the desired data into the switch fabric csr interface data register (switch_csr_data) . the completion of the write cycle is indicated by the clearing of the csr busy (csr_busy) bit, at which time the address in the switch fabric csr interface co mmand register (switch_csr_cmd) is incre- mented or decremented accordingly. the user may then initia te a subsequent write cycle by writing the desired data into the switch fabric csr interface data register (switch_csr_data) . the third write method is to use the direct data range write function. writes within the switch fabric csr interface direct data registers (switch_csr_direct_data) address range automatically set the appropriate register address, set all four csr byte enable (csr_be[3:0]) bits, clears the read/write (r_nw) bit and set the csr busy (csr_busy) bit of the switch fabric csr interface co mmand register (switch_csr_cmd) . the completion of the write cycle is
-page 208 ? 2015 microchip technology inc. indicated by the clearing of the csr busy (csr_busy) bit. since the address range of the switch fabric csrs exceeds that of the switch fabric csr interface direct da ta registers (switch_csr_direct_data) address range, a sub-set of the switch fabric csrs is mapped to the switch fabric csr interface dir ect data registers (switch_cs- r_direct_data) address range as detailed in table 10-8, ?switch fabric cs r to switch_csr_direct_data address range map,? on page 222 . figure 10-8 illustrates the process required to perform a switch fabric csr write. the mini mum wait periods as spec- ified in table 5-2, ?read after write timing rules,? on page 34 are required where noted. 10.5.5 switch fabric csr reads to perform a read of an individual switch fabric register, th e read cycle must be initiated by performing a single write to the switch fabric csr interface co mmand register (switch_csr_cmd) with the csr busy (csr_busy) bit set, the csr address (csr_addr[15:0]) field set to the desired register address, the read/write (r_nw) bit set and the auto increment (auto_inc) and auto decrement (auto_dec) fields cleared. valid data is available for reading when the csr busy (csr_busy) bit is cleared, indicating that the data can be read from the switch fabric csr interface data register (switch_csr_data) . a second read method may be used which utilizes the auto increment/decrement function of the switch fabric csr interface command register (switch_csr_cmd) for reading sequential regist er addresses. when using this method, the switch fabric csr interface co mmand register (switch_csr_cmd) must first be written with the csr busy (csr_busy) bit set, the auto increment (auto_inc) or auto decrement (auto_dec) bit set, the csr address (csr_addr[15:0]) field written with the desired register address and the read/write (r_nw) bit set. the completion of a read cycle is indicate d by the clearing of the csr busy (csr_busy) bit, at which time the data can be read from the switch fabric csr interface da ta register (switch_csr_data) . when the data is read, the address in the switch fabric csr interface co mmand register (switch_csr_cmd) is incremented or decremented accordingly and another read cycle is started auto matically. the user should clear the auto increment (auto_inc) and auto dec- rement (auto_dec) bits before reading the last data to avoid an unintended read cycle. figure 10-8: switch fabrics csr write access flow diagram idle write data register write command register read command register csr_busy = 0 csr write csr_busy = 1 idle write data register write command register read command register csr_busy = 0 csr write auto increment / decrement csr_busy = 1 idle write direct data register range read command register csr_busy = 0 csr write direct address csr_busy = 1 min wait period min wait period min wait period
? 2015 microchip technology inc. -page 209 figure 10-9 illustrates the process required to perform a switch fabric csr read. the minimum wait periods as speci- fied in table 5-2, ?read after write timing rules,? on page 34 and table 5-3, ?read after read timing rules,? on page 36 are required where noted. figure 10-9: switch fabrics csr read access flow diagram idle write command register read command register read data register csr_busy = 0 csr read csr_busy = 1 idle write command register read command register csr_busy = 0 csr read auto increment / decrement csr_busy = 1 write command register read data register last data? yes no read data register min wait period min wait period min wait period
-page 210 ? 2015 microchip technology inc. 10.6 switch fabric interface logic registers this section details the directly addressable syst em csrs which are relate d to the switch fabric. the flow control of all three ports of the switch fabric can be configured via the system csr?s port 1 manual flow con- trol register (manual_fc_1) , port 2 manual flow control register (manual_fc_2) and port 0 manual flow control register (manual_fc_0) . the mac address used by the switch fo r pause frames is configured via the switch fabric mac address high register (switch_mac_addrh) and the switch fabric mac address low register (switch_mac_addrl) . the switch fabric csr interface co mmand register (switch_csr_cmd) , the switch fabric csr interface data register (switch_csr_data) and the switch fabric csr interface direct data registers (switch_csr_di- rect_data) serve as an accessible interface to the full range of otherwise inaccessible switch control and status reg- isters. a list of all the switch fabric csrs can be seen in table 10-9 . for detailed descriptions of the switch fabric csrs that are accessible via these interface registers, refer to section 10.7, "switch fabric control and status registers" . for an overview of the entire directly addressable register map, refer to section 5.0, "register map," on page 29 . table 10-6: switch fabric interface logic registers address register name (symbol) 1a0h port 1 manual flow control register (manual_fc_1) 1a4h port 2 manual flow control register (manual_fc_2) 1a8h port 0 manual flow control register (manual_fc_0) 1ach switch fabric csr interface data register (switch_csr_data) 1b0h switch fabric csr interface command register (switch_csr_cmd) 1f0h switch fabric mac address high register (switch_mac_addrh) 1f4h switch fabric mac address low register (switch_mac_addrl) 200h-2f8h switch fabric csr interface direct data registers (switch_csr_direct_data)
? 2015 microchip technology inc. -page 211 10.6.1 port 1 manual flow co ntrol register (manual_fc_1) this read/write register allows for the manual configuration of the switch port 1 flow control. this register also provides read back of the currently enabled flow control setting s, whether set manually or auto-negotiated. refer to section 10.5.1, "flow control enable logic" for additional information. note: the flow control values in the phy?s auto-negotiation advertisement register are not affected by the values of this register. offset: 1a0h size: 32 bits bits description type default 31:7 reserved ro - 6 port 1 backpressure enable (bp_en_1) this bit enables/disables the generation of half-duplex backpressure on switch port 1. 0: disable backpressure 1: enable backpressure r/w note 4 5 port 1 current duplex (cur_dup_1) this bit indicates the actual d uplex setting of switch port 1. 0: full-duplex 1: half-duplex ro note 5 4 port 1 current receive flow control enable (cur_rx_fc_1) this bit indicates the actual receiv e flow setting of switch port 1. 0: flow control receive is currently disabled 1: flow control receive is currently enabled ro note 5 3 port 1 current transmit flow control enable (cur_tx_fc_1) this bit indicates the actual transmi t flow setting of switch port 1. 0: flow control transmit is currently disabled 1: flow control transmit is currently enabled ro note 5 2 port 1 full-duplex receive flow control enable (rx_fc_1) when the manual_fc_1 bit is set or auto-negotiation is disabled, this bit enables/disables the detection of full-d uplex pause packets on switch port 1. 0: disable flow control receive 1: enable flow control receive r/w note 6 1 port 1 full-duplex transmit flow control enable (tx_fc_1) when the manual_fc_1 bit is set or auto-negotiation is disabled, this bit enables/disables full-duplex pause packets to be generated on switch port 1. 0: disable flow control transmit 1: enable flow control transmit r/w note 6
-page 212 ? 2015 microchip technology inc. note 4: the default value of this field is determined by the bp_en_strap_1 configuration strap. note 5: the default value of this bit is determined by multiple strap settings. note 6: the default value of this field is determined by the fd_fc_strap_1 configuration strap. note 7: the default value of this field is determined by the manual_fc_strap_1 configuration strap. 0 port 1 full-duplex manual flow control select (manual_fc_1) this bit toggles flow control selection between manual and auto-negotiation. 0: if auto-negotiation is enabled, the auto-negotiati on function deter- mines the flow control of switch port 1 (rx_fc_1 and tx_fc_1 values ignored). if auto-negotiation is disabled, the rx_fc_1 and tx_fc_1 values are used. 1: tx_fc_1 and rx_fc_1 bits determine the flow control of switch port 1 when in full-duplex mode. r/w note 7 bits description type default
? 2015 microchip technology inc. -page 213 10.6.2 port 2 manual flow co ntrol register (manual_fc_2) this read/write register allows for the manual configuration of the switch port 2 flow control. this register also provides read back of the currently enabled flow control setting s, whether set manually or auto-negotiated. refer to section 10.5.1, "flow control enable logic" for additional information. note: the flow control values in the phy?s auto-negotiation advertisement register are not affected by the values of this register. offset: 1a4h size: 32 bits bits description type default 31:7 reserved ro - 6 port 2 backpressure enable (bp_en_2) this bit enables/disables the generation of half-duplex backpressure on switch port 2. 0: disable backpressure 1: enable backpressure r/w note 8 5 port 2 current duplex (cur_dup_2) this bit indicates the actual d uplex setting of switch port 2. 0: full-duplex 1: half-duplex ro note 9 4 port 2 current receive flow control enable (cur_rx_fc_2) this bit indicates the actual receiv e flow setting of switch port 2. 0: flow control receive is currently disabled 1: flow control receive is currently enabled ro note 9 3 port 2 current transmit flow control enable (cur_tx_fc_2) this bit indicates the actual transmi t flow setting of switch port 2. 0: flow control transmit is currently disabled 1: flow control transmit is currently enabled ro note 9 2 port 2 full-duplex receive flow control enable (rx_fc_2) when the manual_fc_2 bit is set or auto-negotiation is disabled, this bit enables/disables the detection of full-duplex pause packets on switch port 2. 0: disable flow control receive 1: enable flow control receive r/w note 10 1 port 2 full-duplex transmit flow control enable (tx_fc_2) when the manual_fc_2 bit is set or auto-negotiation is disabled, this bit enables/disables full-duplex pause packets to be generated on switch port 2. 0: disable flow control transmit 1: enable flow control transmit r/w note 10
-page 214 ? 2015 microchip technology inc. note 8: the default value of this field is determined by the bp_en_strap_2 configuration strap. note 9: the default value of this bit is determined by multiple strap settings. note 10: the default value of this field is determined by the fd_fc_strap_2 configuration strap. note 11: the default value of this field is determined by the manual_fc_strap_2 configuration strap. 0 port 2 full-duplex manual flow control select (manual_fc_2) this bit toggles flow control selection between manual and auto-negotiation. 0: if auto-negotiation is enabled, the auto-negotiati on function deter- mines the flow control of switch port 2 (rx_fc_2 and tx_fc_2 values ignored). if auto-negotiation is disabled, the rx_fc_2 and tx_fc_2 values are used. 1: tx_fc_2 and rx_fc_2 bits determine the flow control of switch port 2 when in full-duplex mode r/w note 11 bits description type default
? 2015 microchip technology inc. -page 215 10.6.3 port 0 manual flow co ntrol register (manual_fc_0) this read/write register allows for the manual configuration of the switch port 0 flow control. this register also provides read back of the currently enabled flow control setting s, whether set manually or auto-negotiated. refer to section 10.5.1, "flow control enable logic" for additional information. note: the flow control values in the phy?s auto-negotiation advertisement register are not affected by the values of this register. offset: 1a8h size: 32 bits bits description type default 31:7 reserved ro - 6 port 0 backpressure enable (bp_en_0) this bit enables/disables the generation of half-duplex backpressure on switch port 0. 0: disable backpressure 1: enable backpressure r/w note 12 5 port 0 current duplex (cur_dup_0) this bit indicates the actual d uplex setting of switch port 0. 0: full-duplex 1: half-duplex ro note 13 4 port 0 current receive flow control enab le (cur_rx_0) this bit indicates the actual receiv e flow setting of switch port 0 0: flow control receive is currently disabled 1: flow control receive is currently enabled ro note 13 3 port 0 current transmit flow control enable (cur_tx_fc_0) this bit indicates the actual transmi t flow setting of switch port 0. 0: flow control transmit is currently disabled 1: flow control transmit is currently enabled ro note 13 2 port 0 full-duplex receive flow control enable (rx_fc_0) when the manual_fc_0 bit is set or virtual auto-negotiation is disabled, this bit enables/disables the detection of full-duplex pause packets on switch port 0. 0: disable flow control receive 1: enable flow control receive r/w note 14 1 port 0 full-duplex transmit flow control enable (tx_fc_0) when the manual_fc_0 bit is set or virtual auto-negotiation is disabled, this bit enables/disables full-duplex pause packets to be generated on switch port 0. 0: disable flow control transmit 1: enable flow control transmit r/w note 14
-page 216 ? 2015 microchip technology inc. note 12: the default value of this field is determined by the bp_en_strap_0 configuration strap. note 13: the default value of this bit is determined by multiple strap settings. note 14: the default value of this field is determined by the fd_fc_strap_0 configuration strap. note 15: this bit is ro when in external mac modes. note 16: in external mac modes, this bit has a default value of 1 and is not re-written by the eeprom loader. oth- erwise, the default value of th is field is determined by the manual_fc_strap_0 configuration strap. 0 port 0 full-duplex manual flow control select (manual_fc_0) this bit toggles flow control selection between manual and auto-negotiation. 0: if auto-negotiation is enabled, the auto-negotiati on function deter- mines the flow control of switch port 0 (rx_fc_0 and tx_fc_0 values ignored). if auto-negotiation is disabled, the rx_fc_0 and tx_fc_0 values are used. 1: tx_fc_0 and rx_fc_0 bits determine the flow control of switch port 0 when in full-duplex mode. note: in external mac modes, this bit is forced high. full-duplex flow control should be controlled manually by the host based on the external phys auto-negotiation results. r/w note 15 note 16 bits description type default
? 2015 microchip technology inc. -page 217 10.6.4 switch fabric csr interface data register (switch_csr_data) this read/write register is used in conjunction with the switch fabric csr interface command register (switch_cs- r_cmd) to perform read and write operations with the switch fabric csrs. refer to section 10.7, "switch fabric con- trol and status registers," on page 225 for details on the registers indirectly accessible via this register. offset: 1ach size: 32 bits bits description type default 31:0 switch csr data (csr_data) this field contains the value read from or written to the switch fabric csr. the switch fabric csr is selected via the csr address (csr_addr[15:0]) bits of the switch fabric csr interface command register (switch_cs- r_cmd) . upon a read, the value returned depends on the read/write (r_nw) bit in the switch fabric csr interface command register (switch_csr_cmd) . if read/write (r_nw) is set, the data is from the switch fabric. if read/write (r_nw) is cleared, the data is the value that was last written into this register. r/w 00000000h
-page 218 ? 2015 microchip technology inc. 10.6.5 switch fabric csr interface command register (switch_csr_cmd) this read/write register is us ed in conjunction with the switch fabric csr interface data register (switch_csr_- data) to control the read and write operations to the various switch fabric csrs. refer to section 10.7, "switch fabric control and status registers," on page 225 for details on the registers indirectly accessible via this register. offset: 1b0h size: 32 bits bits description type default 31 csr busy (csr_busy) when a 1 is written to this bit, the r ead or write operation (as determined by the r_nw bit) is performed to the specified switch fabric csr in csr address (csr_addr[15:0]) . this bit will remain set until the operation is complete, at which time the bit will self-c lear. in the case of a read, the clear- ing of this bit indicates to the host that valid data can be read from the switch fabric csr interface data register (switch_csr_data) . the switch_csr_cmd and switch_csr_data registers should not be modified until this bit self-clears. r/w sc 0b 30 read/write (r_nw) this bit determines whether a read or write operation is performed by the host to the specified switch fabric csr. 0: write 1: read r/w 0b 29 auto increment (auto_inc) this bit enables/disables the auto increment feature. when this bit is set, a write to the switch fabric csr interface data register (switch_csr_data) will automatically set the csr busy (csr_busy) bit. once the write command is finished, the csr address (csr_addr[15:0]) will automatically increment. when this bit is set, a read from the switch fabric csr interface data regis- ter (switch_csr_data) will automatically increment the csr address (csr_addr[15:0]) and set the csr busy (csr_busy) bit. this bit should be cleared by software before the last read from the switch_csr_data register. 0: disable auto increment 1: enable auto increment note: this bit has precedence over the auto decrement (auto_dec) bit. r/w 0b
? 2015 microchip technology inc. -page 219 28 auto decrement (auto_dec) this bit enables/disables the auto decrement feature. when this bit is set, a write to the switch fabric csr interface data register (switch_csr_data) will automatically set the csr busy (csr_busy) bit. once the write command is finished, the csr address (csr_addr[15:0]) will automatically decrement. when this bit is set, a read from the switch fabric csr interface data regis- ter (switch_csr_data) will automatically decrement the csr address (csr_addr[15:0]) and set the csr busy (csr_busy) bit. this bit should be cleared by software before the last read from the switch_csr_data register. 0: disable auto decrement 1: enable auto decrement r/w 0b 27:20 reserved ro - 19:16 csr byte enable (csr_be[3:0]) this field is a 4-bit byte enable used for selection of valid bytes during write operations. bytes which are not select ed will not be written to the corre- sponding switch fabric csr. csr_be[3] corresponds to register data bits [31:24] csr_be[2] corresponds to register data bits [23:16] csr_be[1] corresponds to register data bits [15:8] csr_be[0] corresponds to register data bits [7:0] typically all four-byte-enables should be set for auto increment and auto dec- rement operations. r/w 0h 15:0 csr address (csr_addr[15:0]) this field selects the 16-bit address of the switch fabric csr that will be accessed with a read or write operation. refer to table 10-9, ?indirectly accessible switch control and status registers,? on page 225 for a list of switch fabric csr addresses. r/w 00h bits description type default
-page 220 ? 2015 microchip technology inc. 10.6.6 switch fabric mac address hi gh register (switch_mac_addrh) this register contains the upper 16 bits of the mac address used by the switch for pause frames. this register is used in conjunction with switch fabric mac address low register (switch_mac_addrl) . the contents of this register are optionally loaded from the eeprom at power-on through the eeprom loader if a programmed eeprom is detected. the least signif icant byte of this register (bits [7:0]) is loaded from address 05h of the eeprom. the second byte (bits [15:8]) is loaded fr om address 06h of the eeprom. t he host can update the contents of this field after the initialization process has completed. refer to section 10.6.7, "switch fabric mac ad dress low register (switch_mac_addrl)" for information on how this address is loaded by the eeprom loader. section 12.4, "eeprom loader," on page 332 contains additional details on using the eeprom loader. offset: 1f0h size: 32 bits bits description type default 31:23 reserved ro - 22 diffpauseaddr when set, each port may have a unique mac address. r/w 0b 21:20 port 2 physical address [41:40] when diffpauseaddr is set, these bits are used as bits 41 and 40 of the mac address for port 2. r/w 10b 19:18 port 1 physical address [41:40] when diffpauseaddr is set, these bits are used as bits 41 and 40 of the mac address for port 1. r/w 01b 17:16 port 0 physical address [41:40] when diffpauseaddr is set, these bits are used as bits 41 and 40 of the mac address for port 0. r/w 00b 15:0 physical address[47:32] this field contains the upper 16-bits (47:32) of the physical address of the switch fabric macs. bits 41 and 10 are ignored if diffpauseaddr is set. r/w ffffh
? 2015 microchip technology inc. -page 221 10.6.7 switch fabric mac address low register (switch_mac_addrl) this register contains the lower 32 bits of the mac address used by the switch for pause frames. this register is used in conjunction with switch fabric mac address high register (switch_mac_addrh) . the contents of this register are optionally loaded from the eeprom at power-o n through the eeprom loader if a programmed eeprom is detected. the least sign ificant byte of this register (bits [7:0]) is loaded from address 01h of the eeprom. the most significant byte (bits [31:24]) is loaded from address 04h of the eeprom. the host can update the contents of this field after the initialization process has completed. refer to section 12.4, "eeprom loader," on page 332 for information on using the eeprom loader. table 10-7 illustrates the byte ordering of the swit ch_mac_addrl and switch_ mac_addrh registers with respect to the reception of the ethe rnet physical address. also shown is the correlation between the eeprom addresses and the switch_mac_addrl and switch_mac_addrh registers. for example, if the desired ethernet physical addre ss is 12-34-56-78-9a-bc, the switch_mac_addrl and switch_mac_addrh registers would be programmed as shown in figure 10-10 . the values required to automati- cally load this confi guration from the eeprom are also shown. note: by convention, the right nibble of t he left most byte of the ethernet addr ess (in this example, the 2 of the 12h) is the most significant nibble and is transmitted/received first. offset: 1f4h size: 32 bits bits description type default 31:0 physical address[31:0] this field contains the lower 32 bits (31:0) of the physical address of the switch fabric macs. r/w ff0f8000h table 10-7: switch_mac_addrl, switch_ mac_addrh and eeprom byte ordering eeprom address register location wri tten order of recep tion on ethernet 01h switch_mac_addrl[7:0] 1 st 02h switch_mac_addrl[15:8] 2 nd 03h switch_mac_addrl[23:16] 3 rd 04h switch_mac_addrl[31:24] 4 th 05h switch_mac_addrh[7:0] 5 th 06h switch_mac_addrh[15:8] 6 th figure 10-10: example switch_mac_ad dl, switch_mac_add rh and eeprom setup 12h 0 7 34h 8 15 56h 16 23 78h 24 31 9ah bch xx xx a5h 12h 34h 56h 78h 9ah bch 00h 01h 02h 03h 04h 05h 06h eeprom switch_mac_addrl switch_mac_addrh 0 7 8 15 16 23 24 31
-page 222 ? 2015 microchip technology inc. 10.6.8 switch fabric csr interface direct data registers (switch_csr_direct_data) this write-only register set is used to perform directly addressed write operations to the switch fabric csrs. using this set of registers, writes can be directly addressed to select switch fabric registers, as specified in table 10-8 . writes within the switch fabric csr interface direct da ta registers (switch_csr_direct_data) address range automatically set the appropriate csr address (csr_addr[15:0]) , set the four csr byte enable (csr_be[3:0]) bits, clear the read/write (r_nw) bit and set the csr busy (csr_busy) bit in the switch fabric csr interface command register (switch_csr_cmd) . the completion of the write cycle is indicated when the csr busy (csr_busy) bit self-clears. the address that is set in the switch fabric csr interface co mmand register (switch_csr_cmd) is mapped via table 10-8: . for more information on this method of writing to the switch fabric csrs, refer to section 10.5.4, "switch fabric cs r writes," on page 207 . note: this set of registers is for write operat ions only. reads can be performed via the switch fabric csr inter- face command register (switch_csr_cmd) and the switch fabric csr interface data register (switch_csr_data) only. offset: 200h-2f8h size: 32 bits bits description type default 31:0 switch csr data (csr_data) this field contains the value to be written to the corresponding switch fabric register. wo 00000000h table 10-8: switch fabric csr to sw itch_csr_direct_dat a address range map register name switch fabric csr register # switch_csr_direct_data address general switch csrs sw_reset 0001h 200h sw_imr 0004h 204h switch port 0 csrs mac_rx_cfg_0 0401h 208h mac_tx_cfg_0 0440h 20ch mac_tx_fc_settings_0 0441h 210h mac_imr_0 0480h 214h switch port 1 csrs mac_rx_cfg_1 0801h 218h mac_tx_cfg_1 0840h 21ch mac_tx_fc_settings_1 0841h 220h eee_tw_tx_sys_1 0842h 2e8h eee_tx_lpi_req_delay_cnt_1 0843h 2ech mac_imr_1 0880h 224h
? 2015 microchip technology inc. -page 223 switch port 2 csrs mac_rx_cfg_2 0c01h 228h mac_tx_cfg_2 0c40h 22ch mac_tx_fc_settings_2 0c41h 230h eee_tw_tx_sys_2 0c42h 2f0h eee_tx_lpi_req_delay_cnt_2 0c43h 2f4h mac_imr_2 0c80h 234h switch engine csrs swe_alr_cmd 1800h 238h swe_alr_wr_dat_0 1801h 23ch swe_alr_wr_dat_1 1802h 240h swe_alr_cfg 1809h 244h swe_alr_override 180ah 2f8h swe_vlan_cmd 180bh 248h swe_vlan_wr_data 180ch 24ch swe_diffserv_tbl_cmd 1811h 250h swe_diffserv_tbl_wr_data 1812h 254h swe_glb_ingress_ cfg 1840h 258h swe_port_ingress_cfg 1841h 25ch swe_admt_only_ vlan 1842h 260h swe_port_state 1843h 264h swe_pri_to_que 1845h 268h swe_port_mirror 1846h 26ch swe_ingress_port_typ 1847h 270h swe_bcst_throt 1848h 274h swe_admt_n_member 1849h 278h swe_ingress_rate_cfg 184ah 27ch swe_ingress_rate_cmd 184bh 280h swe_ingress_rate_wr_data 184dh 284h swe_ingress_rege n_tbl_0 1855h 288h swe_ingress_rege n_tbl_1 1856h 28ch swe_ingress_rege n_tbl_2 1857h 290h table 10-8: switch fabric csr to swit ch_csr_direct_data address range map register name switch fabric csr register # switch_csr_direct_data address
-page 224 ? 2015 microchip technology inc. swe_imr 1880h 294h buffer manager (bm) csrs bm_cfg 1c00h 298h bm_drop_lvl 1c01h 29ch bm_fc_pause_lvl 1c02h 2a0h bm_fc_resume_lvl 1c03h 2a4h bm_bcst_lvl 1c04h 2a8h bm_rndm_dscrd_tbl_cmd 1c09h 2ach bm_rndm_dscrd_tbl_wdata 1c0ah 2b0h bm_egrss_port_type 1c0ch 2b4h bm_egrss_rate_00_01 1c0dh 2b8h bm_egrss_rate_02_03 1c0eh 2bch bm_egrss_rate_10_11 1c0fh 2c0h bm_egrss_rate_12_13 1c10h 2c4h bm_egrss_rate_20_21 1c11h 2c8h bm_egrss_rate_22_23 1c12h 2cch bm_vlan_0 1c13h 2d0h bm_vlan_1 1c14h 2d4h bm_vlan_2 1c15h 2d8h bm_imr 1c20h 2dch table 10-8: switch fabric csr to sw itch_csr_direct_dat a address range map register name switch fabric csr register # switch_csr_direct_data address
? 2015 microchip technology inc. -page 225 10.7 switch fabric control and status registers this section details the various indirectly addressable switch control and status registers that reside within the switch fabric. the switch control and status regi sters allow configuration of each individual switch port, the switch engine and buffer manager. switch fabric related interrupts and resets are also controlled and monitored via the switch csrs. the switch csrs are not directly mapped into the system a ddress space. all switch csrs are accessed i ndirectly via the switch fabric csr interface co mmand register (switch_csr_cmd) , the switch fabric csr interface data register (switch_csr_data) and the switch fabric csr interface direct data registers (switch_csr_di- rect_data) in the system csr address space. all accesses to the switch csrs must be performed through these registers. refer to section 10.6, "switch fabric interface logic registers" for additional information. note: the flow control settings of the switch ports are configured via the switch fabric interface logic registers : port 1 manual flow control register (manual_fc_1) , port 2 manual flow control register (manual_f- c_2) and port 0 manual flow control register (manual_fc_0) located in the system csr address space. table 10-9 lists the switch csrs and their corresponding addresse s in order. the switch fabric registers can be cate- gorized into the following sub-sections: ? section 10.7.1, "general switch csrs," on page 234 ? section 10.7.2, "switch port 0, port 1 and port 2 csrs," on page 238 ? section 10.7.3, "switch engine csrs," on page 265 ? section 10.7.4, "buffer manager csrs," on page 302 table 10-9: indirectly accessible swit ch control and status registers address (indirect) register name (symbol) general switch csrs 0000h switch device id register (sw_dev_id) 0001h switch reset register (sw_reset) 0002h-0003h reserved for future use (reserved) 0004h switch global interrupt mask register (sw_imr) 0005h switch global interrupt pending register (sw_ipr) 0006h-03ffh reserved for future use (reserved) switch port 0 csrs (x=0) 0400h port x mac version id register (mac_ver_id_x) 0401h port x mac receive configurat ion register (mac_rx_cfg_x) 0402h-040fh reserved for future use (reserved) 0410h port x mac receive undersize coun t register (mac_rx_undsze_cnt_x) 0411h port x mac receive 64 byte count register (mac_rx_64_cnt_x) 0412h port x mac receive 65 to 127 byte count register (mac_rx_65_to_127_cnt_x) 0413h port x mac receive 128 to 255 byte count register (mac_rx_128_to_255_cnt_x) 0414h port x mac receive 256 to 511 byte count register (mac_rx_256_to_511_cnt_x) 0415h port x mac receive 512 to 1023 byte co unt register (mac_rx_512_to_1023_cnt_x) 0416h port x mac receive 1024 to max byte count register (mac_rx_1024_to_max_cnt_x) 0417h port x mac receive oversize count register (mac_rx_ovrsze_cnt_x)
-page 226 ? 2015 microchip technology inc. 0418h port x mac receive ok count register (mac_rx_pktok_cnt_x) 0419h port x mac receive crc error count register (mac_rx_crcerr_cnt_x) 041ah port x mac receive multicast count register (mac_rx_mulcst_cnt_x) 041bh port x mac receive broadcast coun t register (mac_rx_brdcst_cnt_x) 041ch port x mac receive pause frame count register (mac_rx_pause_cnt_x) 041dh port x mac receive fragment error count register (m ac_rx_frag_cnt_x) 041eh port x mac receive jabber error count register (mac_rx_jabb_cnt_x) 041fh port x mac receive alignment error count register (mac_rx_align_cnt_x) 0420h port x mac receive packet length count register (mac_rx_pktlen_cnt_x) 0421h port x mac receive good packet length count register (mac_rx_goodpktlen_cnt_x) 0422h port x mac receive symbol error count register (mac_rx_symbol_cnt_x) 0423h port x mac receive control frame count register (mac_rx_ctlfrm_cnt_x) 0424h-043fh reserved for future use (reserved) 0440h port x mac transmit configuration register (mac_tx_cfg_x) 0441h port x mac transmit flow control se ttings register (mac_tx_fc_settings_x) 0442h-0450h reserved for future use (reserved) 0451h port x mac transmit deferred count register (mac_tx_defer_cnt_x) 0452h port x mac transmit pause count register (mac_tx_pause_cnt_x) 0453h port x mac transmit ok count register (mac_tx_pktok_cnt_x) 0454h port x mac transmit 64 byte count register (mac_tx_64_cnt_x) 0455h port x mac transmit 65 to 127 byte count register (mac_tx_65_to_127_cnt_x) 0456h port x mac transmit 128 to 255 byte count register (mac_tx_128_to_255_cnt_x) 0457h port x mac transmit 256 to 511 byte count register (mac_tx_256_to_511_cnt_x) 0458h port x mac transmit 512 to 1023 byte count register (mac_tx_512_to_1023_cnt_x) 0459h port x mac transmit 1024 to max byte count register (mac_tx_1024_to_max_cnt_x) 045ah port x mac transmit undersize c ount register (mac_tx_undsze_cnt_x) 045bh reserved for future use (reserved) 045ch port x mac transmit packet length count register (mac_tx_pktlen_cnt_x) 045dh port x mac transmit broadcast coun t register (mac_tx_brdcst_cnt_x) 045eh port x mac transmit multicast count register (mac_tx_mulcst_cnt_x) 045fh port x mac transmit late collision count register (mac_tx_latecol_cnt_x) table 10-9: indirectly accessible swit ch control and status registers address (indirect) register name (symbol)
? 2015 microchip technology inc. -page 227 0460h port x mac transmit exce ssive collision count register (mac_tx_exccol_cnt_x) 0461h port x mac transmit single collision count register (mac_tx_snglecol_cnt_x) 0462h port x mac transmit multiple collision count register (mac_tx_multicol_cnt_x) 0463h port x mac transmit total collision count register (mac_tx_totalcol_cnt_x) 0464h-047fh reserved for future use (reserved) 0480h port x mac interrupt mask register (mac_imr_x) 0481h port x mac interrupt pending register (mac_ipr_x) 0482h-07ffh reserved for future use (reserved) switch port 1 csrs (x=1) 0800h port x mac version id register (mac_ver_id_x) 0801h port x mac receive configurat ion register (mac_rx_cfg_x) 0802h-080fh reserved for future use (reserved) 0810h port x mac receive undersize coun t register (mac_rx_undsze_cnt_x) 0811h port x mac receive 64 byte count register (mac_rx_64_cnt_x) 0812h port x mac receive 65 to 127 byte count register (mac_rx_65_to_127_cnt_x) 0813h port x mac receive 128 to 255 byte count register (mac_rx_128_to_255_cnt_x) 0814h port x mac receive 256 to 511 byte count register (mac_rx_256_to_511_cnt_x) 0815h port x mac receive 512 to 1023 byte co unt register (mac_rx_512_to_1023_cnt_x) 0816h port x mac receive 1024 to max byte count register (mac_rx_1024_to_max_cnt_x) 0817h port x mac receive oversize count register (mac_rx_ovrsze_cnt_x) 0818h port x mac receive ok count register (mac_rx_pktok_cnt_x) 0819h port x mac receive crc error count register (mac_rx_crcerr_cnt_x) 081ah port x mac receive multicast count register (mac_rx_mulcst_cnt_x) 081bh port x mac receive broadcast coun t register (mac_rx_brdcst_cnt_x) 081ch port x mac receive pause frame count register (mac_rx_pause_cnt_x) 081dh port x mac receive fragment error count register (mac_rx_frag_cnt_x) 081eh port x mac receive jabber error count register (mac_rx_jabb_cnt_x) 081fh port x mac receive alignment error count register (mac_rx_align_cnt_x) 0820h port x mac receive packet length count register (mac_rx_pktlen_cnt_x) 0821h port x mac receive good packet length co unt register (mac_rx_goodpktlen_cnt_x) 0822h port x mac receive symbol error count register (mac_rx_symbol_cnt_x) table 10-9: indirectly accessible swit ch control and status registers address (indirect) register name (symbol)
-page 228 ? 2015 microchip technology inc. 0823h port x mac receive control frame count register (mac_rx_ctlfrm_cnt_x) 0824h port x rx lpi transitions register (rx_lpi_transition_x) 0825h port x rx lpi time register (rx_lpi_time_x) 0826h-083fh reserved for future use (reserved) 0840h port x mac transmit configuration register (mac_tx_cfg_x) 0841h port x mac transmit flow control se ttings register (mac_tx_fc_settings_x) 0842h port x eee time wait tx sy stem register (eee_tw_tx_sys_x) 0843h port x eee tx lpi request delay register (eee_tx_lpi_req_delay_x) 0844h-0850h reserved for future use (reserved) 0851h port x mac transmit deferred count register (mac_tx_defer_cnt_x) 0852h port x mac transmit pause count register (mac_tx_pause_cnt_x) 0853h port x mac transmit ok count register (mac_tx_pktok_cnt_x) 0854h port x mac transmit 64 byte count register (mac_tx_64_cnt_x) 0855h port x mac transmit 65 to 127 byte count register (mac_tx_65_to_127_cnt_x) 0856h port x mac transmit 128 to 255 byte count register (mac_tx_128_to_255_cnt_x) 0857h port x mac transmit 256 to 511 byte count register (mac_tx_256_to_511_cnt_x) 0858h port x mac transmit 512 to 1023 byte count register (mac_tx_512_to_1023_cnt_x) 0859h port x mac transmit 1024 to max byte count register (mac_tx_1024_to_max_cnt_x) 085ah port x mac transmit undersize c ount register (mac_tx_undsze_cnt_x) 085bh reserved for future use (reserved) 085ch port x mac transmit packet length count register (mac_tx_pktlen_cnt_x) 085dh port x mac transmit broadcast coun t register (mac_tx_brdcst_cnt_x) 085eh port x mac transmit multicast count register (mac_tx_mulcst_cnt_x) 085fh port x mac transmit late collision count register (mac_tx_latecol_cnt_x) 0860h port x mac transmit excessive collisio n count register (mac_tx_exccol_cnt_x) 0861h port x mac transmit single collision count register (mac_tx_snglecol_cnt_x) 0862h port x mac transmit multiple collision count register (mac_tx_multicol_cnt_x) 0863h port x mac transmit total collision count register (mac_tx_totalcol_cnt_x) 0864h port x tx lpi transitions register (tx_lpi_transition_x) 0865h port x tx lpi time register (tx_lpi_time_x) 0866h-087fh reserved for future use (reserved) table 10-9: indirectly accessible swit ch control and status registers address (indirect) register name (symbol)
? 2015 microchip technology inc. -page 229 0880h port x mac interrupt mask register (mac_imr_x) 0881h port x mac interrupt pending register (mac_ipr_x) 0882h-0bffh reserved for future use (reserved) switch port 2 csrs (x=2) 0c00h port x mac version id register (mac_ver_id_x) 0c01h port x mac receive configurat ion register (mac_rx_cfg_x) 0c02h-0c0fh reserved for future use (reserved) 0c10h port x mac receive undersize coun t register (mac_rx_undsze_cnt_x) 0c11h port x mac receive 64 byte count register (mac_rx_64_cnt_x) 0c12h port x mac receive 65 to 127 byte count register (mac_rx_65_to_127_cnt_x) 0c13h port x mac receive 128 to 255 byte count register (mac_rx_128_to_255_cnt_x) 0c14h port x mac receive 256 to 511 byte count register (mac_rx_256_to_511_cnt_x) 0c15h port x mac receive 512 to 1023 byte co unt register (mac_rx_512_to_1023_cnt_x) 0c16h port x mac receive 1024 to max byte count register (mac_rx_1024_to_max_cnt_x) 0c17h port x mac receive oversize count register (mac_rx_ovrsze_cnt_x) 0c18h port x mac receive ok count register (mac_rx_pktok_cnt_x) 0c19h port x mac receive crc error count register (mac_rx_crcerr_cnt_x) 0c1ah port x mac receive multicast count register (mac_rx_mulcst_cnt_x) 0c1bh port x mac receive broadcast coun t register (mac_rx_brdcst_cnt_x) 0c1ch port x mac receive pause frame count register (mac_rx_pause_cnt_x) 0c1dh port x mac receive fragment error count register (mac_rx_frag_cnt_x) 0c1eh port x mac receive jabber error count register (mac_rx_jabb_cnt_x) 0c1fh port x mac receive alignment error count register (mac_rx_align_cnt_x) 0c20h port x mac receive packet length count register (mac_rx_pktlen_cnt_x) 0c21h port x mac receive good packet length co unt register (mac_rx_goodpktlen_cnt_x) 0c22h port x mac receive symbol error count register (mac_rx_symbol_cnt_x) 0c23h port x mac receive control frame count register (mac_rx_ctlfrm_cnt_x) 0c24h port x rx lpi transitions register (rx_lpi_transition_x) 0c25h port x rx lpi time register (rx_lpi_time_x) 0c26h-0c3fh reserved for future use (reserved) 0c40h port x mac transmit configuration register (mac_tx_cfg_x) table 10-9: indirectly accessible swit ch control and status registers address (indirect) register name (symbol)
-page 230 ? 2015 microchip technology inc. 0c41h port x mac transmit flow control se ttings register (mac_tx_fc_settings_x) 0c42h port x eee time wait tx sy stem register (eee_tw_tx_sys_x) 0c43h port x eee tx lpi request delay register (eee_tx_lpi_req_delay_x) 0c44h-0c50h reserved fo r future use (reserved) 0c51h port x mac transmit deferred count register (mac_tx_defer_cnt_x) 0c52h port x mac transmit pause count register (mac_tx_pause_cnt_x) 0c53h port x mac transmit ok count register (mac_tx_pktok_cnt_x) 0c54h port x mac transmit 64 byte count register (mac_tx_64_cnt_x) 0c55h port x mac transmit 65 to 127 byte count register (mac_tx_65_to_127_cnt_x) 0c56h port x mac transmit 128 to 255 byte count register (mac_tx_128_to_255_cnt_x) 0c57h port x mac transmit 256 to 511 byte count register (mac_tx_256_to_511_cnt_x) 0c58h port x mac transmit 512 to 1023 byte count register (mac_tx_512_to_1023_cnt_x) 0c59h port x mac transmit 1024 to max byte count register (mac_tx_1024_to_max_cnt_x) 0c5ah port x mac transmit undersize c ount register (mac_tx_undsze_cnt_x) 0c5bh reserved for future use (reserved) 0c5ch port x mac transmit packet length count register (mac_tx_pktlen_cnt_x) 0c5dh port x mac transmit broadcast coun t register (mac_tx_brdcst_cnt_x) 0c5eh port x mac transmit multicast count register (mac_tx_mulcst_cnt_x) 0c5fh port x mac transmit late collision count register (mac_tx_latecol_cnt_x) 0c60h port x mac transmit excessive collisio n count register (mac_tx_exccol_cnt_x) 0c61h port x mac transmit single collision count register (mac_tx_snglecol_cnt_x) 0c62h port x mac transmit multiple collision count register (mac_tx_multicol_cnt_x) 0c63h port x mac transmit total collision count register (mac_tx_totalcol_cnt_x) 0c64h port x tx lpi transitions register (tx_lpi_transition_x) 0c65h port x tx lpi time register (tx_lpi_time_x) 0c66h-0c7fh reserved for future use (reserved) 0c80h port x mac interrupt mask register (mac_imr_x) 0c81h port x mac interrupt pending register (mac_ipr_x) 0c82h-17ffh reserved for future use (reserved) switch engine csrs 1800h switch engine alr command register (swe_alr_cmd) table 10-9: indirectly accessible swit ch control and status registers address (indirect) register name (symbol)
? 2015 microchip technology inc. -page 231 1801h switch engine alr write data 0 register (swe_alr_wr_dat_0) 1802h switch engine alr write data 1 register (swe_alr_wr_dat_1) 1803h-1804h reserved for future use (reserved) 1805h switch engine alr read data 0 register (swe_alr_rd_dat_0) 1806h switch engine alr read data 1 register (swe_alr_rd_dat_1) 1807h reserved for future use (reserved) 1808h switch engine alr command status register (swe_alr_cmd_sts) 1809h switch engine alr configurat ion register (swe_alr_cfg) 180ah switch engine alr override register (swe_alr_override) 180bh switch engine vlan command register (swe_vlan_cmd) 180ch switch engine vlan write data register (swe_vlan_wr_data) 180dh reserved for future use (reserved) 180eh switch engine vlan read data register (swe_vlan_rd_data) 180fh reserved for future use (reserved) 1810h switch engine vlan command status register (swe_vlan_cmd_sts) 1811h switch engine diffserv table command register (swe_diffserv_tbl_cfg) 1812h switch engine diffserv table write data register (swe_diffserv_tbl_wr_data) 1813h switch engine diffserv table read data register (swe_diffserv_tbl_rd_data) 1814h switch engine diffserv table command stat us register (swe_diffserv_tbl_cmd_sts) 1815h-183fh reserved for future use (reserved) 1840h switch engine global ingress configur ation register (swe_global_ingrss_cfg) 1841h switch engine port ingress configur ation register (swe_port_ingrss_cfg) 1842h switch engine admit only vlan register (swe_admt_only_vlan) 1843h switch engine port state register (swe_port_state) 1844h reserved for future use (reserved) 1845h switch engine priority to queue register (swe_pri_to_que) 1846h switch engine port mirroring register (swe_port_mirror) 1847h switch engine ingress port type register (swe_ingrss_port_typ) 1848h switch engine broadcast thrott ling register (swe_bcst_throt) 1849h switch engine admit non member register (swe_admt_n_member) 184ah switch engine ingress rate configuration register (swe_ingrss_rate_cfg) table 10-9: indirectly accessible swit ch control and status registers address (indirect) register name (symbol)
-page 232 ? 2015 microchip technology inc. 184bh switch engine ingress rate command register (swe_ingrss_rate_cmd) 184ch switch engine ingress rate command stat us register (swe_ingrss_rate_cmd_sts) 184dh switch engine ingress rate write data register (swe_ingrss_rate_wr_data) 184eh switch engine ingress rate read data register (swe_ingrss_rate_rd_data) 184fh reserved for future use (reserved) 1850h switch engine port 0 ingress filtered count register (swe_filtered_cnt_0) 1851h switch engine port 1 ingress filtered count register (swe_filtered_cnt_1) 1852h switch engine port 2 ingress filtered count register (swe_filtered_cnt_2) 1853h-1854h reserved for future use (reserved) 1855h switch engine port 0 ingress vlan priority regeneration table register (swe_ingrss_re- gen_tbl_0) 1856h switch engine port 1 ingress vlan priority regeneration table register (swe_ingrss_re- gen_tbl_1) 1857h switch engine port 2 ingress vlan priority regeneration table register (swe_ingrss_re- gen_tbl_2) 1858h switch engine port 0 learn discard count register (swe_lrn_discrd_cnt_0) 1859h switch engine port 1 learn discard count register (swe_lrn_discrd_cnt_1) 185ah switch engine port 2 learn discard count register (swe_lrn_discrd_cnt_2) 185bh-187fh reserved for future use (reserved) 1880h switch engine interrupt mask register (swe_imr) 1881h switch engine interrupt pending register (swe_ipr) 1882h-1bffh reserved for future use (reserved) buffer manager (bm) csrs 1c00h buffer manager configuration register (bm_cfg) 1c01h buffer manager drop level register (bm_drop_lvl) 1c02h buffer manager flow control pause level register (bm_fc_pause_lvl) 1c03h buffer manager flow control resume level register (bm_fc_resume_lvl) 1c04h buffer manager broadcast buffer level register (bm_bcst_lvl) 1c05h buffer manager port 0 drop count register (bm_drp_cnt_src_0) 1c06h buffer manager port 1 drop count register (bm_drp_cnt_src_1) 1c07h buffer manager port 2 drop count register (bm_drp_cnt_src_2) 1c08h buffer manager reset status register (bm_rst_sts) 1c09h buffer manager random discard table command register (bm_rndm_dscrd_tbl_cmd) table 10-9: indirectly accessible swit ch control and status registers address (indirect) register name (symbol)
? 2015 microchip technology inc. -page 233 1c0ah buffer manager random discard table write data register (bm_rndm_dscrd_tbl_wdata) 1c0bh buffer manager random discard table read data register (bm_rndm_dscrd_tbl_rdata) 1c0ch buffer manager egress port type register (bm_egrss_port_type) 1c0dh buffer manager port 0 egress rate priority queue 0/1 register (bm_egrss_rate_00_01) 1c0eh buffer manager port 0 egress rate priority queue 2/3 register (bm_egrss_rate_02_03) 1c0fh buffer manager port 1 egress rate priority queue 0/1 register (bm_egrss_rate_10_11) 1c10h buffer manager port 1 egress rate priority queue 2/3 register (bm_egrss_rate_12_13) 1c11h buffer manager port 2 egress rate priority queue 0/1 register (bm_egrss_rate_20_21) 1c12h buffer manager port 2 egress rate priority queue 2/3 register (bm_egrss_rate_22_23) 1c13h buffer manager port 0 default vlan id and priority register (bm_vlan_0) 1c14h buffer manager port 1 default vlan id and priority register (bm_vlan_1) 1c15h buffer manager port 2 default vlan id and priority register (bm_vlan_2) 1c16h buffer manager port 0 ingress rate drop count register (bm_rate_drp_cnt_src_0) 1c17h buffer manager port 1 ingress rate drop count register (bm_rate_drp_cnt_src_1) 1c18h buffer manager port 2 ingress rate drop count register (bm_rate_drp_cnt_src_2) 1c19h-1c1fh reserved for future use (reserved) 1c20h buffer manager interrupt mask register (bm_imr) 1c21h buffer manager interrupt pending register (bm_ipr) 1c22h-ffffh reserved for future use (reserved) table 10-9: indirectly accessible swit ch control and status registers address (indirect) register name (symbol)
-page 234 ? 2015 microchip technology inc. 10.7.1 general switch csrs this section details the general switch fabric csrs. these registers control th e main reset and interrupt functions of the switch fabric. a list of the general switch csrs a nd their corresponding register numbers is included in table 10-9 . 10.7.1.1 switch device id register (sw_dev_id) this read-only register contains switch device id information, including the devi ce type, chip version and revision codes. register #: 0000h size: 32 bits bits description type default 31:24 reserved ro - 23:16 device type code (device_type) ro 03h 15:8 chip version code (chip_version) ro 06h 7:0 revision code (revision) ro 07h
? 2015 microchip technology inc. -page 235 10.7.1.2 switch reset register (sw_reset) this register contains the switch fabric global reset. refer to the switch reset portion of section 6.2, "resets," on page 38 for more information. register #: 0001h size: 32 bits bits description type default 31:1 reserved ro - 0 switch fabric reset (sw_reset) this bit is the global switch fabric reset. all switch fabric blocks are affected. this bit must be manually cleared by software. wo 0b
-page 236 ? 2015 microchip technology inc. 10.7.1.3 switch global interrupt mask register (sw_imr) this read/write register contains the gl obal interrupt mask for the switch fabric interrupts. all switch related interrupts in the switch global interrupt pending register (sw_ipr) may be masked via this register. an interrupt is masked by setting the corresponding bit of this register. clearing a bit will unmask the interrupt. when an unmasked switch fabric interrupt is generated in the switch global interrupt pending register (sw_ipr) , the interrupt will trigger the switch fab- ric interrupt event (switch_int) bit in the interrupt status register (int_sts) . refer to section 8.0, "system inter- rupts," on page 67 for more information. register #: 0004h size: 32 bits bits description type default 31:9 reserved ro - 8:7 reserved note: these bits must be written as 11b. r/w 11b 6 buffer manager interrupt mask (bm) when set, prevents the generation of s witch fabric interrupts due to the buf- fer manager via the buffer manager interrupt pending register (bm_ipr) . the status bits in the switch global interrupt pending register (sw_ipr) are not affected. r/w 1b 5 switch engine interrupt mask (swe) when set, prevents the generation of switch fabric interrupts due to the switch engine via the switch engine interrupt pending register (swe_ipr) . the status bits in the switch global interrupt pending register (sw_ipr) are not affected. r/w 1b 4:3 reserved note: these bits must be written as 11b. r/w 11b 2 port 2 mac interrupt mask (mac_2) when set, prevents the generation of switch fabric interrupts due to the port 2 mac via the mac_ipr_2 register (see section 10.7.2.50, on page 264 ). the status bits in the switch global interrupt pending register (sw_ipr) are not affected. r/w 1b 1 port 1 mac interrupt mask (mac_1) when set, prevents the generation of switch fabric interrupts due to the port 1 mac via the mac_ipr_1 register (see section 10.7.2.50, on page 264 ). the status bits in the switch global interrupt pending register (sw_ipr) are not affected. r/w 1b 0 port 0 mac interrupt mask (mac_0) when set, prevents the generation of switch fabric interrupts due to the port 0 mac via the mac_ipr_0 register (see section 10.7.2.50, on page 264 ). the status bits in the switch global interrupt pending register (sw_ipr) are not affected. r/w 1b
? 2015 microchip technology inc. -page 237 10.7.1.4 switch global interrupt pending register (sw_ipr) this read-only register contains the pending global interrupts for the switch fabric. a set bit indicates an unmasked bit in the corresponding switch fabric sub-syst em has been triggered. all switch-relat ed interrupts in this register may be masked via the switch global interrupt mask register (sw_imr) . when an unmasked switch fabric interrupt is gen- erated in this register, t he interrupt will trigger the switch fabric interr upt event (switch_int) bit in the interrupt status register (int_sts) . refer to section 8.0, "system interrupts," on page 67 for more information. register #: 0005h size: 32 bits bits description type default 31:7 reserved ro - 6 buffer manager interrupt (bm) set when any unmasked bit in the buffer manager interrupt pending register (bm_ipr) is triggered. a read of this register clears this bit. rc 0b 5 switch engine interrupt (swe) set when any unmasked bit in the switch engine interrupt pending register (swe_ipr) is triggered. a read of this register clears this bit. rc 0b 4:3 reserved ro - 2 port 2 mac interrupt (mac_2) set when any unmasked bit in the mac_ipr_2 register (see section 10.7.2.50, on page 264 ) is triggered. a read of this register clears this bit. rc 0b 1 port 1 mac interrupt (mac_1) set when any unmasked bit in the mac_ipr_1 register (see section 10.7.2.50, on page 264 ) is triggered. a read of this register clears this bit. rc 0b 0 port 0 mac interrupt (mac_0) set when any unmasked bit in the mac_ipr_0 register (see section 10.7.2.50, on page 264 ) is triggered. a read of this register clears this bit. rc 0b
-page 238 ? 2015 microchip technology inc. 10.7.2 switch port 0, port 1 and port 2 csrs this section details the switch port 0, port 1 and port 2 csrs . each port provides a functionally identical set of registers which allow for the configuration of port settings, inte rrupts and the monitoring of the various packet counters. because the port 0, port 1 and port 2 csrs are functionally identical, their re gister descriptions have been consolidated. a lowercase ?x? has been appended to the end of each switch port register name in this section, where ?x? should be replaced with ?0?, ?1? or ?2? for the port 0, port 1 or port 2 registers respectively. a list of the switch port 0, port 1 and port 2 registers and their corresponding register numbers is included in table 10-9: . 10.7.2.1 port x mac version id register (mac_ver_id_x) this read-only register contains switch device id information, including the devi ce type, chip version and revision codes. register #: port0: 0400h size: 32 bits port1: 0800h port2: 0c00h bits description type default 31:12 reserved ro - 11:8 device type code (device_type) ro 5h 7:4 chip version code (chip_version) ro 9h 3:0 revision code (revision) ro 3h
? 2015 microchip technology inc. -page 239 10.7.2.2 port x mac re ceive configuration register (mac_rx_cfg_x) this read/write register conf igures the packet type passing parameters of the port. register #: port0: 0401h size: 32 bits port1: 0801h port2: 0c01h bits description type default 31:8 reserved ro - 7 reserved note: this bit must always be written as 0. r/w 0b 6 reserved ro - 5 enable receive own transmit when set, the switch port will receive its own transmission if it is looped back from the phy. normally, this function is only used in half-duplex phy loop- back. r/w 0b 4 reserved ro - 3 jumbo2k when set, the maximum packet size accepted is 2048 bytes. statistics boundaries are also adjusted. r/w 0b 2 reserved ro - 1 reject mac types when set, mac control frames (packets with a type field of 8808h) are fil- tered. when cleared, mac control fr ames, other than mac control pause frames, are sent to the forwarding process. mac control pause frames are always consumed by the switch. r/w 1b 0 rx enable (rxen) when set, the receive port is enabled. when cleared, the receive port is dis- abled. r/w 1b
-page 240 ? 2015 microchip technology inc. 10.7.2.3 port x mac receive undersize co unt register (mac_rx_undsze_cnt_x) this register provides a counter of undersized packets rece ived by the port. the counter is cleared upon being read. 10.7.2.4 port x mac receive 64 byte count register (mac_rx_64_cnt_x) this register provides a counter of 64 byte packets re ceived by the port. the counter is cleared upon being read. note: a bad packet is defined as a packet that has an fcs or symbol error. for this counter, a packet that is not an integral number of bytes is rounded down to the nearest byte. register #: port0: 0410h size: 32 bits port1: 0810h port2: 0c10h bits description type default 31:0 rx undersize count of packets that have less than 64 byte and a valid fcs. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 115 hours. rc 00000000h register #: port0: 0411h size: 32 bits port1: 0811h port2: 0c11h bits description type default 31:0 rx 64 bytes count of packets (including bad packets) that have exactly 64 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h
? 2015 microchip technology inc. -page 241 10.7.2.5 port x mac receive 65 to 127 byte count register (mac_rx_65_to_127_cnt_x) this register provides a counter of received packets between the size of 65 to 127 bytes. the counter is cleared upon being read. note: a bad packet is defined as a packet that has an fcs or symbol error. for this counter, a packet that is not an integral number of bytes is rounded down to the nearest byte. 10.7.2.6 port x mac receive 128 to 255 byte count register (mac_rx_128_to_255_cnt_x) this register provides a counter of received packets between the size of 128 to 255 bytes. the counter is cleared upon being read. note: a bad packet is defined as a packet that has an fcs or symbol error. for this counter, a packet that is not an integral number of bytes is rounded down to the nearest byte. register #: port0: 0412h size: 32 bits port1: 0812h port2: 0c12h bits description type default 31:0 rx 65 to 127 bytes count of packets (including bad packets) that have between 65 and 127 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 487 hours. rc 00000000h register #: port0: 0413h size: 32 bits port1: 0813h port2: 0c13h bits description type default 31:0 rx 128 to 255 bytes count of packets (including bad packets) that have between 128 and 255 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 848 hours. rc 00000000h
-page 242 ? 2015 microchip technology inc. 10.7.2.7 port x mac receive 256 to 511 byte count register (mac_rx_256_to_511_cnt_x) this register provides a counter of re ceived packets between the size of 256 to 511 bytes. the counter is cleared upon being read. note: a bad packet is defined as a packet that has an fcs or symbol error. for this counter, a packet that is not an integral number of bytes is rounded down to the nearest byte. 10.7.2.8 port x mac receive 512 to 1023 byte count register (mac_rx_512_to_1023_cnt_x) this register provides a counter of received packets between the size of 512 to 1023 bytes. the counter is cleared upon being read. note: a bad packet is defined as a packet that has an fcs or symbol error. for this counter, a packet that is not an integral number of bytes is rounded down to the nearest byte. register #: port0: 0414h size: 32 bits port1: 0814h port2: 0c14h bits description type default 31:0 rx 256 to 511 bytes count of packets (including bad packets) that have between 256 and 511 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 1581 hours. rc 00000000h register #: port0: 0415h size: 32 bits port1: 0815h port2: 0c15h bits description type default 31:0 rx 512 to 1023 bytes count of packets (including bad packets) that have between 512 and 1023 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 3047 hours. rc 00000000h
? 2015 microchip technology inc. -page 243 10.7.2.9 port x mac receive 1024 to max byte count register (mac_rx_1024_to_max_cnt_x) this register provides a counter of received packets betw een the size of 1024 to the ma ximum allowable number bytes. the counter is cleared upon being read. note: a bad packet is defined as a packet that has an fcs or symbol error. for this counter, a packet with the maximum number of bytes that is not an integral num ber of bytes (e.g., a 1518 1/2 byte packet) is counted. 10.7.2.10 port x mac receiv e oversize count register (mac_rx_ovrsze_cnt_x) this register provides a counter of received packets with a size greater than the maximum byte size. the counter is cleared upon being read. note: for this counter, a packet with the maximum number of by tes that is not an integral number of bytes (e.g., a 1518 1/2 byte packet) is not considered oversize. register #: port0: 0416h size: 32 bits port1: 0816h port2: 0c16h bits description type default 31:0 rx 1024 to max bytes count of packets (including bad packets) that have between 1024 and the maximum allowable number of bytes. the max number of bytes is 1518 for untagged packets and 1522 for tagged packets. if the jumbo2k bit is set in the port x mac receive configurat ion register (mac_rx_cfg_x) , the max number of bytes is 2048. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 5979 hours. rc 00000000h register #: port0: 0417h size: 32 bits port1: 0817h port2: 0c17h bits description type default 31:0 rx oversize count of packets that have more than the maximum allowable number of bytes and a valid fcs. the max number of bytes is 1518 for untagged pack- ets and 1522 for tagged packets. if the jumbo2k bit is set in the port x mac receive configuration re gister (mac_rx_cfg_x) , the max number of bytes is 2048. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 8813 hours. rc 00000000h
-page 244 ? 2015 microchip technology inc. 10.7.2.11 port x mac rece ive ok count register (mac_rx_pktok_cnt_x) this register provides a counter of re ceived packets that are or proper lengt h and are free of errors. the counter is cleared upon being read. note: a bad packet is one that has a fcs or symbol error. 10.7.2.12 port x mac receive crc error count register (mac_rx_crcerr_cnt_x) this register provides a counter of received packets that with crc errors. the counter is cleared upon being read. register #: port0: 0418h size: 32 bits port1: 0818h port2: 0c18h bits description type default 31:0 rx ok count of packets that are of proper length and are free of errors. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: port0: 0419h size: 32 bits port1: 0819h port2: 0c19h bits description type default 31:0 rx crc count of packets that have between 64 and the maximum allowable number of bytes and have a bad fcs, but do not have an extra nibble. the max num- ber of bytes is 1518 for untagged packets and 1522 for tagged packets. if the jumbo2k bit is set in the port x mac receive configuration register (mac_rx_cfg_x) , the max number of bytes is 2048. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 137 hours. rc 00000000h
? 2015 microchip technology inc. -page 245 10.7.2.13 port x mac receiv e multicast count register (mac_rx_mulcst_cnt_x) this register provides a count er of valid received packets with a multicas t destination address. the counter is cleared upon being read. note: a bad packet is one that has a fcs or symbol error. 10.7.2.14 port x mac receiv e broadcast count regist er (mac_rx_brdcst_cnt_x) this register provides a counter of va lid received packets with a broadcast desti nation address. the counter is cleared upon being read. note: a bad packet is one that has a fcs or symbol error. register #: port0: 041ah size: 32 bits port1: 081ah port2: 0c1ah bits description type default 31:0 rx multicast count of good packets (proper length and free of errors), including mac con- trol frames, that have a multicast de stination address (not including broad- casts). note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: port0: 041bh size: 32 bits port1: 081bh port2: 0c1bh bits description type default 31:0 rx broadcast count of valid packets (proper length and free of errors) that have a broad- cast destination address. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h
-page 246 ? 2015 microchip technology inc. 10.7.2.15 port x mac receive pause frame count register (mac_rx_pause_cnt_x) this register provides a counter of valid received pa use frame packets. the counter is cleared upon being read. note: a bad packet is one that has a fcs or symbol error. 10.7.2.16 port x mac receive fragment error count register (mac_rx_frag_cnt_x) this register provides a counter of received packets of less than 64 bytes and a fcs error. the counter is cleared upon being read. register #: port0: 041ch size: 32 bits port1: 081ch port2: 0c1ch bits description type default 31:0 rx pause frame count of valid packets (proper length and free of errors) that have a type field of 8808h and an op-code of 0001(pause). note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 481 hours. rc 00000000h register #: port0: 041dh size: 32 bits port1: 081dh port2: 0c1dh bits description type default 31:0 rx fragment count of packets that have less than 64 bytes and a fcs error. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 115 hours. rc 00000000h
? 2015 microchip technology inc. -page 247 10.7.2.17 port x mac receiv e jabber error co unt register (mac_rx_jabb_cnt_x) this register provides a count er of received packets with greater than th e maximum allowable number of bytes and a fcs error. the counter is cleared upon being read. note: for this counter, a packet with the maximum number of byte s that is not an integral number of bytes (e.g. a 1518 1/2 byte packet) and contains a fcs error is not considered jabber and is not counted here. 10.7.2.18 port x mac receive alignment error count register (mac_rx_align_cnt_x) this register provides a counter of received packets with 64 bytes to the maximum allowable and a fcs error. the counter is cleared upon being read. note: for this counter, a packet with the maximum number of byte s that is not an integral number of bytes (e.g. a 1518 1/2 byte packet) and a fcs error is considered an alignment error and is counted. register #: port0: 041eh size: 32 bits port1: 081eh port2: 0c1eh bits description type default 31:0 rx jabber count of packets that have more t han the maximum allowable number of bytes and a fcs error. the max number of bytes is 1518 for untagged packets and 1522 for tagged packets. if the jumbo2k bit is set in the port x mac receive configuration register (mac_rx_cfg_x) , the max number of bytes is 2048. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 8813 hours. rc 00000000h register #: port0: 041fh size: 32 bits port1: 081fh port2: 0c1fh bits description type default 31:0 rx alignment count of packets that have between 64 bytes and the maximum allowable number of bytes and are not byte aligned and have a bad fcs. the max number of bytes is 1518 for untagged packets and 1522 for tagged packets. if the jumbo2k bit is set in the port x mac receive configuration register (mac_rx_cfg_x) , the max number of bytes is 2048. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h
-page 248 ? 2015 microchip technology inc. 10.7.2.19 port x mac receive packet length count register (mac_rx_pktlen_cnt_x) this register provides a counter of total bytes received. the counter is cleared upon being read. note: if necessary, for oversized packets, the packet is ei ther truncated at 1518 by tes (untagged, jumbo2k=0), 1522 bytes (tagged, jumbo2k=0) or 2048 bytes (jum bo2k=1). if this occurs, the byte count recorded is 1518, 1522 or 2048, respectively. the jumbo2k bit is located in the port x mac receive configuration reg- ister (mac_rx_cfg_x) . note: a bad packet is one that has an fcs or symbol error. for this counter, a packet that is not an integral number of bytes (e.g. a 1518 1/2 byte packet) is rounded down to the nearest byte. 10.7.2.20 port x mac receive good packet leng th count register (ma c_rx_goodpktlen_cnt_x) this register provides a counter of total bytes receiv ed in good packets. the counter is cleared upon being read. note: a bad packet is one that has an fcs or symbol error. register #: port0: 0420h size: 32 bits port1: 0820h port2: 0c20h bits description type default 31:0 rx bytes count of total bytes received (including bad packets). note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 5.8 hours. rc 00000000h register #: port0: 0421h size: 32 bits port1: 0821h port2: 0c21h bits description type default 31:0 rx good bytes count of total bytes received in good packets (proper length and free of errors). note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 5.8 hours. rc 00000000h
? 2015 microchip technology inc. -page 249 10.7.2.21 port x mac receive symbol error count register (mac_rx_symbol_cnt_x) this register provides a counter of received packets with a symbol error. the counter is cleared upon being read. 10.7.2.22 port x mac receive control frame count regist er (mac_rx_ctlfrm_cnt_x) this register provides a counter of good packets with a type field of 8808h. the counter is cleared upon being read. note: a bad packet is one that has an fcs or symbol error. register #: port0: 0422h size: 32 bits port1: 0822h port2: 0c22h bits description type default 31:0 rx symbol count of packets that had a receive symbol error. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 115 hours. rc 00000000h register #: port0: 0423h size: 32 bits port1: 0823h port2: 0c23h bits description type default 31:0 rx control frame count of good packets (proper length and free of errors) that have a type field of 8808h. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h
-page 250 ? 2015 microchip technology inc. 10.7.2.23 port x rx lpi transitions register (rx_lpi_transition_x) this register indicates the number of times that the rx lpi indication fr om the phy changed from de-asserted to asserted. 10.7.2.24 port x rx lpi time register (rx_lpi_time_x) this register shows the total duration that the phy has indicated rx lpi. register #: size: 32 bits port1: 0824h port2: 0c24h bits description type default 31:0 eee rx lpi transitions count of total number of times that the rx lpi indication from the phy changed from de-asserted to asserted. the counter is reset if the energy efficient ethernet (eee_enable) bit in the port x mac transmit configur ation register (mac_tx_cfg_x) is low. ro 00000000h register #: size: 32 bits port1: 0825h port2: 0c25h bits description type default 31:0 eee rx lpi time this field shows the total duration, in microseconds, that the phy has indi- cated rx lpi. the counter is reset if the energy efficient ethernet (eee_enable) bit in the port x mac transmit configur ation register (mac_tx_cfg_x) is low. ro 00000000h
? 2015 microchip technology inc. -page 251 10.7.2.25 port x mac transmit configuration register (mac_tx_cfg_x) this read/write register c onfigures the transmit packet parameters of the port. note 17: the default value of this field is determined by the eee_enable_strap_1 or eee_enable_strap_2 configu- ration strap. the default for switch port 0 is 0. register #: port0: 0440h size: 32 bits port1: 0840h port2: 0c40h bits description type default 31:9 reserved ro - 8 energy efficient ethernet (eee_enable) when set, this bit enables eee operation (both tx lpi and rx lpi) note: for switch port 0, this bi t must always be written as 0. r/w note 17 7 mac counter test when set, tx and rx counters that normally clear to 0 when read, will be set to 7fff_fffch when read with the exception of the port x mac receive packet length count register (mac_rx_pktlen_cnt_x) , port x mac transmit packet length count register (mac_tx_pktlen_cnt_x) and port x mac receive good packet length count register (mac_rx_good- pktlen_cnt_x) counters which will be set to 7fff_ff80h. r/w 0b 6:2 ifg config these bits control the transmit inter-frame gap. ifg bit times = (ifg config * 4) + 12 note: ifg config values less than 15 are unsupported. r/w 10101b 1 tx pad enable when set, transmit packets shorter than 64 bytes are padded with zeros and will become 64 bytes in length. note: padding is used when a vlan tagged frame of less than 68 bytes is received and has its tag removed (becoming less than 64 bytes in length). r/w 1b 0 tx enable (txen) when set, the transmit port is enabled. when cleared, the transmit port is dis- abled. r/w 1b
-page 252 ? 2015 microchip technology inc. 10.7.2.26 port x mac transmit flow control settings register (mac_tx_fc_settings_x) this read/write register configures the flow control settings of the port. register #: port0: 0441h size: 32 bits port1: 0841h port2: 0c41h bits description type default 31:18 reserved ro - 17:16 backoff reset rx/tx half-duplex-only. determines when the truncated binary exponential backoff attempts counter is reset. 00 = reset on successful tr ansmission (ieee standard) 01 = reset on successful reception 1x = reset on either successful transmission or reception r/w 00b 15:0 pause time value the value that is inserted into the tr ansmitted pause packet when the switch wants to ?xoff? its link partner. r/w ffffh
? 2015 microchip technology inc. -page 253 10.7.2.27 port x eee time wait tx system register (eee_tw_tx_sys_x) this register configures the time to wait before starting packet transmission after tx lpi removal. register #: size: 32 bits port1: 0842h port2: 0c42h bits description type default 31:24 reserved ro - 23:0 tx delay after tx lpi removal this field configures the time to wait, in microseconds, before starting packet transmission after tx lpi removal. software should only change this field when the energy efficient ethernet (eee_enable) bit is cleared. note: in order to meet the ieee 80 2.3 specified re quirement, the minimum value of this field should be 00001eh. r/w 00001eh
-page 254 ? 2015 microchip technology inc. 10.7.2.28 port x eee tx lpi request de lay register (eee_tx_lpi_req_delay_x) this register contains the amount of time , in microseconds, the mac must wait after the tx fifo is empty before invok- ing the lpi protocol. note: the actual time can be up to 1 us longer than specified. note: a value of zero is valid and will cause no delay to occur. note: if the tx fifo becomes non-em pty, the timer is restarted register #: size: 32 bits port1: 0843h port2: 0c43h bits description type default 31:0 eee tx lpi request delay this field contains the time to wait, in microseconds, before invoking the lpi protocol. software should only change this field when the energy efficient ethernet (eee_enable) bit is cleared. r/w 00000000h
? 2015 microchip technology inc. -page 255 10.7.2.29 port x mac transm it deferred count regist er (mac_tx_defer_cnt_x) this register provides a counter deferred packets. the counter is cleared upon being read. 10.7.2.30 port x mac transmit pause count register (mac_tx_pause_cnt_x) this register provides a counter of transmitted p ause packets. the counter is cleared upon being read. register #: port0: 0451h size: 32 bits port1: 0851h port2: 0c51h bits description type default 31:0 tx deferred count of packets that were available for transmission but were deferred on the first transmit attempt due to netw ork traffic (either on receive or prior transmission). this counter is not incr emented on collisions. this counter is incremented only in half-duplex operation. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: port0: 0452h size: 32 bits port1: 0852h port2: 0c52h bits description type default 31:0 tx pause count of pause packets transmitted. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h
-page 256 ? 2015 microchip technology inc. 10.7.2.31 port x mac transmit ok co unt register (mac _tx_pktok_cnt_x) this register provides a counter of successful tr ansmissions. the counter is cleared upon being read. 10.7.2.32 port x mac transm it 64 byte count register (mac_tx_64_cnt_x) this register provides a counter of 64 byte packets tran smitted by the port. the counter is cleared upon being read. register #: port0: 0453h size: 32 bits port1: 0853h port2: 0c53h bits description type default 31:0 tx ok count of successful transmissions. undersize packets are not included in this count. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 481 hours. rc 00000000h register #: port0: 0454h size: 32 bits port1: 0854h port2: 0c54h bits description type default 31:0 tx 64 bytes count of packets that have exactly 64 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 481 hours. rc 00000000h
? 2015 microchip technology inc. -page 257 10.7.2.33 port x mac transmit 65 to 127 byte count register (mac_tx_65_to_127_cnt_x) this register provides a counter of trans mitted packets between the size of 65 to 127 bytes. the counter is cleared upon being read. 10.7.2.34 port x mac transmit 128 to 255 byte count register (mac_tx_128_to_255_cnt_x) this register provides a counter of transmitted packets betw een the size of 128 to 255 bytes. the counter is cleared upon being read. register #: port0: 0455h size: 32 bits port1: 0855h port2: 0c55h bits description type default 31:0 tx 65 to 127 bytes count of packets that have between 65 and 127 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 487 hours. rc 00000000h register #: port0: 0456h size: 32 bits port1: 0856h port2: 0c56h bits description type default 31:0 tx 128 to 255 bytes count of packets that have between 128 and 255 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 848 hours. rc 00000000h
-page 258 ? 2015 microchip technology inc. 10.7.2.35 port x mac transmit 256 to 511 byte count register (mac_tx_256_to_511_cnt_x) this register provides a counter of transmitted packets be tween the size of 256 to 511 bytes. the counter is cleared upon being read. 10.7.2.36 port x mac transmit 512 to 1023 byte count register (mac_tx_512_to_1023_cnt_x) this register provides a counter of transmitted packets betw een the size of 512 to 1023 by tes. the counter is cleared upon being read. register #: port0: 0457h size: 32 bits port1: 0857h port2: 0c57h bits description type default 31:0 tx 256 to 511 bytes count of packets that have between 256 and 511 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 1581 hours. rc 00000000h register #: port0: 0458h size: 32 bits port1: 0858h port2: 0c58h bits description type default 31:0 tx 512 to 1023 bytes count of packets that have between 512 and 1023 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 3047 hours. rc 00000000h
? 2015 microchip technology inc. -page 259 10.7.2.37 port x mac transmit 1024 to max byte count register (mac_tx_1024_to_max_cnt_x) this register provides a counter of transmitted packets between the size of 1024 to the maximum allowable number bytes. the counter is cleared upon being read. 10.7.2.38 port x mac transm it undersize count regist er (mac_tx_ undsze_cnt_x) this register provides a counter of undersized packets tr ansmitted by the port. the count er is cleared upon being read. register #: port0: 0459h size: 32 bits port1: 0859h port2: 0c59h bits description type default 31:0 tx 1024 to max bytes count of packets that have more than 1024 bytes. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 5979 hours. rc 00000000h register #: port0: 045ah size: 32 bits port1: 085ah port2: 0c5ah bits description type default 31:0 tx undersize count of packets that have less than 64 bytes. note: this condition could occur when tx padding is disabled and a tag is removed. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 458 hours. rc 00000000h
-page 260 ? 2015 microchip technology inc. 10.7.2.39 port x mac transmit packet le ngth count register (mac_tx_pktlen_cnt_x) this register provides a counter of total bytes transmitted. the counter is cleared upon being read. 10.7.2.40 port x mac transmit broadcast count register (mac_tx_brdcst_cnt_x) this register provides a counter of transmitted br oadcast packets. the counter is cleared upon being read. register #: port0: 045ch size: 32 bits port1: 085ch port2: 0c5ch bits description type default 31:0 tx bytes count of total bytes transmitted (does not include bytes from collisions, but does include bytes from pause packets). note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 5.8 hours. rc 00000000h register #: port0: 045dh size: 32 bits port1: 085dh port2: 0c5dh bits description type default 31:0 tx broadcast count of broadcast packets transmitted. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 481 hours. rc 00000000h
? 2015 microchip technology inc. -page 261 10.7.2.41 port x mac transm it multicast count register (mac_tx_mulcst_cnt_x) this register provides a counter of transmitted mult icast packets. the counter is cleared upon being read. 10.7.2.42 port x mac transmit late collision count regist er (mac_tx_latecol_cnt_x) this register provides a counter of tr ansmitted packets which experienced a late collision. the counter is cleared upon being read. 10.7.2.43 port x mac transmit excessive collision count r egister (mac_tx_exccol_cnt_x) this register provides a counter of transmitted packets wh ich experienced 16 collisions. the counter is cleared upon being read. register #: port0: 045eh size: 32 bits port1: 085eh port2: 0c5eh bits description type default 31:0 tx multicast count of multicast packets transmitted including mac control pause frames. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: port0: 045fh size: 32 bits port1: 085fh port2: 0c5fh bits description type default 31:0 tx late collision count of transmitted packets that experien ced a late collision. this counter is incremented only in half-duplex operation. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: port0: 0460h size: 32 bits port1: 0860h port2: 0c60h bits description type default 31:0 tx excessive collision count of transmitted packets that exper ienced 16 collisions. this counter is incremented only in half-duplex operation. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 1466 hours. rc 00000000h
-page 262 ? 2015 microchip technology inc. 10.7.2.44 port x mac transmit single collision count regist er (mac_tx_snglecol_cnt_x) this register provides a counter of transmitted packets which experienced exactl y 1 collision. the counter is cleared upon being read. 10.7.2.45 port x mac transmit multiple collision count regist er (mac_tx_multicol_cnt_x) this register provides a counter of transmitted packets which experienced between 2 and 15 collisions. the counter is cleared upon being read. 10.7.2.46 port x mac transmit total collisio n count register (mac_tx_totalcol_cnt_x) this register provides a counter of total collisions including late collisions. the counter is cleared upon being read. register #: port0: 0461h size: 32 bits port1: 0861h port2: 0c61h bits description type default 31:0 tx single collision count of transmitted packets that experienced exactly 1 collision. this counter is incremented only in half-duplex operation. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 573 hours. rc 00000000h register #: port0: 0462h size: 32 bits port1: 0862h port2: 0c62h bits description type default 31:0 tx multiple collision count of transmitted packets that experienced between 2 and 15 collisions. this counter is incremented on ly in half-duplex operation. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 664 hours. rc 00000000h register #: port0: 0463h size: 32 bits port1: 0863h port2: 0c63h bits description type default 31:0 tx total collision total count of collisions including late collisions. this counter is incremented only in half-duplex operation. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 92 hours. rc 00000000h
? 2015 microchip technology inc. -page 263 10.7.2.47 port x tx lpi transition s register (tx_lpi_transition_x) this register indicates the total numbe r of times tx lpi request to the phy changed from de-asserted to asserted. 10.7.2.48 port x tx lpi time register (tx_lpi_time_x) this register shows the total duration that tx lpi request to the phy has been asserted. register #: size: 32 bits port1: 0864h port2: 0c64h bits description type default 31:0 eee tx lpi transitions count of total number of times the tx lpi request to the phy changed from de-asserted to asserted. the counter is reset if the energy efficient ethernet (eee_enable) bit in the port x mac transmit configur ation register (mac_tx_cfg_x) is low. ro 00000000h register #: size: 32 bits port1: 0865h port2: 0c65h bits description type default 31:0 eee tx lpi time this field shows the total duration, in microseconds, that tx lpi request to the phy has been asserted. the counter is reset if the energy efficient ethernet (eee_enable) bit in the port x mac transmit configur ation register (mac_tx_cfg_x) is low. ro 00000000h
-page 264 ? 2015 microchip technology inc. 10.7.2.49 port x mac interrupt mask register (mac_imr_x) this register contains the port x interrup t mask. port x related interrupts in the port x mac interrupt pending register (mac_ipr_x) may be masked via this register. an interrupt is masked by setting the corresponding bit of this register. clearing a bit will unmask the interrupt. refer to section 8.0, "system interrupts," on page 67 for more information. note: there are no possible port x interrupt conditions availabl e. this register exists for future use and should be configured as indicated for future compatibility. 10.7.2.50 port x mac interrupt pending register (mac_ipr_x) this read-only register contains the pendi ng port x interrupts. a set bit indicates an interrupt has been triggered. all inter- rupts in this register may be masked via the port x mac interrupt pending register (mac_ipr_x) register. refer to sec- tion 8.0, "system interrupts," on page 67 for more information. note: there are no possible port x interrupt conditions available. this register exists for future use. register #: port0: 0480h size: 32 bits port1: 0880h port2: 0c80h bits description type default 31:8 reserved ro - 7:0 reserved note: these bits must be written as 11h. r/w 11h register #: port0: 0481h size: 32 bits port1: 0881h port2: 0c81h bits description type default 31:0 reserved ro -
? 2015 microchip technology inc. -page 265 10.7.3 switch engine csrs this section details the switch engine related csrs. these registers allow conf iguration and monitoring of the various switch engine components including the alr, vlan, port vi d and diffserv tables. a list of the general switch csrs and their corresponding register numbers is included in table 10-9 . 10.7.3.1 switch engine alr command register (swe_alr_cmd) this register is used to manually read and write for mac a ddresses from/into the alr table. setting any bit in this reg- ister will set the operation pending bit in the switch engine alr command status register (swe_alr_cmd_sts) and perform the specified command. only one bit should be set at a time. for a read accesses (get commands), the operation pending bit indicates when the command is finished. the switch engine alr read data 0 register (swe_alr_rd_dat_0) and the switch engine alr read data 1 register (swe_alr_rd_dat_1) can then be read. for write accesses (make command), the switch engine alr write data 0 register (swe_alr_wr_dat_0) and the switch engine alr write data 1 register (swe_alr_wr_dat_1) should first be written with the mac address and data. the operation pending bit indicates when the command is finished. register #: 1800h size: 32 bits bits description type default 31:3 reserved ro - 2 make entry when set, the contents of swe_alr_wr_dat_0 and swe_alr_wr_- dat_1 are written into the alr table. the alr logic determines the location where the entry is written. this command can also be used to change or delete a previously written or automatically learned entry. this bit self-clears once the operation is complete as indicated by a low in the operation pending bit in the switch engine alr command status register (swe_alr_cmd_sts) . this bit has no affect when written low. r/w sc 0b 1 get first entry when set, the alr read pointer is reset to the beginning of the alr table and the alr table is searched for the first valid entry, which is loaded into the swe_alr_rd_dat_0 and swe_alr_rd_dat_1 registers. this bit self-clears once the operation is complete as indicated by a low in the operation pending bit in the switch engine alr command status register (swe_alr_cmd_sts) . this bit has no affect when written low. r/w sc 0b 0 get next entry when set, the next valid entry in the alr mac address table is loaded into the swe_alr_rd_dat_0 and swe_alr_rd_dat_1 registers. this bit self-clears once the operation is complete as indicated by a low in the operation pending bit in the switch engine alr command status register (swe_alr_cmd_sts) . this bit has no affect when written low. r/w sc 0b
-page 266 ? 2015 microchip technology inc. 10.7.3.2 switch engine alr write data 0 register (swe_alr_wr_dat_0) this register is used in conjunction with the switch engine alr write data 1 register (swe_alr_wr_dat_1) and contains the first 32 bits of alr data to be written. register #: 1801h size: 32 bits bits description type default 31:0 mac address this field contains the first 32 bits of the alr entry that will be written in the alr table. these bits correspond to t he first 32 bits of the mac address. bit 0 holds the lsb of the first byte (the multicast bit). r/w 00000000h
? 2015 microchip technology inc. -page 267 10.7.3.3 switch engine alr write data 1 register (swe_alr_wr_dat_1) this register is used in conjunction with the switch engine alr write data 0 register (swe_alr_wr_dat_0) and contains the last 32 bits of alr data to be written. register #: 1802h size: 32 bits bits description type default 31:27 reserved ro - 26 valid when set, this bit makes the entry valid. it can be cleared to invalidate a pre- vious entry that contained the specified mac address. r/w 0b 25 age 1/override this bit is used by the aging and forwarding processes. if the static bit of this register is cleared, th is bit is the msb of the aging timer. software should set this bit so that the entry will age in the normal amount of time. if the static bit is set, this bit is used as a port state override bit. when set, packets received with a destination address that matches the mac address in the swe_alr_wr_dat_1 and swe_alr_wr_dat_0 registers will be forwarded regardless of the port state (except the disabled state) of the ingress or egress port(s). this is typically used to allow the reception of bpdu packets in the non-forwarding state. r/w 0b 24 static when this bit is set, this entry will not be removed by the aging process and/ or be changed by the learning process. when this bit is cleared, this entry will be automatically removed after 5 to 10 minutes of inactivity. inactivity is defined as no packets being received with a source address that matches this mac address. note: this bit is normally set by software when adding manual entries. r/w 0b 23 age 0/filter this bit is used by the aging and forwarding processes. if the static bit of this register is cleared, this bit is the lsb of the aging timer. software should set this bit so that the entry will age in the normal amount of time. if the static bit is set, this bit is used to filter packets. when set, packets with a destination address that matches this mac address will be filtered. r/w 0b 22 priority enable when set, this bit enables usage of the priority field for this mac address entry. when clear, the priority field is not used. r/w 0b 21:19 priority these bits specify the priority that is used for packets with a destination address that matches this mac address. th is priority is only used if both the priority enable bit of this register and the da highest priority bit of the switch engine global ingress configuration register (swe_global_in- grss_cfg) are set. r/w 000b
-page 268 ? 2015 microchip technology inc. 18:16 port these bits indicate the port(s) associated with this mac address. when bit 18 is cleared, a single port is selected . when bit 18 is set, multiple ports are selected. r/w 000b 15:0 mac address these field contains the last 16 bits of the alr entry that will be written into the alr table. they correspond to the last 16 bits of the mac address. bit 15 holds the msb of the last byte (the last bit on the wire). the first 32 bits of the mac address are located in the switch engine alr write data 0 register (swe_alr_wr_dat_0) . r/w 0000h bits description type default value associated port(s) 000 port 0 001 port 1 010 port 2 011 reserved 100 port 0 and port 1 101 port 0 and port 2 110 port 1 and port 2 111 port 0, port 1 and port 2
? 2015 microchip technology inc. -page 269 10.7.3.4 switch engine alr read data 0 register (swe_alr_rd_dat_0) this register is used in conjunction with the switch engine alr read data 1 register (swe_alr_rd_dat_1) to read the alr table. it contains the first 32 bits of the alr entry and is loaded via the get first entry or get next entry com- mands in the switch engine alr command register (swe_alr_cmd) . this register is only valid when either of the valid or end of table bits in the switch engine alr read data 1 register (swe_alr_rd_dat_1) are set. register #: 1805h size: 32 bits bits description type default 31:0 mac address this field contains the first 32 bits of the alr entry. these bits correspond to the first 32 bits of the mac address. bit 0 holds the lsb of the first byte (the multicast bit). ro 00000000h
-page 270 ? 2015 microchip technology inc. 10.7.3.5 switch engine alr read data 1 register (swe_alr_rd_dat_1) this register is used in conjunction with the switch engine alr read data 0 register (swe_alr_rd_dat_0) to read the alr table. it contains the last 32 bits of the alr entry and is loaded via the get first entry or get next entry com- mands in the switch engine alr command register (swe_alr_cmd) . this register is only valid when either of the valid or end of table bits are set. register #: 1806h size: 32 bits bits description type default 31:28 reserved ro - 27 end of table this bit indicates that the end of the alr table has been reached and further get next entry commands are not required. note: the valid bit may or may not be set when the end of the table is reached. ro 0b 26 valid this bit clears when the get first entry or get next entry bits of the switch engine alr command register (swe_alr_cmd) are written. this bit sets when a valid entry is found in the alr table. this bit stays cleared if the top of the alr table is reached without finding an entry. ro 0b 25 age 1/override this bit is used by the aging and forwarding processes. if the static bit of this register is cleared, th is bit is the msb of the aging timer. software should set this bit so that the entry will age in the normal amount of time. if the static bit is set, this bit is used as a port state override bit. when set, packets received with a destination address that matches the mac address in the swe_alr_wr_dat_1 and swe_alr_wr_dat_0 registers will be forwarded regardless of the port state (except the disabled state) of the ingress or egress port(s). this is typically used to allow the reception of bpdu packets in the non-forwarding state. ro 0b 24 static indicates that this entry will not be re moved by the aging process. when this bit is cleared, this entry will be automatically removed after 5 to 10 minutes of inactivity. inactivity is defined as no packets being received with a source address that matches this mac address. ro 0b 23 age 0/filter this bit is used by the aging and forwarding processes. if the static bit of this register is cleared, this bit is the lsb of the aging timer. software should set this bit so that the entry will age in the normal amount of time. if the static bit is set, this bit is used to filter packets. when set, packets with a destination address that matches this mac address will be filtered. ro 0b 22 priority enable indicates whether or not the usage of the priority field is enabled for this mac address entry. ro 0b
? 2015 microchip technology inc. -page 271 21:19 priority these bits specify the priority that is used for packets with a destination address that matches this mac address. th is priority is only used if both the priority enable bit of this register and the da highest priority bit in the switch engine global ingress configuration register (swe_global_in- grss_cfg) are set. ro 000b 18:16 port these bits indicate the port(s) associated with this mac address. when bit 18 is cleared, a single port is selected . when bit 18 is set, multiple ports are selected. ro 000b 15:0 mac address these field contains the last 16 bits of the alr entry. they correspond to the last 16 bits of the mac address. bit 15 holds the msb of the last byte (the last bit on the wire). the first 32 bits of the mac address are located in the switch engine alr read data 0 register (swe_alr_rd_dat_0) . ro 0000h bits description type default value associated port(s) 000 port 0 001 port 1 010 port 2 011 reserved 100 port 0 and port 1 101 port 0 and port 2 110 port 1 and port 2 111 port 0, port 1 and port 2
-page 272 ? 2015 microchip technology inc. 10.7.3.6 switch engine alr command status register (swe_alr_cmd_sts) this register indicates the current alr command status. note 18: the default value of this bit is 0 immediately followin g any switch fabric reset and then self-sets to 1 once the alr table is initialized. register #: 1808h size: 32 bits bits description type default 31:2 reserved ro - 1 alr init done when set, indicates that the alr table has finished being initialized by the reset process. the initialization is performed upon any reset that resets the switch fabric. the initialization takes a pproximately 20 s. during this time, any received packet will be dropped. software should monitor this bit before writing any of the alr tables or registers. ro ss note 18 0 operation pending when set, indicates that the alr command is taking place. this bit self- clears once the alr command has finished. ro sc 0b
? 2015 microchip technology inc. -page 273 10.7.3.7 switch engine alr configuration register (swe_alr_cfg) this register controls the alr aging timer du ration and the allowance of broadcast entries. register #: 1809h size: 32 bits bits description type default 31:28 reserved ro - 27:16 aging time this field sets the minimum time to age mac addresses from the alr table. the time is specified in 1 second incr ements plus 1 second. a value of 0 is 1 second, a value of 1 is 2 seconds, etc. the maxi mum value of fffh is approximately 69 minutes. the default sets a minimum time of 300 seconds. r/w 129h 15:3 reserved ro - 2 allow broadcast entries when set, this bit allows the use of the broadcast mac address in the alr table. r/w 0b 1 alr age enable when set, this bit enables the aging process. r/w 1b 0 alr age test when set, this bit changes the aging timer from seconds to milliseconds. r/w 0b
-page 274 ? 2015 microchip technology inc. 10.7.3.8 switch engine alr override register (swe_alr_override) this register controls the alr destination override function. register #: 180ah size: 32 bits bits description type default 31:11 reserved ro - 10:9 alr override destination port 2 when the alr override enable port 2 bit is set, packets received on port 2 are sent to the port(s) specified by this field. r/w 00b 8 alr override enable port 2 when set, the alr destination mac address lookup result for packets received on port 2 are ignored and replaced with the value in alr override destination port 2 . note: the alr associated data age 1/override , static , age 0/filter , priority enable and priority are still used. note: forwarding rules described in section 10.3.2 are still followed. r/w 0b 7 reserved ro - 6:5 alr override destination port 1 when the alr override enable port 1 bit is set, packets received on port 1 are sent to the port(s) specified by this field. r/w 00b 4 alr override enable port 1 when set, the alr destination mac address lookup result for packets received on port 1 are ignored and replaced with the value in alr override destination port 1 . note: the alr associated data age 1/override , static , age 0/filter , priority enable and priority are still used. note: forwarding rules described in section 10.3.2 are still followed. r/w 0b 3 reserved ro - value port(s) 00 port 0 01 port 1 10 reserved 11 reserved value port(s) 00 port 0 01 reserved 10 port 2 11 reserved
? 2015 microchip technology inc. -page 275 2:1 alr override destination port 0 when the alr override enable port 0 bit is set, packets received on port 0 are sent to the port(s) specified by this field. r/w 00b 0 alr override enable port 0 when set, the alr destination mac address lookup result for packets received on port 0 are ignored and replaced with the value in alr override destination port 0 . note: the alr associated data age 1/override , static , age 0/filter , priority enable and priority are still used. note: forwarding rules described in section 10.3.2 are still followed. r/w 0b bits description type default value port(s) 00 reserved 01 port 1 10 port 2 11 reserved
-page 276 ? 2015 microchip technology inc. 10.7.3.9 switch engine vlan command register (swe_vlan_cmd) this register is used to read and write the vlan or port vid tables. a write to this address performs the specified access. for a read access, the operation pending bit in the switch engine vlan command status register (swe_vlan_c- md_sts) indicates when the command is finished. the switch engine vlan read data register (swe_vlan_rd_- data) can then be read. for a write access, the switch engine vlan write data register (swe_vlan_wr_data) should be written first. the operation pending bit in the switch engine vlan command status register (swe_vlan_cmd_sts) indicates when the command is finished. register #: 180bh size: 32 bits bits description type default 31:6 reserved ro - 5 vlan rnw this bit specifies a read(1) or a write(0) command. r/w 0b 4 pvidnvlan when set, this bit selects the port vid table. when cleared, this bit selects the vlan table. r/w 0b 3:0 vlan/port this field specifies the vlan(0-15) or port(0-2) to be read or written. note: values outside of the valid range may cause unexpected results. r/w 0h
? 2015 microchip technology inc. -page 277 10.7.3.10 switch engine vlan write data register (swe_vlan_wr_data) this register is used write the vlan or port vid tables. register #: 180ch size: 32 bits bits description type default 31:18 reserved ro -
-page 278 ? 2015 microchip technology inc. 17:0 port default vi d and priority when the port vid table is selected (pvidnvlan=1 of the switch engine vlan command register (swe_vlan_cmd) ), bits 11:0 of this field specify the default vid for the port, bits 14:12 sp ecify the default priority for packets with a non-broadcast destination mac address and bits 17:15 specify the default priority for packets with a broadcast destination mac address. all other bits of this field are reserved. these bits are used when a packet is received without a vlan tag or with a null vlan id. the default vid is also used when the 802.1q vlan disable bit is set. the default priority is also used when no other priority choice is selected. by default, the vid for all three ports is 1 and the priorities for all three ports is 0. note: values of 0 and fffh should not be used since they are special vlan ids per the ieee 802.3q specification. vlan data when the vlan table is selected (pvidnvlan=0 of the switch engine vlan command register (swe_vlan_cmd) ), the bits form the vlan table entry as follows: r/w 00 0000 0000 0000 0000b bits description type default bits description default 17 member port 2 indicates the configuration of port 2 for this vlan entry. 1 = member - packets with a vid that matches this entry are allowed on ingress. the port is a member of the broadcast domain on egress. 0 = not a member - packets with a vid that matches this entry are filtered on ingress unless the admit non member bit in the switch engine admit non member register (swe_admt_n_member) is set for this port. the port is not a member of the broadcast domain on egress. 0b 16 un-tag port 2 when this bit is set, packets with a vid that matches this entry will have their tag removed when re- transmitted on port 2 when it is designated as a hybrid port via the buffer manager egress port type register (bm_egrss_port_type) . 0b 15 member port 1 see description for member port 2. 0b 14 un-tag port 1 see description for un-tag port 2. 0b 13 member port 0 see description for member port 2. 0b 12 un-tag port 0 see description for un-tag port 2. 0b 11:0 vid these bits specify the vlan id associated with this vlan entry. to disable a vlan entry, a value of 0 should be used. note: a value of 0 is considered a null vlan and should not normally be used other than to disable a vlan entry. note: a value of 3ffh is considered reserved by ieee 802.1q and should not be used. 000h
? 2015 microchip technology inc. -page 279 10.7.3.11 switch engine vlan read data register (swe_vlan_rd_data) this register is used to read the vlan or port vid tables. register #: 180eh size: 32 bits bits description type default 31:18 reserved ro -
-page 280 ? 2015 microchip technology inc. 17:0 port default vi d and priority when the port vid table is selected (pvidnvlan=1 of the switch engine vlan command register (swe_vlan_cmd) ), bits 11:0 of this field specify the default vid for the port, bits 14:12 sp ecify the default priority for packets with a non-broadcast destination mac address and bits 17:15 specify the default priority for packets with a broadcast destination mac address. all other bits of this field are reserved. these bits are used when a packet is received without a vlan tag or with a null vlan id. the default vid is also used when the 802.1q vlan disable bit is set. the default priority is also used when no other priority choice is selected. by default, the vid for all three ports is 1 and the priorities for all three ports is 0. note: values of 0 and fffh should not be used since they are special vlan ids per the ieee 802.3q specification. vlan data when the vlan table is selected (pvidnvlan=0 of the switch engine vlan command register (swe_vlan_cmd) ), the bits form the vlan table entry as follows: ro 00 0000 0000 0000 0000b bits description type default bits description default 17 member port 2 indicates the configuration of port 2 for this vlan entry. 1 = member - packets with a vid that matches this entry are allowed on ingress. the port is a member of the broadcast domain on egress. 0 = not a member - packets with a vid that matches this entry are filtered on ingress unless the admit non member bit in the switch engine admit non member register (swe_admt_n_member) is set for this port. the port is not a member of the broadcast domain on egress. 0b 16 un-tag port 2 when this bit is set, packets with a vid that matches this entry will have their tag removed when re- transmitted on port 2 when it is designated as a hybrid port via the buffer manager egress port type register (bm_egrss_port_type) . 0b 15 member port 1 see description for member port 2. 0b 14 un-tag port 1 see description for un-tag port 2. 0b 13 member port 0 see description for member port 2. 0b 12 un-tag port 0 see description for un-tag port 2. 0b 11:0 vid these bits specify the vlan id associated with this vlan entry. to disable a vlan entry, a value of 0 should be used. note: a value of 0 is considered a null vlan and should not normally be used other than to disable a vlan entry. note: a value of 3ffh is considered reserved by ieee 802.1q and should not be used. 000h
? 2015 microchip technology inc. -page 281 10.7.3.12 switch engine vlan command status register (swe_vlan_cmd_sts) this register indicates the current vlan command status. 10.7.3.13 switch engine diffserv table command register (swe_diffserv_tbl_cfg) this register is used to read and writ e the diffserv table. a write to this a ddress performs the specified access. this table is used to map the received ip tos/cs to a priority. for a read access, the operation pending bit in the switch engine diffserv table co mmand status register (swe_- diffserv_tbl_cmd_sts) indicates when the command is finished. the switch engine diffserv table read data register (swe_diffserv_tbl_rd_data) can then be read. for a write access, the switch engine diffserv table write data register (swe_diffserv_tbl_wr_data) should be written first. the operation pending bit in the switch engine diffserv table command status register (swe_diffserv_tbl_cmd_sts) indicates when the command is finished. register #: 1810h size: 32 bits bits description type default 31:1 reserved ro - 0 operation pending when set, this bit indicates that the read or write command is taking place. this bit self-clears once the command has finished. ro sc 0b register #: 1811h size: 32 bits bits description type default 31:8 reserved ro - 7 diffserv table rnw this bit specifies a read(1) or a write(0) command. r/w 0b 6 reserved ro - 5:0 diffserv table index this field specifies the tos/ cs entry that is accessed. r/w 000000b
-page 282 ? 2015 microchip technology inc. 10.7.3.14 switch engine diffserv table write data register (swe_diffserv_tbl_wr_data) this register is used to write the diffserv table. the diffserv table is not initialized upon reset on power-up. if diffserv is enabled, the full table should be initialized by the host. 10.7.3.15 switch engine diffserv table read data register (swe_diffserv_tbl_rd_data) this register is used to read the diffserv table. 10.7.3.16 switch engine diffserv table command status register (swe_diffserv_tbl_cmd_sts) this register indicates the current diffserv command status. register #: 1812h size: 32 bits bits description type default 31:3 reserved ro - 2:0 diffserv priority these bits specify the assigned receive priority for ip packets with a tos/cs field that matches this index. r/w 000b register #: 1813h size: 32 bits bits description type default 31:3 reserved ro - 2:0 diffserv priority these bits specify the assigned receive priority for ip packets with a tos/cs field that matches this index. ro 000b register #: 1814h size: 32 bits bits description type default 31:1 reserved ro - 0 operation pending when set, this bit indicates that the read or write command is taking place. this bit self-clears once the command has finished. ro sc 0b
? 2015 microchip technology inc. -page 283 10.7.3.17 switch engine global ingress conf iguration register (swe_global_ingrss_cfg) this register is used to configure the global ingress rules. register #: 1840h size: 32 bits bits description type default 31:18 reserved ro - 17 enable other mld next headers when set, next header values of 43, 44, 50, 51 and 60 are also used when monitoring mld packets. r/w 0b 16 enable any mld hop-by-hop next header when set, the next header value in the ipv6 hop-by-hop options header is ignore when monitoring mld packets. r/w 0b 15 802.1q vlan disable when set, the vid from the vlan tag is ignored and the per port default vid (pvid) is used for purposes of vlan rules. this does not affect the packet tag on egress. r/w 0b 14 use tag when set, the priority from the vlan ta g is enabled as a transmit priority queue choice. r/w 0b 13 allow monitor echo when set, monitoring packets are allowed to be echoed back to the source port. when cleared, monitoring packets, like other packets, are never sent back to the source port. this bit is useful when the monitor port wishes to receive its own mld/igmp packets. r/w 0b 12:10 mld/igmp monitor port this field is the port bit map where ipv6 mld packets and ipv4 igmp pack- ets are sent. r/w 0b 9 use ip when set, the ipv4 tos or ipv6 sc field is enabled as a transmit priority queue choice. r/w 0b 8 enable mld monitoring when set, ipv6 multicast listening discovery packets are monitored and sent to the mld/igmp monitoring port. r/w 0b 7 enable igmp monitoring when set, ipv4 igmp packets are moni tored and sent to the mld/igmp monitor port. r/w 0b 6 swe counter test when this bit is set the switch engine counters that normally clear to 0 when read will be set to 7fff_fffch when read. r/w 0b 5 da highest priority when this bit is set and the priority enable bit in the alr table for the destina- tion mac address is set, the transmit prio rity queue that is selected is taken from the alr priority bits (see the switch engine alr read data 1 register (swe_alr_rd_dat_1) ). r/w 0b
-page 284 ? 2015 microchip technology inc. 4 filter multicast when this bit is set, packets with a multic ast destination address are filtered if the address is not found in the alr table. broadcasts are not included in this filter. r/w 0b 3 drop unknown when this bit is set, packets with a unica st destination address are filtered if the address is not found in the alr table. r/w 0b 2 use precedence when the priority is taken from an ipv4 packet (enabled via the use ip bit), this bit selects between precedence bits in the tos octet or the diffserv table. when set, ipv4 packets will use the precedence bits in the tos octet to select the transmit priority queue. when cleared, ipv4 packets will use the diffserv table to select the transmit priority queue. r/w 1b 1 vl higher priority when this bit is set and vlan priority is enabled (via the use tag bit), the pri- ority from the vlan tag has higher priority than the ip tos/sc field. r/w 1b 0 vlan enable when set, vlan ingress rules are enabled. r/w 0b bits description type default
? 2015 microchip technology inc. -page 285 10.7.3.18 switch engine port ingress conf iguration register (swe_port_ingrss_cfg) this register is used to configure the per port ingress rules. register #: 1841h size: 32 bits bits description type default 31:6 reserved ro - 5:3 enable learning on ingress when set, source addresses are learned when a packet is received on the corresponding port and the corresponding port state in the switch engine port state register (swe_port_state) is set to forwarding or learning. there is one enable bit per ingress port. bits 5,4,3 correspond to switch ports 2,1,0 respectively. r/w 111b 2:0 enable membership checking when set, vlan membership is checked when a packet is received on the corresponding port. the packet will be filtered if the ingre ss port is not a member of the vlan (unless the admit non member bit is set for the port in the switch engine admit non member regist er (swe_admt_n_member) ). for destination addresses that are found in the alr table, the packet will be filtered if the egress port is not a me mber of the vlan (for destination addresses that are not found in the alr table only the ingress port is checked for membership). the vlan enable bit in the switch engine global ingress configuration reg- ister (swe_glo bal_ingrss_cfg) needs to be set for these bits to have an affect. there is one enable bit per ingress port. bits 2,1,0 correspond to switch ports 2,1,0 respectively. r/w 000b
-page 286 ? 2015 microchip technology inc. 10.7.3.19 switch engine admit only vlan register (swe_admt_only_vlan) this register is used to configure the per port ingress rule for allowing only vlan tagged packets. register #: 1842h size: 32 bits bits description type default 31:3 reserved ro - 2:0 admit only vlan when set, untagged and priority tagged packets are filtered. the vlan enable bit in the switch engine global ingress configuration reg- ister (swe_glo bal_ingrss_cfg) needs to be set for these bits to have an affect. there is one enable bit per ingress port. bits 2,1,0 correspond to switch ports 2,1,0 respectively. r/w 000b
? 2015 microchip technology inc. -page 287 10.7.3.20 switch engine port state register (swe_port_state) this register is used to confi gure the per port spanning tree state. register #: 1843h size: 32 bits bits description type default 31:6 reserved ro - 5:4 port state port 2 these bits specify the spanning tree port states for port 2. 00 = forwarding 01 = listening/blocking 10 = learning 11 = disabled r/w 00b 3:2 port state port 1 these bits specify the spanning tree port states for port 1. 00 = forwarding 01 = listening/blocking 10 = learning 11 = disabled r/w 00b 1:0 port state port 0 these bits specify the spanning tree port states for port 0. 00 = forwarding 01 = listening/blocking 10 = learning 11 = disabled r/w 00b
-page 288 ? 2015 microchip technology inc. 10.7.3.21 switch engine priority to queue register (swe_pri_to_que) this register specifies the traffic class table th at maps the packet priority into the egress queues. register #: 1845h size: 32 bits bits description type default 31:16 reserved ro - 15:14 priority 7 traffic class these bits specify the egress queue that is used for packets with a priority of 7. r/w 11b 13:12 priority 6 traffic class these bits specify the egress queue that is used for packets with a priority of 6. r/w 11b 11:10 priority 5 traffic class these bits specify the egress queue that is used for packets with a priority of 5. r/w 10b 9:8 priority 4 traffic class these bits specify the egress queue that is used for packets with a priority of 4. r/w 10b 7:6 priority 3 traffic class these bits specify the egress queue that is used for packets with a priority of 3. r/w 01b 5:4 priority 2 traffic class these bits specify the egress queue that is used for packets with a priority of 2. r/w 00b 3:2 priority 1 traffic class these bits specify the egress queue that is used for packets with a priority of 1. r/w 00b 1:0 priority 0 traffic class these bits specify the egress queue that is used for packets with a priority of 0. r/w 01b
? 2015 microchip technology inc. -page 289 10.7.3.22 switch engine port mirroring register (swe_port_mirror) this register is used to configure port mirroring. register #: 1846h size: 32 bits bits description type default 31:9 reserved ro - 8 enable rx mirroring filtered when set, packets that would normally have been filtered are included in the receive mirroring function and are sent only to the sniffer port. when cleared, filtered packets are not mirrored. note: the ingress filtered count regist ers will still count these packets as filtered and the switch engine interrupt pending register (swe_ipr) will still register a drop interrupt. r/w 0b 7:5 sniffer port these bits specify the sniffer port that transmits packets that are monitored. bits 7,6,5 correspond to switch ports 2,1,0 respectively. note: only one port should be set as the sniffer. r/w 00b 4:2 mirrored port these bits specify if a port is to be mirrored. bits 4,3,2 correspond to switch ports 2,1,0 respectively. note: multiple ports can be set as mirrored. r/w 00b 1 enable rx mirroring this bit enables packets received on t he mirrored ports to be also sent to the sniffer port. r/w 0b 0 enable tx mirroring this bit enables packets transmitted on the mirrored ports to be also sent to the sniffer port. r/w 0b
-page 290 ? 2015 microchip technology inc. 10.7.3.23 switch engine ingress port type register (swe_ingrss_port_typ) this register is used to enable the special tagging mode used to determine the destination port based on the vlan tag contents. 10.7.3.24 switch engine broadcast th rottling register (swe_bcst_throt) this register configures the broadcast input rate throttling. register #: 1847h size: 32 bits bits description type default 31:6 reserved ro - 5:4 ingress port type port 2 a setting of 11b enables the usage of the vlan tag to specify the packet des- tination. all other values disable this feature. r/w 00b 3:2 ingress port type port 1 a setting of 11b enables the usage of the vlan tag to specify the packet des- tination. all other values disable this feature. r/w 00b 1:0 ingress port type port 0 a setting of 11b enables the usage of the vlan tag to specify the packet des- tination. all other values disable this feature. r/w 00b register #: 1848h size: 32 bits bits description type default 31:27 reserved ro - 26 broadcast throttle enable port 2 this bit enables broadcast input rate throttling on port 2. r/w 0b 25:18 broadcast throttle level port 2 these bits specify the number of bytes x 64 allowed to be received per every 1.72ms interval. r/w 00000010b 17 broadcast throttle enable port 1 this bit enables broadcast input rate throttling on port 1. r/w 0b 16:9 broadcast throttle level port 1 these bits specify the number of bytes x 64 allowed to be received per every 1.72 ms interval. r/w 00000010b 8 broadcast throttle enable port 0 this bit enables broadcast input rate throttling on port 0. r/w 0b 7:0 broadcast throttle level port 0 these bits specify the number of bytes x 64 allowed to be received per every 1.72 ms interval. r/w 00000010b
? 2015 microchip technology inc. -page 291 10.7.3.25 switch engine admit non me mber register (swe_admt_n_member) this register is used to allow access to a vlan even if the ingress port is not a member. 10.7.3.26 switch engine ingress rate configuration register (swe_ingrss_rate_cfg) this register, along with the settings accessible via the switch engine ingress rate command register (swe_in- grss_rate_cmd) , is used to configure the ingress rate metering/coloring. register #: 1849h size: 32 bits bits description type default 31:3 reserved ro - 2:0 admit non member when set, a received packet is accepted even if the ingress port is not a member of the destination vlan. the vlan still must be active in the switch. there is one bit per ingress port. bits 2,1,0 correspond to switch ports 2,1,0 respectively. r/w 000b register #: 184ah size: 32 bits bits description type default 31:3 reserved ro - 2:1 rate mode these bits configure the rate metering/coloring mode. 00 = source port & priority 01 = source port only 10 = priority only 11 = reserved r/w 00b 0 ingress rate enable when set, ingress rates are metered and packets are colored and dropped if necessary. r/w 0b
-page 292 ? 2015 microchip technology inc. 10.7.3.27 switch engine in gress rate command register (swe_ingrss_rate_cmd) this register is used to indirectly read and write the ingress rate metering/color table registers. a write to this address performs the specified access. for a read access, the operation pending bit in the switch engine ingress rate co mmand status register (swe_in- grss_rate_cmd_sts) indicates when the command is finished. the switch engine ingress rate read data reg- ister (swe_ingrss_rate_rd_data) can then be read. for a write access, the switch engine ingress rate write data register (swe_ingrss_rate_wr_data) should be written first. the operation pending bit in the switch engine ingress rate co mmand status register (swe_in- grss_rate_cmd_sts) indicates when the command is finished. for details on 16-bit wide ingress rate table regist ers indirectly accessible by this register, see ingress rate table registers below. register #: 184bh size: 32 bits bits description type default 31:8 reserved ro - 7 ingress rate rnw these bits specify a read(1) or write(0) command. r/w 0b 6:5 type these bits select between the ingress rate metering/color table registers as follows: 00 = reserved 01 = committed information rate registers (uses cis address field) 10 = committed burst register 11 = excess burst register r/w 00b 4:0 cir address these bits select one of the 24 committed information rate registers. when rate mode is set to source port & priority in the switch engine ingress rate configuration regist er (swe_ingrss_rate_cfg) , the first set of 8 registers (cir addresses 0-7) are for to port 0, the second set of 8 registers (cir addresses 8-15) are for port 1 and the third set of registers (cir addresses 16-23) are for port 2. priority 0 is the lower register of each set (e.g., 0, 8 and 16). when rate mode is set to source port only, the first register (cir address 0) is for port 0, the second register (cir address 1) is for port 1 and the third register (cir address 2) is for port 2. when rate mode is set to priority only, the first register (cir address 0) is for priority 0, the second register (cir address 1) is for priority 1 and so forth up to priority 23. note: values outside of the valid range may cause unexpected results. r/w 00000b
? 2015 microchip technology inc. -page 293 ingress rate table registers the ingress rate metering/color table consists of 24 committ ed information rate (cir) regi sters (one per port/priority), a committed burst size register and an excess burst size regi ster. all metering/color table registers are 16-bits in size and are accessed indirectly via the switch engine ingress rate command register (swe_ingrss_rate_cmd) . descriptions of these registers are detailed in table 10-10 below. table 10-10: metering/color table register descriptions description type default excess burst size this register specifies the maximum excess burst size in bytes. bursts larger than this value that exceed the excess data rate are dropped. note: either this value or the committed burst size should be set larger than or equal to the largest possible packet expected. note: all of the excess burst token buckets ar e initialized to this default value. if a lower value is programmed into this register, the token buckets will need to be normally depleted below this value before this value has any affect on limiting the to ken bucket maximum values. this register is 16-bits wide. r/w 0600h committed burst size this register specifies the maximum committed burst size in bytes. bursts larger than this value that exceed the committed data rate are subjected to random drop- ping. note: either this value or the excess burs t size should be set larger than or equal to the largest possible packet expected. note: all of the committed burst token bucke ts are initialized to this default value. if a lower value is programmed into this register, the token buckets will need to be normally depleted below this value before this value has any affect on limiting the token bucket maximum values. this register is 16-bits wide. r/w 0600h committed informati on rate (cir) these registers specify the co mmitted data rate for the port/priority pair. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. there are 24 of these r egisters each 16-bits wide. r/w 0014h
-page 294 ? 2015 microchip technology inc. 10.7.3.28 switch engine ingres s rate command status register (swe_ingrss_rate_cmd_sts) this register indicates the current ingress rate command status. 10.7.3.29 switch engine ingres s rate write data register (swe_ingrss_rate_wr_data) this register is used to write the ingress rate table registers. 10.7.3.30 switch engine ingres s rate read data register (swe_ingrss_rate_rd_data) this register is used to read the ingress rate table registers. register #: 184ch size: 32 bits bits description type default 31:1 reserved ro - 0 operation pending when set, indicates that the read or wr ite command is taking place. this bit self-clears once the command has finished. ro sc 0b register #: 184dh size: 32 bits bits description type default 31:16 reserved ro - 15:0 data this is the data to be written to the in gress rate table registers as specified in the switch engine ingress rate command register (swe_in- grss_rate_cmd) . refer to ingress rate table registers on page 293 for details on these registers. r/w 0000h register #: 184eh size: 32 bits bits description type default 31:16 reserved ro - 15:0 data this is the read data from the ingress rate table registers as specified in the switch engine ingress rate command register (swe_in- grss_rate_cmd) . refer to ingress rate table registers on page 293 for details on these registers. ro 0000h
? 2015 microchip technology inc. -page 295 10.7.3.31 switch engine port 0 ingress f iltered count register (swe_filtered_cnt_0) this register counts the number of packets filtered at ingress on port 0. this c ount includes packets filtered due to broad- cast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately). 10.7.3.32 switch engine port 1 ingress f iltered count register (swe_filtered_cnt_1) this register counts the number of packets filtered at ingress on port 1. this c ount includes packets filtered due to broad- cast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately). 10.7.3.33 switch engine port 2 ingress f iltered count register (swe_filtered_cnt_2) this register counts the number of packets filtered at ingress on port 2. this c ount includes packets filtered due to broad- cast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately). register #: 1850h size: 32 bits bits description type default 31:0 filtered this field is a count of packets filter ed at ingress and is cleared when read. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: 1851h size: 32 bits bits description type default 31:0 filtered this field is a count of packets filter ed at ingress and is cleared when read. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: 1852h size: 32 bits bits description type default 31:0 filtered this field is a count of packets filter ed at ingress and is cleared when read. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h
-page 296 ? 2015 microchip technology inc. 10.7.3.34 switch engine port 0 ingress vlan priority regeneration table register (swe_ingrss_regen_tbl_0) this register provides the ability to map the received vlan priority to a regenerated priori ty. the regenerated priority is used in determining the output priority queue. by default, th e regenerated priority is identical to the received priority. register #: 1855h size: 32 bits bits description type default 31:24 reserved ro - 23:21 regen7 these bits specify the regenerated priority for received priority 7. r/w 111b 20:18 regen6 these bits specify the regenerated priority for received priority 6. r/w 110b 17:15 regen5 these bits specify the regenerated priority for received priority 5. r/w 101b 14:12 regen4 these bits specify the regenerated priority for received priority 4. r/w 100b 11:9 regen3 these bits specify the regenerated priority for received priority 3. r/w 011b 8:6 regen2 these bits specify the regenerated priority for received priority 2. r/w 010b 5:3 regen1 these bits specify the regenerated priority for received priority 1. r/w 001b 2:0 regen0 these bits specify the regenerated priority for received priority 0. r/w 000b
? 2015 microchip technology inc. -page 297 10.7.3.35 switch engine port 1 ingress vlan priority regeneration table register (swe_ingrss_regen_tbl_1) this register provides the ability to map the received vlan priority to a regenerated priori ty. the regenerated priority is used in determining the output priority queue. by default, the regen erated priority is identical to the received priority. register #: 1856h size: 32 bits bits description type default 31:24 reserved ro - 23:21 regen7 these bits specify the regenerated priority for received priority 7. r/w 111b 20:18 regen6 these bits specify the regenerated priority for received priority 6. r/w 110b 17:15 regen5 these bits specify the regenerated priority for received priority 5. r/w 101b 14:12 regen4 these bits specify the regenerated priority for received priority 4. r/w 100b 11:9 regen3 these bits specify the regenerated priority for received priority 3. r/w 011b 8:6 regen2 these bits specify the regenerated priority for received priority 2. r/w 010b 5:3 regen1 these bits specify the regenerated priority for received priority 1. r/w 001b 2:0 regen0 these bits specify the regenerated priority for received priority 0. r/w 000b
-page 298 ? 2015 microchip technology inc. 10.7.3.36 switch engine port 2 ingress vlan priority regeneration table register (swe_ingrss_regen_tbl_2) this register provides the ability to map the received vlan priority to a regenerated priori ty. the regenerated priority is used in determining the output priority queue. by default, th e regenerated priority is identical to the received priority. 10.7.3.37 switch engine port 0 learn disca rd count register (swe_lrn_discrd_cnt_0) this register counts the numb er of mac addresses on port 0 that were no t learned or were overwritten by a different address due to address table space limitations. register #: 1857h size: 32 bits bits description type default 31:24 reserved ro - 23:21 regen7 these bits specify the regenerated priority for received priority 7. r/w 111b 20:18 regen6 these bits specify the regenerated priority for received priority 6. r/w 110b 17:15 regen5 these bits specify the regenerated priority for received priority 5. r/w 101b 14:12 regen4 these bits specify the regenerated priority for received priority 4. r/w 100b 11:9 regen3 these bits specify the regenerated priority for received priority 3. r/w 011b 8:6 regen2 these bits specify the regenerated priority for received priority 2. r/w 010b 5:3 regen1 these bits specify the regenerated priority for received priority 1. r/w 001b 2:0 regen0 these bits specify the regenerated priority for received priority 0. r/w 000b register #: 1858h size: 32 bits bits description type default 31:0 learn discard this field is a count of mac addresse s not learned or overwritten and is cleared when read. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 481 hours. rc 00000000h
? 2015 microchip technology inc. -page 299 10.7.3.38 switch engine port 1 learn discard count register (swe_lrn_discrd_cnt_1) this register counts the numb er of mac addresses on port 1 that were no t learned or were overwritten by a different address due to address table space limitations. 10.7.3.39 switch engine port 2 learn discard count register (swe_lrn_discrd_cnt_2) this register counts the numb er of mac addresses on port 2 that were no t learned or were overwritten by a different address due to address table space limitations. 10.7.3.40 switch engine interr upt mask register (swe_imr) this register contains the switch engine in terrupt mask, which masks the interrupts in the switch engine interrupt pend- ing register (swe_ipr) . all switch engine interrupts are masked by settin g the interrupt mask bit. clearing this bit will unmask the interrupts. refer to section 8.0, "system interrupts," on page 67 for more information. register #: 1859h size: 32 bits bits description type default 31:0 learn discard this field is a count of mac addresse s not learned or overwritten and is cleared when read. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: 185ah size: 32 bits bits description type default 31:0 learn discard this field is a count of mac addresse s not learned or overwritten and is cleared when read. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: 1880h size: 32 bits bits description type default 31:1 reserved ro - 0 interrupt mask when set, this bit masks interrupts from th e switch engine. the status bits in the switch engine interrupt pending register (swe_ipr) are not affected. r/w 1b
-page 300 ? 2015 microchip technology inc. 10.7.3.41 switch engine interrupt pending register (swe_ipr) this register contains the switch engine interrupt status. the status is double buffered. all interrupts in this register may be masked via the switch engine interrupt mask register (swe_imr) . refer to section 8.0, "system interrupts," on page 67 for more information. register #: 1881h size: 32 bits bits description type default 31:15 reserved ro - 14:11 drop reason b when the set b valid bit is set, these bits indicate the reason a packet was dropped per the table below: rc 0000b bit values description 0000 admit only vlan was set and the packet was untagged or priority tagged. 0001 the destination address was not in the alr table (unknown or broadcast), enable membership checking on ingress was set, admit non member was cleared and the source port was not a member of the incoming vlan. 0010 the destination address was found in the alr table but the source port was not in the forwarding state. 0011 the destination address was found in the alr table but the destination port was not in the forwarding state. 0100 the destination address was found in the alr table but enable membership checking on ingress was set and the destination port was not a member of the incoming vlan. 0101 the destination address was found in the alr table but the enable membership checking on ingress was set, admit non member was cleared and the source port was not a member of the incoming vlan. 0110 drop unknown was set and the destination address was a unicast but not in the alr table. 0111 filter multicast was set and the destination address was a multicast and not in the alr table. 1000 the packet was a broadcast but exceeded the broadcast throttling limit. 1001 the destination address was not in the alr table (unknown or broadcast) and the source port was not in the forwarding state. 1010 the destination address was found in the alr table but the source and destination ports were the same. 1011 the destination address was found in the alr table and the filter bit was set for that address. 1100 reserved 1101 reserved 1110 a packet was received with a vlan id of fffh. 1111 reserved
? 2015 microchip technology inc. -page 301 10:9 source port b when the set b valid bit is set, these bits indicate the source port on which the packet was dropped. 00 = port 0 01 = port 1 10 = port 2 11 = reserved rc 00b 8 set b valid when set, bits 14:9 are valid. rc 0b 7:4 drop reason a when the set a valid bit is set, these bits indicate the reason a packet was dropped. see the drop reason b descripti on above for definitions of each value of this field. rc 0000b 3:2 source port a when the set a valid bit is set, these bits indicate the source port on which the packet was dropped. 00 = port 0 01 = port 1 10 = port 2 11 = reserved rc 00b 1 set a valid when set, bits 7:2 are valid. rc 0b 0 interrupt pending when set, a packet dropped event(s) is indicated. rc 0b bits description type default
-page 302 ? 2015 microchip technology inc. 10.7.4 buffer manager csrs this section details the buffer manager (bm) registers. these regist ers allow configuration and monitoring of the switch buffer levels and usage. a list of the general switch csrs and their corresponding register numbers is included in table 10-9 . 10.7.4.1 buffer manager configuration register (bm_cfg) this register enables egress rate pacing and ingress rate discarding. register #: 1c00h size: 32 bits bits description type default 31:7 reserved ro - 6 bm counter test when this bit is set, buffer manager (bm) counters that normally clear to 0 when read, will be set to 7fff_fffc when read. r/w 0b 5 fixed priority queue servicing when set, output queues are serviced with a fixed priority ordering. when cleared, output queues are serviced with a weighted round robin ordering. r/w 0b 4:2 egress rate enable when set, egress rate pacing is enabled. bits 4,3,2 correspond to switch ports 2,1,0 respectively. r/w 0b 1 drop on yellow when this bit is set, packets that exceed the ingress committed burst size (colored yellow) are subjected to random discard. note: see section 10.7.3.27, "s witch engine ingress rate command register (swe_ingrss_rate_cmd)," on page 292 for information on configuring the ingress committed burst size. r/w 0b 0 drop on red when this bit is set, packets that exc eed the ingress excess burst size (col- ored red) are discarded. note: see section 10.7.3.27, "s witch engine ingress rate command register (swe_ingrss_rate_cmd)," on page 292 for information on configuring the ingress excess burst size. r/w 0b
? 2015 microchip technology inc. -page 303 10.7.4.2 buffer manager drop level register (bm_drop_lvl) this register configures t he overall buffer usage limits. 10.7.4.3 buffer manager flow control pause level register (bm_fc_pause_lvl) this register configures the buffer usage le vel when a pause frame or backpressure is sent. register #: 1c01h size: 32 bits bits description type default 31:16 reserved ro - 15:8 drop level low these bits specify the buffer limit t hat can be used per ingress port during times when 2 or 3 ports are active. each buffer is 128 bytes. note: a port is ?active? when 36 buffers are in use for that port. r/w 49h 7:0 drop level high these bits specify the buffer limit t hat can be used per ingress port during times when 1 port is active. each buffer is 128 bytes. note: a port is ?active? when 36 buffers are in use for that port. r/w 64h register #: 1c02h size: 32 bits bits description type default 31:16 reserved ro - 15:8 pause level low these bits specify the buffer usage level during times when 2 or 3 ports are active. each buffer is 128 bytes. note: a port is ?active? when 36 buffers are in use for that port. r/w 21h 7:0 pause level high these bits specify the buffer usage level during times when 1 port is active. each buffer is 128 bytes. note: a port is ?active? when 36 buffers are in use for that port. r/w 3ch
-page 304 ? 2015 microchip technology inc. 10.7.4.4 buffer manager flow control re sume level register (bm_fc_resume_lvl) this register configures the buffer usage level when a pause frame with a pause value of 1 is sent. 10.7.4.5 buffer manager broadcast buffer level register (bm_bcst_lvl) this register configures the bu ffer usage limits for broadcasts, multicasts and unknown unicasts. register #: 1c03h size: 32 bits bits description type default 31:16 reserved ro - 15:8 resume level low these bits specify the buffer usage level during times when 2 or 3 ports are active. each buffer is 128 bytes. note: a port is ?active? when 36 buffers are in use for that port. r/w 03h 7:0 resume level high these bits specify the buffer usage level during times when 0 or 1 ports are active. each buffer is 128 bytes. note: a port is ?active? when 36 buffers are in use for that port. r/w 07h register #: 1c04h size: 32 bits bits description type default 31:8 reserved ro - 7:0 broadcast drop level these bits specify the maximum number of buffers that can be used by broadcasts, multicasts and unknown unicasts. each buffer is 128 bytes. r/w 31h
? 2015 microchip technology inc. -page 305 10.7.4.6 buffer manager port 0 drop count register (bm_drp_cnt_src_0) this register counts the number of packets dropped by the buffer manager that were re ceived on port 0. this count includes packets dropped due to buffer space limits and ingre ss rate limit discarding (red and random yellow dropping). 10.7.4.7 buffer manager port 1 drop count register (bm_drp_cnt_src_1) this register counts the number of packets dropped by the buffer manager that were re ceived on port 1. this count includes packets dropped due to buffer space limits and ingre ss rate limit discarding (red and random yellow dropping). 10.7.4.8 buffer manager port 2 drop count register (bm_drp_cnt_src_2) this register counts the number of packets dropped by the buffer manager that were re ceived on port 2. this count includes packets dropped due to buffer space limits and ingre ss rate limit discarding (red and random yellow dropping). register #: 1c05h size: 32 bits bits description type default 31:0 dropped count these bits count the number of droppe d packets received on port 0 and is cleared when read. note: the counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: 1c06h size: 32 bits bits description type default 31:0 dropped count these bits count the number of droppe d packets received on port 1 and is cleared when read. note: the counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: 1c07h size: 32 bits bits description type default 31:0 dropped count these bits count the number of droppe d packets received on port 2 and is cleared when read. note: the counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h
-page 306 ? 2015 microchip technology inc. 10.7.4.9 buffer manager reset status register (bm_rst_sts) this register indicates when the buffer man ager has been initialized by the reset process. note 19: the default value of this bit is 0 immediately followin g any switch fabric reset and then self-sets to 1 once the alr table is initialized. register #: 1c08h size: 32 bits bits description type default 31:1 reserved ro - 0 bm ready when set, indicates the buffer manager tables have finished being initialized by the reset process. the initialization is performed upon any reset that resets the switch fabric. ro ss note 19
? 2015 microchip technology inc. -page 307 10.7.4.10 buffer manager random discard table command register (bm_rndm_dscrd_tbl_cmd) this register is used to read and write the random discard we ight table. a write to this address performs the specified access. this table is used to set the packet drop probability verses the buffer usage. for a read access, the buffer manager random discard table read data register (bm_rndm_dscrd_tbl_rdata) can be read following a write to this register. for a write access, the buffer manager random discard table wr ite data register (bm_rndm_dscrd_tbl_w- data) should be written before writing this register. register #: 1c09h size: 32 bits bits description type default 31:5 reserved ro - 4 random discard weight table rnw specifies a read (1) or a write (0) command. r/w 0b 3:0 random discard weight table index specifies the buffer usage range that is accessed. there are a total of 16 probability entrie s. each entry corresponds to a range of the number of buffers used by the ingress port. the ranges are structured to give more resolution towards the lower buffer usage end. r/w 0h bit values buffer usage level 0000 0 to 7 0001 8 to 15 0010 16 to 23 0011 24 to 31 0100 32 to 39 0101 40 to 47 0110 48 to 55 0111 56 to 63 1000 64 to 79 1001 80 to 95 1010 96 to 111 1011 112 to 127 1100 128 to 159 1101 160 to 191 1110 192 to 223 1111 224 to 255
-page 308 ? 2015 microchip technology inc. 10.7.4.11 buffer manager random discard table write data register (bm_rndm_dscrd_tbl_wdata) this register is used to write the random discard weight table. note: the random discard weight table is not initialized up on reset or power-up. if a random discard is enabled, the full table should be initialized by the host. 10.7.4.12 buffer manager random discard table read data register (bm_rndm_dscrd_tbl_rdata) this register is used to read the random discard weight table. register #: 1c0ah size: 32 bits bits description type default 31:10 reserved ro - 9:0 drop probability these bits specify the discard probabili ty of a packet that has been colored yellow by the ingress metering. the probability is given in 1/1024?s. for example, a setting of 1 is one in 1024 or approximately 0.1%. a setting of all ones (1023) is 1023 in 1024 or approximately 99.9%. there are a total of 16 probability entries. each entry corresponds to a range of the number of buffers used by the ingress port, as specified in section 10.7.4.10, "buffer manager random discard table command register (bm_rndm_dscrd_tbl_cmd)" . r/w 00 0000 0000b register #: 1c0bh size: 32 bits bits description type default 31:10 reserved ro - 9:0 drop probability these bits specify the discard probabili ty of a packet that has been colored yellow by the ingress metering. the probability is given in 1/1024?s. for example, a setting of 1 is one in 1024 or approximately 0.1%. a setting of all ones (1023) is 1023 in 1024 or approximately 99.9%. there are a total of 16 probability entries. each entry corresponds to a range of the number of buffers used by the ingress port, as specified in section 10.7.4.10, "buffer manager random discard table command register (bm_rndm_dscrd_tbl_cmd)" . ro 00 0000 0000b
? 2015 microchip technology inc. -page 309 10.7.4.13 buffer manager egress port type regi ster (bm_egrss_port_type) this register is used to configur e the egress vlan tagging rules. see section 10.4.6, "adding, removing and changing vlan tags," on page 202 for additional details. register #: 1c0ch size: 32 bits bits description type default 31:23 reserved ro - 22 vid/priority select port 2 this bit determines the vid and priority in inserted or changed tags. 0: the default vid of the ingress port / priority calculated on ingress. 1: the default vid / priority of the egress port. this is only used when the egress port type is set as hybrid. r/w 0b 21 insert tag port 2 when set, untagged packets will have a tag added. the vid and priority is determined by the vid/priority select port 2 bit. the un-tag bit in the vlan table for the default vlan id also needs to be cleared in order for the tag to be inserted. this is only used when the egress port type is set as hybrid. r/w 0b 20 change vlan id port 2 when set, regular tagged packets will have their vlan id overwritten with the default vlan id of either the in gress or egress port, as determined by the vid/priority select port 2 bit. the change tag bit also needs to be set. the un-tag bit in the vlan table for the incoming vlan id also needs to be cleared, otherwise the ta g will be removed instead. priority tagged packets will have their vlan id overwritten with the default vlan id of either the ingress or egress port independent of this bit. this is only used when the egress port type is set as hybrid. r/w 0b 19 change priority port 2 when set, regular tagged and priority tagged packets will have their priority overwritten with the priority determined by the vid/priority select port 2 bit. for regular tagged packets, the change tag bit also needs to be set by soft- ware. the un-tag bit in the vlan table for the incoming vlan id also needs to be cleared, otherwise the tag would be removed instead. this is only used when the egress port type is set as hybrid. r/w 0b
-page 310 ? 2015 microchip technology inc. 18 change tag port 2 when set, allows the change tag and change priority bits to affect regular tagged packets. this bit has no affect on priority tagged packets. this is only used when the egress port type is set as hybrid. r/w 0b 17:16 egress port type port 2 these bits set the egress port type wh ich determines the tagging/un-tagging rules. r/w 0b 15 reserved ro - 14 vid/priority select port 1 identical to vid/priority sele ct port 2 definition above. r/w 0b 13 insert tag port 1 identical to insert tag port 2 definition above. r/w 0b 12 change vlan id port 1 identical to change vlan id port 2 definition above. r/w 0b 11 change priority port 1 identical to change priority port 2 definition above. r/w 0b 10 change tag port 1 identical to change tag port 2 definition above. r/w 0b 9:8 egress port type port 1 identical to egress port ty pe port 2 definition above. r/w 0b 7 reserved ro - 6 vid/priority select port 0 identical to vid/priority sele ct port 2 definition above. r/w 0b 5 insert tag port 0 identical to insert tag port 2 definition above. r/w 0b 4 change vlan id port 0 identical to change vlan id port 2 definition above. r/w 0b 3 change priority port 0 identical to change priority port 2 definition above. r/w 0b bits description type default bit values egress port type 00 dumb packets from regular ports pass untouched. special tagged packets from the external mii port have their tagged stripped. 01 access tagged packets (including special tagged packets from the external mii port) have their tagged stripped. 10 hybrid supports a mix of tagging, un -tagging and changing tags. see section 10.4.6, "adding, removing and changing vlan tags," on page 202 for additional details. 11 cpu a special tag is added to indicate the source of the packet. see section 10.4.6, "adding, removing and changing vlan tags," on page 202 for additional details.
? 2015 microchip technology inc. -page 311 10.7.4.14 buffer manager port 0 egress rate priority queue 0/1 register (bm_egrss_rate_00_01) this register, along with the buffer manager configuration register (bm_cfg) , is used to configure the egress rate pac- ing. 10.7.4.15 buffer manager port 0 egress rate priority queue 2/3 register (bm_egrss_rate_02_03) this register, along with the buffer manager configuration register (bm_cfg) , is used to configure the egress rate pac- ing. 2 change tag port 0 identical to change tag port 2 definition above. r/w 0b 1:0 egress port type port 0 identical to egress port ty pe port 2 definition above. r/w 0b register #: 1c0dh size: 32 bits bits description type default 31:26 reserved ro - 25:13 egress rate port 0 priority queue 1 these bits specify the egress data rate for the port 0 priority queue 1. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b 12:0 egress rate port 0 priority queue 0 these bits specify the egress data rate for the port 0 priority queue 0. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b register #: 1c0eh size: 32 bits bits description type default 31:26 reserved ro - 25:13 egress rate port 0 priority queue 3 these bits specify the egress data rate for the port 0 priority queue 3. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b 12:0 egress rate port 0 priority queue 2 these bits specify the egress data rate for the port 0 priority queue 2. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b bits description type default
-page 312 ? 2015 microchip technology inc. 10.7.4.16 buffer manager port 1 egress rate priority queue 0/1 register (bm_egrss_rate_10_11) this register, along with the buffer manager configur ation register (bm_cfg) , is used to configure the egress rate pac- ing. 10.7.4.17 buffer manager port 1 egress rate priority queue 2/3 register (bm_egrss_rate_12_13) this register, along with the buffer manager configur ation register (bm_cfg) , is used to configure the egress rate pac- ing. register #: 1c0fh size: 32 bits bits description type default 31:26 reserved ro - 25:13 egress rate port 1 priority queue 1 these bits specify the egress data rate for the port 1 priority queue 1. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b 12:0 egress rate port 1 priority queue 0 these bits specify the egress data rate for the port 1 priority queue 0. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b register #: 1c10h size: 32 bits bits description type default 31:26 reserved ro - 25:13 egress rate port 1 priority queue 3 these bits specify the egress data rate for the port 1 priority queue 3. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b 12:0 egress rate port 1 priority queue 2 these bits specify the egress data rate for the port 1 priority queue 2. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b
? 2015 microchip technology inc. -page 313 10.7.4.18 buffer manager port 2 egress rate priority queue 0/1 register (bm_egrss_rate_20_21) this register, along with the buffer manager configuration register (bm_cfg) , is used to configure the egress rate pac- ing. 10.7.4.19 buffer manager port 2 egress rate priority queue 2/3 register (bm_egrss_rate_22_23) this register, along with the buffer manager configuration register (bm_cfg) , is used to configure the egress rate pac- ing. register #: 1c11h size: 32 bits bits description type default 31:26 reserved ro - 25:13 egress rate port 2 priority queue 1 these bits specify the egress data rate for the port 2 priority queue 1. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b 12:0 egress rate port 2 priority queue 0 these bits specify the egress data rate for the port 2 priority queue 0. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b register #: 1c12h size: 32 bits bits description type default 31:26 reserved ro - 25:13 egress rate port 2 priority queue 3 these bits specify the egress data rate for the port 2 priority queue 3. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b 12:0 egress rate port 2 priority queue 2 these bits specify the egress data rate for the port 2 priority queue 2. the rate is specified in time per byte. the time is this value plus 1 times 20 ns. r/w 00000 00000000b
-page 314 ? 2015 microchip technology inc. 10.7.4.20 buffer manager port 0 default vlan id and priority register (bm_vlan_0) this register is used to specify the default vlan id and priority of port 0. 10.7.4.21 buffer manager port 1 default vlan id and priority register (bm_vlan_1) this register is used to specify the default vlan id and priority of port 1. register #: 1c13h size: 32 bits bits description type default 31:15 reserved ro - 14:12 default priority these bits specify the default priority that is used when a tag is inserted or changed on egress. r/w 000b 11:0 default vlan id these bits specify the default that is used when a tag is inserted or changed on egress. r/w 0000 00000001b register #: 1c14h size: 32 bits bits description type default 31:15 reserved ro - 14:12 default priority these bits specify the default priority that is used when a tag is inserted or changed on egress. r/w 000b 11:0 default vlan id these bits specify the default that is used when a tag is inserted or changed on egress. r/w 0000 00000001b
? 2015 microchip technology inc. -page 315 10.7.4.22 buffer manager port 2 default vlan id and priority register (bm_vlan_2) this register is used to specify the default vlan id and priority of port 2. 10.7.4.23 buffer manager port 0 ingress rate drop count register (bm_rate_drp_cnt_src_0) this register counts the number of pa ckets received on port 0 that were dropped by the buffer manager due to ingress rate limit discarding (red and random yellow dropping). 10.7.4.24 buffer manager port 1 ingress rate drop count register (bm_rate_drp_cnt_src_1) this register counts the number of pa ckets received on port 1 that were dropped by the buffer manager due to ingress rate limit discarding (red and random yellow dropping). register #: 1c15h size: 32 bits bits description type default 31:15 reserved ro - 14:12 default priority these bits specify the default priority that is used when a tag is inserted or changed on egress. r/w 000b 11:0 default vlan id these bits specify the default that is used when a tag is inserted or changed on egress. r/w 0000 00000001b register #: 1c16h size: 32 bits bits description type default 31:0 dropped count these bits count the number of droppe d packets received on port 0 and is cleared when read. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h register #: 1c17h size: 32 bits bits description type default 31:0 dropped count these bits count the number of droppe d packets received on port 1 and is cleared when read. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. rc 00000000h
-page 316 ? 2015 microchip technology inc. 10.7.4.25 buffer manager port 2 ingress rate drop count register (bm_rate_drp_cnt_src_2) this register counts the number of pa ckets received on port 2 that were dropped by the buffer manager due to ingress rate limit discarding (red and random yellow dropping). 10.7.4.26 buffer manager interrupt mask register (bm_imr) this register contains the buffer manager in terrupt mask, which masks the interrupts in the buffer manager interrupt pending register (bm_ipr) . all buffer manager interrupts are masked by setting the interrupt mask bit. clearing this bit will unmask the interrupts. refer to section 8.0, "system interrupts," on page 67 for more information. register #: 1c18h size: 32 bits bits description type default 31:0 dropped count these bits count the number of droppe d packets received on port 2 and is cleared when read. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 481 hours. rc 00000000h register #: 1c20h size: 32 bits bits description type default 31:1 reserved ro - 0 interrupt mask when set, this bit masks interrupts from the buffer manager. the status bits in the buffer manager interrupt pending register (bm_ipr) are not affected. r/w 1b
? 2015 microchip technology inc. -page 317 10.7.4.27 buffer manager interrupt pending register (bm_ipr) this register contains the buffer manager interrupt status. the status is double buffered. all interrupts in this register may be masked via the buffer manager interrupt mask register (bm_imr) . refer to section 8.0, "system interrupts," on page 67 for more information. register #: 1c21h size: 32 bits bits description type default 31:14 reserved ro - 13:10 drop reason b when the status b pending bit is set, t hese bits indicate the reason a packet was dropped per the table below: rc 0000b 9:8 source port b when the status b pending bit is set, these bits indicate the source port on which the packet was dropped. 00 = port 0 01 = port 1 10 = port 2 11 = reserved rc 00b bit values description 0000 the destination address was not in the alr table (unknown or broadcast) and the broadcast buffer level was exceeded. 0001 drop on red was set and the packet was colored red. 0010 there were no buffers available. 0011 there were no memory descriptors available. 0100 the destination address was not in the alr table (unknown or broadcast) and there were no valid destination ports. 0101 the packet had a receive error and was >64 bytes. 0110 the buffer drop level was exceeded. 0111 reserved 1000 reserved 1001 drop on yellow was set, the packet was colored yellow and was randomly selected to be dropped. 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
-page 318 ? 2015 microchip technology inc. 7 status b pending when set, bits 13:8 are valid. rc 0b 6:3 drop reason a when the set a valid bit is set, these bits indicate the reason a packet was dropped. see the drop reason b descripti on above for definitions of each value of this field. rc 0000b 2:1 source port a when the set a valid bit is set, these bits indicate the source port on which the packet was dropped. 00 = port 0 01 = port 1 10 = port 2 11 = reserved rc 00b 0 set a valid when set, bits 6:1 are valid. rc 0b bits description type default
? 2015 microchip technology inc. -page 319 11.0 i 2 c slave controller 11.1 functional overview this chapter details the i 2 c slave controller provided by the device. the i 2 c slave controller can be used for cpu serial management and allows cpu access to all system csrs. the i 2 c slave controller implements the low level i 2 c slave serial interface (start and stop condition detection, dat a bit transmission/reception and acknowledge generation/recep- tion), handles the slave command protocol and perfo rms system register r eads and writes. the i 2 c slave controller con- forms to the nxp i 2 c-bus specification . 11.2 i 2 c overview i 2 c is a bi-directional 2-wire data protocol . a device that sends data is defined as a transmitter and a device that receives data is defined as a receiver. the bus is controlled by a ma ster which generates the scl clock, controls bus access and generates the start and stop condit ions. either a master or slave may operate as a transmitter or receiver as determined by the master. both the clock ( i2cscl ) and data ( i2csda ) signals have digital input filters that reject pulses that are less than 100 ns. the data pin is driven low when either interface s ends a low, emulating the wired-and function of the i 2 c bus. since the slave interface never drives the clo ck pin, the wired-and is not necessary. the following bus states exist: ? idle: both i2csda and i2cscl are high when the bus is idle. ? start & stop conditions: a start condition is defined as a high to low transition on the i2csda line while i2cscl is high. a stop condition is defined as a low to high transition on the i2csda line while i2cscl is high. the bus is considered to be busy following a start condition and is co nsidered free 4.7 s/1.3 s (for 100 khz and 400 khz operation, respectively) following a stop condition. the bus stays busy following a repeated start condition (instead of a stop condition). starts and rep eated starts are otherwise functionally equivalent. ? data valid: data is valid, following the start condition, when i2csda is stable while i2cscl is high. data can only be changed while the clock is low. there is one valid bit pe r clock pulse. every byte must be 8 bits long and is transmitted msb first. ? acknowledge: each byte of data is followed by an acknowledge bit. the master generates a ninth clock pulse for the acknowledge bit. the transmitter releases i2csda (high). the receiver drives i2csda low so that it remains valid during the high period of the clock, taking into account the setup and hold times. the receiver may be the master or the slave depending on the direction of the dat a. typically the receiver acknowledges each byte. if the master is the receiver, it does not generate an acknowledge on the last byte of a transf er. this informs the slave to not drive the next byte of data so that the master may generate a stop or repeated start condition. figure 11-1 displays the various bus states of a typical i 2 c cycle. figure 11-1: i 2 c cycle i2csda i2cscl s start condition p stop condition data valid or ack data valid or ack data stable data can change data stable data can change sr re-start condition data can change data can change
-page 320 ? 2015 microchip technology inc. 11.3 i 2 c slave operation when in i 2 c managed mode, the i 2 c slave interface is used for cpu manageme nt of the device. all system csrs are accessible to the cpu in these modes. i 2 c mode is selected when the serial_mngt_mode_strap configuration strap is set to 1b. the i 2 c slave controller implements the low level i 2 c slave serial interface (start and stop condition detection, data bit transmission and reception and acknowledge generat ion and reception), handles the slave command protocol and performs system register reads and writes. the i 2 c slave controller conforms to the nxp i 2 c-bus specification . the i 2 c slave serial interface consists of a data wire ( i2csda ) and a serial clock ( i2cscl ). the serial clock is driven by the master, while the data wire is bi-directional. both signals are open-drain and require external pull-up resistors. the i 2 c slave serial interface supports the standard-mode spee d of up to 100 khz and the fast-mode speed of 400 khz. refer to the nxp i 2 c-bus specification for detailed i 2 c timing information with the following modifications: ? tvd;dat maximum (sda data output valid from scl fal ling) is 3000ns and 700ns for standard and fast modes respectively. ? tvd;ack maximum (sda acknowledge output valid from sc l falling) is 3000ns and 700ns for standard and fast modes respectively. ? tsp maximum (input spike suppression on scl and sda) is 100ns. ? thd;dat minimum (sda data and acknowl edge output hold from scl falling) is 100ns. 11.3.1 i 2 c slave command format the i 2 c slave serial interface supports single register and mult iple register read and write commands. a read or write command is started by the master first sending a start condition , followed by a control byte. the control byte consists of a 7-bit slave address and a 1-bit read/write indication (r/~w). the default slave address used by the device is 0001010b, written as sa6 (first bit on the wire) th rough sa0 (last bit on the wire). alternatively, the i 2 c slave address may be configured to another address by setting the i2c_addr_override_strap and configuring the i2c_ad- dress_strap[6:0] with the desired value. assuming the slave address in the control byte matches this address, the con- trol byte is acknowledged by the devi ce. otherwise, the entire sequ ence is ignored until the next start condition. the i 2 c command format can be seen in figure 11-2 . if the read/write indication (r/~w) in t he control byte is a 0 (indicating a potentia l write), the next byte sent by the master is the register address. after the address byte is acknowle dged by the device, the master may either send data bytes to be written or it may send another start condition (to star t the reading of data) or a stop condition. the latter two will terminate the current write (wit hout writing any data), but will have the affect of setting the internal register address which will be used for subsequent reads. if the read/write indication in the control byte is a 1 (indic ating a read), the device will start sending data following the control byte acknowledgment. note: all registers are accessed as dwo rds. appending two 0 bits to the address field will form the register address. addresses and data are transferred msb firs t. data is transferred msb first (little endian). figure 11-2: i 2 c slave addressing s s a 2 s a 1 s a 0 0 r/~w control byte a 7 a 6 a 5 a 4 a 3 a 2 a c k a c k address byte s a 6 s a 5 s a 4 s a 3 * start or stop or data [31] a 9 a 8
? 2015 microchip technology inc. -page 321 11.3.2 device initialization until the device has been initialized to the point w here the various configuration inputs are valid, the i 2 c slave interface will not respond to or be affected by any external pin activity. 11.3.2.1 i 2 c slave read polling for initialization complete before device initialization, the i 2 c slave interface will not return valid data. to determine when the i 2 c slave interface is functional, the byte order test r egister (byte_test) should be polled. once the correct pattern is read, the inter- face can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) can be polled to determine when the device is fully configured. note: the host should only use single re gister reads (one data cycle per i 2 c start/stop) while polling the byte_test register. 11.3.3 access during and following power management during any power management mode other than d0, reads and writes are ignored and the i 2 c slave interface will not respond to or be affected by any external pin activity. to determine when the i 2 c slave interface is functional, the byte order test register (byte_test) should be polled. once the correct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) can be polled to determine when the device is fully configured. note: the host should only use single re gister reads (one data cycle per i 2 c start/stop) while polling the byte_test register. 11.3.4 i 2 c slave read sequence following the device addressing, as detailed in section 11.3.1 , a register is read from the device when the master sends a start condition and control byte with the r/~w bit set. assuming the slave address in the control byte matches the device address, the control byte is acknowledged by the devic e. otherwise, the entire seque nce is ignored until the next start condition. following the acknowledge, the device sends 4 bytes of data. the first 3 bytes are acknowledged by the master and on the fourth, the master sends a no-acknowl edge followed by the stop condition. the no-acknowledge informs the device not to send the next 4 bytes (as it would in the case of a multip le read). the internal register address is unchanged following the single read. multiple reads are performed when the master sends an ackn owledge on the fourth byte. the internal address is incre- mented and the next register is shifted out. once the internal address reaches its maximum, it rolls over to 0. the mul- tiple read is concluded when the master sends a no-ack nowledge followed by a stop condition. the no-acknowledge informs the device not to send the next 4 bytes. the inter nal register address is increm ented for each read including the final. for both single and multiple reads, in the case that the ma ster sends a no-acknowledge on any of the first three bytes of the register, the device will stop s ending subsequent bytes. if t he master sends an unexpected start or stop condition, the device will stop sending immediately and will respond to the next sequence as needed. i 2 c reads from unused register addresses return all zeros.
-page 322 ? 2015 microchip technology inc. figure 11-3 illustrates a typical single and multiple register read. special csr handling live bits since data is read serially, register values are latched (r egistered) at the beginning of each 32-bit read to prevent the host from reading an intermediate value. the latchi ng occurs multiple times in a multiple read sequence. change on read registers and fifos any register that is affected by a read operation (e.g. a cl ear on read bit) is cleared once the host has acknowledge the 3rd byte of output (an acknowled ge of the 3rd byte indicates that the host wil l read the fourth byte). since the full 32-bits of the register were saved at the beginning of the read, the 4th byte of data that is output is the original value and not the updated value. in the event that the host sends a no-a cknowledge on one of the first three bytes or a start or stop condition occurs unexpectedly before the acknowledge of th e 3rd byte, the read is considered in valid and the register is not affected. multiple registers may be clear ed in a multiple read cycle, each one being cleared as it is read. change on read live register bits as described above, the current value from a register with live bits (as is the case of any register) is saved before the data is shifted out. although a h/w event t hat occurs following the data capture woul d still update the live bit(s), the live bit(s) will be affected (cleared, etc.) once the output shif t has started and the h/w event would be lost. in order to prevent this, the individual csrs defer the h/w ev ent update until after the read indication. 11.3.5 i 2 c slave write sequence following the device addressing, as detailed in section 11.3.1 , a register is written to the device when the master con- tinues to send data bytes. each byte is acknowledged by the device. following the fourth by te of the sequence, the mas- ter may either send another start condition or halt the seq uence with a stop condition. the internal register address is unchanged following a single write. multiple writes are performed when the master sends additional bytes following the fourth acknowledge. the internal address is automatically incremented and the next register is written. once the internal address reaches its maximum value, it rolls over to 0. the multiple write is concluded when the master sends another start or stop condition. the inter- nal register address is incremented for each write including th e final. this is not relevant for subsequent writes, since a new register address would be included on a new write cycle. howe ver, this does affect the internal register address if it were to be used for reads without first resetting the register address. for both single and multiple writes, if the master sends an unexpec ted start or stop condition, the device will stop imme- diately and will respond to the next sequence as needed. the data write to the register occurs after the 32 bits are in put. in the event that 32 bits are not written (master sends a start or a stop condition occurs unexpect edly), the write is considered invalid and the register is not affected. multiple registers may be written in a multiple writ e cycle, each one being wr itten after 32 bits. i 2 c writes must no t be performed to unused register addresses. figure 11-3: i 2 c slave reads multiple register reads s control byte a c k single register read 1 d 5 d 4 d 3 d 2 d 1 d 0 a c k p s a 2 s a 1 s a 0 s a 6 s a 5 s a 4 s a 3 a c k d 3 1 d 3 0 d 2 9 d 2 8 s 2 7 d 2 6 d 2 5 d 2 4 d 2 3 d 2 2 s a c k 1 s a 2 s a 1 s a 0 s a 6 s a 5 s a 4 s a 3 a c k d 3 1 d 3 0 d 2 5 d 2 4 data byte... d 2 1 d 2 0 data byte data 1 byte d 4 d 3 d 2 d 1 d 0 a c k p d 4 d 3 d 2 d 1 d 0 a c k d 3 1 d 3 0 d 2 9 d 2 8 d 2 7 d 2 6 s s a 2 s a 1 s a 0 0 a 7 a 6 a 5 a 4 a 3 a 2 a c k a c k address byte s a 6 s a 5 s a 4 s a 3 a 9 a 8 s s a 2 s a 1 s a 0 0 control byte a 7 a 6 a 5 a 4 a 3 a 2 a c k a c k address byte s a 6 s a 5 s a 4 s a 3 a 9 a 8 r/~w r/~w .. . .. ... ... . control byte control byte ...data byte ...data m byte data m+1 byte... ...data n byte
? 2015 microchip technology inc. -page 323 figure 11-4 illustrates a typical single and multiple register write. figure 11-4: i 2 c slave writes multiple register writes single register write a c k d 5 d 4 d 3 d 2 d 1 d 0 p d 3 1 d 3 0 d 2 9 d 2 8 s 2 7 d 2 6 d 2 5 d 2 4 d 2 3 d 2 2 d 2 1 d 2 0 data byte a c k a c k a c k d 3 1 d 3 0 d 2 5 d 2 4 d 5 d 4 d 3 d 2 d 1 d 0 p d 5 d 4 d 3 d 2 d 1 d 0 a c k d 3 1 d 3 0 d 2 9 d 2 8 d 2 7 d 2 6 d 2 5 a c k a c k s s a 2 s a 1 s a 0 0 a 7 a 6 a 5 a 4 a 3 a 2 a c k address byte s a 6 s a 5 s a 4 s a 3 a 9 a 8 s s a 2 s a 1 s a 0 0 a 7 a 6 a 5 a 4 a 3 a 2 a c k address byte s a 6 s a 5 s a 4 s a 3 a 9 a 8 control byte control byte data 1 byte .. ... . ...data m byte data m+1 byte... .. . ...data n byte .. . ...data byte data byte...
-page 324 ? 2015 microchip technology inc. 12.0 i 2 c master eeprom controller 12.1 functional overview this chapter details the eeprom i 2 c master and eeprom loader provided by the device. the i 2 c eeprom controller is an i 2 c master module which interfaces an optional extern al eeprom with the system register bus and the eeprom loader. multiple sizes of exte rnal eeproms are supported. co nfiguration of the eeprom si ze is accomplished via the eeprom_size_strap configuration strap. various commands are supported for eeprom access, allowing for the storage and retrieval of static data. the i 2 c interface conforms to the nxp i 2 c-bus specification . the eeprom loader provides th e automatic loading of conf iguration sett ings from the eeprom into the device at reset. the eeprom loader module interfaces to the eepr om controller, ethernet ph ys and the system csrs. 12.2 i 2 c overview i 2 c is a bi-directional 2-wire data protocol. a device that send s data is defined as a transmitte r and a device that receives data is defined as a receiver. the bus is c ontrolled by a master which generates the eescl clock, controls bus access and generates the start and stop conditions. either a master or slave may operate as a transmitter or receiver as deter- mined by the master. both the clock ( eescl ) and data ( eesda ) signals have digital input filters that reject pulses that are less than 100 ns. the data pin is driven low when either interface s ends a low, emulating the wired-and function of the i 2 c bus. the following bus states exist: ? idle: both eesda and eescl are high when the bus is idle. ? start & stop conditions: a start condition is defined as a high to low transition on the eesda line while eescl is high. a stop condition is defined as a low to high transition on the eesda line while eescl is high. the bus is considered to be busy following a start condition and is considered free 4.7 s/1.3 s (for 100 khz and 400 khz operation, respectively) following a stop condition. the bus stays busy following a repeated start condition (instead of a stop condition). starts and rep eated starts are otherwise functionally equivalent. ? data valid: data is valid, following the start condition, when eesda is stable while eescl is high. data can only be changed while the clock is low. there is one valid bit per clock pulse. every byte must be 8 bits long and is transmitted msb first. ? acknowledge: each byte of data is followed by an acknowled ge bit. the master generates a ninth clock pulse for the acknowledge bit. the transmitter releases eesda (high). the receiver drives eesda low so that it remains valid during the high period of the clock, taking into account the setup and hold times. the receiver may be the master or the slave depending on the direction of the dat a. typically the receiver acknowledges each byte. if the master is the receiver, it does not generate an acknowledge on the last byte of a transf er. this informs the slave to not drive the next byte of data so that the master ma y generate a stop or repeated start condition. figure 12-1 displays the various bus states of a typical i 2 c cycle. figure 12-1: i 2 c cycle eesda eescl s start condition p stop condition data valid or ack data valid or ack data stable data can change data stable data can change sr re-start condition data can change data can change
? 2015 microchip technology inc. -page 325 12.3 i 2 c master eeprom controller the i 2 c eeprom controller supports i 2 c compatible eeproms. note: when the eeprom loader is running, it has exclusive use of the i 2 c eeprom controller. refer to section 12.4, "eeprom loader" for more information. the i 2 c master implements a low level serial interface (start and stop condition generation, data bit transmission and reception, acknowledge generation an d reception) for connection to i 2 c eeproms and consists of a data wire ( eesda ) and a serial clock ( eescl ). the serial clock is driven by the master, while the data wire is bi-directional. both signals are open-drain and require external pull-up resistors. the i 2 c master interface runs at the standard-mode rate of 100 khz. i 2 c master interface timing information is detailed in figure 12-2 and table 12-1 . figure 12-2: i 2 c master timing table 12-1: i 2 c master timing values symbol description min typ max units f scl eescl clock frequency 100 khz t high eescl high time 4.0 ? s t low eescl low time 4.7 ? s t r rise time of eesda and eescl 1000 ns t f fall time of eesda and eescl 300 ns t su;sta setup time (provided to slave) of eescl high before eesda output falling for repeated start con- dition 5.2 note 1 ? s t hd;sta hold time (provided to slave) of eescl after eesda output falling for start or repeated start con- dition 4.5 note 1 ? s t su;dat;in setup time (from slave) eesda input before eescl rising 200 note 2 ns t hd;dat;in hold time (from slave) of eesda input after eescl falling 0ns t su;dat;out setup time (provided to slave) eesda output before eescl rising 1250 note 3 ns eesda (out) eescl s p sr s t f t r t hd;sta t hd;dat;in t su;dat;in t su;sta t su;sto t buf t sp eesda (in) t high t low t hd;dat;out t sp t sp t su;dat;out
-page 326 ? 2015 microchip technology inc. note 1: these values provide 500 ns of margin compared to the i 2 c specification. note 2: this value provides 50 ns of margin compared to the i 2 c specification. note 3: these values provide 1000 ns of margin compared to the i 2 c specification. based on the eeprom_size_strap configuration strap, various sized i 2 c eeproms are supported. the varying size ranges are supported by additional bits in the eeprom controller address (epc_address) field of the eeprom command register (e2p_cmd) . within each size range, the largest eeprom uses all the address bits, while the smaller eeproms treat the upper address bits as don?t care s. the eeprom controller driv es all the address bits as requested regardless of the actual size of the eeprom. the supported size ranges for i 2 c operation are shown in table 12-2 . note 4: bits in the control byte are used as the upper address bits. 12.3.1 i 2 c eeprom device addressing the i 2 c eeprom is addressed for a read or write operation by first sending a cont rol byte followed by the address byte or bytes. the control byte is preceded by a start conditi on. the control byte and address byte(s) are each acknowledged by the eeprom slave. if the eeprom slave fails to send an acknowledge, then the sequen ce is aborted (a start con- dition and a stop condition are sent) and the eeprom controller ti meout (epc_timeout) bit of the eeprom com- mand register (e2p_cmd) is set. the control byte consists of a 4 bit cont rol code, 3 bits of chip/block select an d one direction bit. the control code is 1010b. for single byte addressing eeproms, the chip/block se lect bits are used for address bits 10, 9 and 8. for double byte addressing eeproms, the ch ip/block select bits are set lo w. the direction bit is set lo w to indicate the address is being written. t hd;dat;out hold time (provided to slave) of eesda output after eescl falling 1000 note 3 ns t su;sto setup time (provided to slave) of eescl high before eesda output rising for stop condition 4.5 note 1 ? s t buf bus free time 4.7 ? s t sp input spike suppression on eescl and eesda 100 ns table 12-2: i 2 c eeprom size ranges eeprom_size_strap # of address bytes eeprom size eeprom types 01 ( note 4 ) 128 x 8 through 2048 x 8 24xx01, 24xx02, 24xx04, 24xx08, 24xx16 1 2 4096 x 8 through 65536 x 8 24xx32, 24xx64, 24xx128, 24xx256, 24xx512 table 12-1: i 2 c master timing values (continued) symbol description min typ max units
? 2015 microchip technology inc. -page 327 figure 12-3 illustrates a typical i 2 c eeprom addressing bit order for single and double byte addressing. 12.3.2 i 2 c eeprom byte read following the device addressing, a data byte may be read fr om the eeprom by outputting a start condition and control byte with a control code of 1010b, chip/block select bits as described in section 12.3.1 and the r/~w bit high. the eeprom will respond with an acknowledge, followed by 8 bits of data. if the eeprom slave fails to send an acknowl- edge, then the sequence is aborted (a star t condition and a stop condition are sent) and the eeprom controller tim- eout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. the i 2 c master then sends a no- acknowledge, followed by a stop condition. figure 12-4 illustrates a typical i 2 c eeprom byte read for single and double byte addressing. for a register level description of a read operation, refer to section 12.3.7, "i2c master eeprom controller operation," on page 330 . 12.3.3 i 2 c eeprom sequential byte reads following the device addressing, data bytes may be read seque ntially from the eeprom by outputting a start condition and control byte with a control code of 1010 b, chip/block select bits as described in section 12.3.1 and the r/~w bit high. the eeprom will respond with an acknowledge, followed by 8 bits of data. if the eeprom slave fails to send an acknowledge, then the sequence is aborted (a star t condition and a stop condition are sent) and the eeprom controller timeout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. the i 2 c master then sends an acknowledge and the eeprom responds with the next 8 bits of da ta. this continues until the last desired byte is read, at which point the i 2 c master sends a no-acknowledge (instead of t he acknowledge), followed by a stop condition. figure 12-3: i 2 c eeprom addressing figure 12-4: i 2 c eeprom byte read s 1 0 1 0 a 1 0 a 9 a 8 0 r/~w control byte a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k a c k chip / block select bits s 1 0 1 0 0 control byte a c k a c k single byte addressing double byte addressing a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k address byte address low byte address high byte a 9 a 8 0 0 0 a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 r/~w chip / block select bits s 1 0 1 0 a 1 0 a 9 a 8 control byte a c k s 1 0 1 0 control byte a c k single byte addressing read double byte addressing read 0 0 0 1 data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k p 1 data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k p a c k a c k r/~w chip / block select bits r/~w chip / block select bits
-page 328 ? 2015 microchip technology inc. figure 12-5 illustrates a typical i 2 c eeprom sequential byte reads for single and double byte addressing. sequential reads are used by the eeprom loader. refer to section 12.4, "eeprom loader" for additional information. for a register level description of a read operation, refer to section 12.3.7, "i2c master eeprom controller operation," on page 330 . 12.3.4 i 2 c eeprom byte writes following the device addressing, a data byte may be written to the eeprom by outputting the data after receiving the acknowledge from the eeprom. the data byte is acknowledged by the eeprom slave and the i 2 c master finishes the write cycle with a stop condition. if the eeprom slave fa ils to send an acknowledge, then the sequence is aborted (a start condition and a stop condition are sent) and the eeprom controller timeout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. following the data byte write cycle, the i 2 c master will poll the eeprom to determine when the byte write is finished. after meeting the minimum bus free time, a start condition is s ent followed by a control byte with a control code of 1010b, chip/block select bits low (since they are don?t cares) and the r/~w bit low. if the eeprom is finished with the byte write, it will respond with an ackn owledge. otherwise, it will res pond with a no-acknowledge and the i 2 c master will issue a stop and repeat the poll. if the acknowledge does not occur within 30 ms, a timeout occurs (a start condition and a stop condition are sent) and the eeprom controller ti meout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. the check for timeout is only performed fo llowing each no-acknowledge, since it may be possible that the eeprom write fi nished before the timeout but the 30 ms expired before the po ll was performed (due to the bus being used by another master). once the i 2 c master receives the acknowledge, it concludes by sending a start condi tion, followed by a stop condition, which will place the eeprom into standby. figure 12-6 illustrates a typical i 2 c eeprom byte write. figure 12-5: i 2 c eeprom sequential byte reads figure 12-6: i 2 c eeprom byte write s 1 0 1 0 a 1 0 a 9 a 8 control byte a c k s 1 0 1 0 control byte a c k single byte addressing sequential reads 0 0 0 1 data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k p 1 data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k a c k a c k data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k p a c k data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 double byte addressing sequential reads ... r/~w chip / block select bits r/~w chip / block select bits ... a c k data byte p a c k s 1 0 1 0 0 r / ~ w control byte chip / block select bits 0 0 0 s 1 0 1 0 0 r / ~ w control byte chip / block select bits 0 0 0 s 1 0 1 0 0 r / ~ w control byte chip / block select bits 0 0 0 ... d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k a c k a c k s p poll cycle poll cycle poll cycle data cycle conclude p p bus free time bus free time ... ... bus free time
? 2015 microchip technology inc. -page 329 for a register level description of a write operation, refer to section 12.3.7, "i2c master eeprom controller operation," on page 330 . 12.3.5 wait state generation the serial clock is also used as an input as it can be held low by the slave devi ce in order to wait-state the data cycle. once the slave has data available or is ready to receive, it will release the clock. assuming the masters clock low time is also expired, the clock will rise and the cycle will continue. if the slave device holds the clock low for more than 30 ms, the current command sequence is aborted (a start condition and a stop condition are not sent since the clock is being held low, instead the clock and data lines are just released) and the eeprom controller timeout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. 12.3.6 i 2 c bus arbitration and clock synchronization since the i 2 c master and the i 2 c slave serial interfaces share common pins, there are at least two master i 2 c devices on the bus (the device and the host). there exists the potential that both masters try to a ccess the bus at the same time. the i 2 c specification handles this situation with three mechanisms: bus busy, clock synchronization and bus arbitration. note: the timing parameters referred to in the following subsec tions refer to the detailed timing information pre- sented in the nxp i 2 c-bus specification . 12.3.6.1 bus busy a master may start a transfer only if the bus is not busy. the bus is consid ered to be busy after the start condition and is considered to be free again t buf time after the stop condition. the stan dard mode value of 4.7 s is used for t buf since the eeprom master runs at the standard mode rate. fo llowing reset, it is unknown if the bus is actually busy, since the start condition may have been missed. therefore, following reset, the bus is initially considered busy and is considered free t buf time after the stop condition or if clock and data are seen high for 4 ms. 12.3.6.2 clock synchronization clock synchronization is used, since both masters may be g enerating different clock frequencies. when the clock is driven low by one master, each other active master will rest art its low timer and also drive the clock low. each master will drive the clock low for its minimum low time and then rele ase it. the clock line will not go high until all masters have released it. the slowest master therefor e determines the actual low time. devices with shorter low timers will wait. once the clock goes high, each master will start its high timer. the first master to reach its high time will once again drive the clock low. the fastest master therefore determines the actu al high time. the process then repeats. clock synchroniza- tion is similar to the cycle stretching that can be done by a slave device, with the exceptio n that a slave device can only extend the low time of the clock. it c an not cause the falling edge of the clock. 12.3.6.3 arbitration arbitration involves testing the input data vs. the output data, when the clock goes high, to see if they match. since the data line is wired-and?ed, a master transmi tting a high value will see a mismatch if another master is transmitting a low value. the comparison is not done when receiving bits from t he slave. arbitration starts wit h the control byte and, if both masters are accessing the same slave, can continue into address and data bits (for writes) or acknowledge bits (for reads). if desired, a master that loses arbitration can continue to generate clo ck pulses until the end of the loosing byte (note that the ack on a read is consi dered the end of the byte) but the losing master may no longer drive any data bits. it is not permitted for another master to access the eeprom while the device is using it during startup or due to an eeprom command. the other mast er should wait sufficient time or poll the device to determine when the eeprom is available. this restriction simplifies the arbitration and access process since arbitration will always be resolved when transmitting the 8 control bits during the device addressing or during the poll cycles. if arbitration is lost during the device addressing, the i 2 c master will return to the beginning of the device addressing sequence and wait for the bus to become free. if arbitration is lost during a poll cycle, the i 2 c master will return to the beginning of the poll cycle sequence and wait for the bus to become free. note that in this case the 30 ms timeout-counter should not be reset. if the 30 ms timeout should expire while waiting for the bus to become free, the sequence should not abort without first completing a final poll (with the exception of the busy / arbitration timeout described in section 12.3.6.4 ).
-page 330 ? 2015 microchip technology inc. 12.3.6.4 timeout due to busy or arbitration it is possible for another master to monopolize the bus (due to a continual bu s busy or more successful arbitration). if successful arbitration is not achieved within 1.92 s from the star t of the read or write request or from the start of the poll cycle, the command sequence or poll cycle is aborted and the eeprom controller timeout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. note that this is a total timeout value and not the timeout for any one portion of the sequence. 12.3.7 i 2 c master eeprom co ntroller operation i 2 c master eeprom operations are performed using the eeprom command register (e2p_cmd) and eeprom data register (e2p_data) . the following operations are supported: ? read (read location) ? write (write location) ? reload (eeprom lo ader reload - see section 12.4, "eeprom loader" ) note: the eeprom loader uses the read command only. the supported commands are detailed in section 12.5.1, "eeprom command register (e2p_cmd)," on page 337 . details specific to each operational mode are explained in section 12.2, "i2c overview," on page 324 and section 12.4, "eeprom loader" , respectively. when issuing a write command, the desired data must first be written into the eeprom data register (e2p_data) . the write command may then be issued by setting the eeprom controller command (epc_command) field of the eeprom command register (e2p_cmd) to the desired command value. if the operation is a write, the eeprom controller address (epc_address) field in the eeprom command register (e2p_cmd) must also be set to the desired location. the command is executed when the eeprom controller busy (epc_busy) bit of the eeprom com- mand register (e2p_cmd) is set. the completion of the operation is indicated when the eeprom controller busy (epc_busy) bit is cleared. when issuing a read command, the eeprom controller command (epc_command) and eeprom controller address (epc_address) fields of the eeprom command register (e2p_cmd) must be configured with the desired command value and the read address, respectively. the read command is executed by setting the eeprom control- ler busy (epc_busy) bit of the eeprom command register (e2p_cmd) . the completion of the operation is indicated when the eeprom controller busy (epc_busy) bit is cleared, at which time the data from the eeprom may be read from the eeprom data register (e2p_data) . the reload operation is performed by writing the reload command into the eeprom controller command (epc_command) field of the eeprom command register (e2p_cmd) . the command is executed by setting the eeprom controller busy (epc_busy) bit of the eeprom command register (e2p_cmd) . in all cases, the software must wait for the eeprom controller busy (epc_busy) bit to clear before modifying the eeprom command register (e2p_cmd) . if an operation is attempted and the eeprom device does not respond within 30 ms, the device will timeout and the eeprom controller timeout (epc_timeout) bit of the eeprom command register (e2p_cmd) will be set.
? 2015 microchip technology inc. -page 331 figure 12-7 illustrates the process re quired to perform an eeprom read or write operation. figure 12-7: eeprom access flow diagram eeprom write idle write e2p_data register write e2p_cmd register read e2p_cmd register epc_busy = 0 eeprom read idle write e2p_cmd register read e2p_cmd register read e2p_data register epc_busy = 0
-page 332 ? 2015 microchip technology inc. 12.4 eeprom loader the eeprom loader inte rfaces to the i 2 c eeprom controller, the phys and to the system csrs (via the register access mux). all system csrs are ac cessible to the eeprom loader. the eeprom loader runs upon a pin reset ( rst# ), power-on reset (por ), digital reset ( digital reset (digital_rst) bit in the reset control register (reset_ctl) ) or upon the issuance of a reload command via the eeprom com- mand register (e2p_cmd) . refer to section 6.2, "resets," on page 38 for additional information on resets. the eeprom contents must be loaded in a specific forma t for use with the eeprom loa der. an overview of the eeprom content format is shown in ta b l e 1 2 - 3 . each section of eeprom contents is discussed in detai l in the follow- ing sections. 12.4.1 eeprom loader operation upon a pin reset (( rst# ), power-on reset (por), digital reset ( digital reset (digital_rst) bit in the reset control register (reset_ctl) ) or upon the issuance of a reload command via the eeprom command register (e2p_cmd) , the eeprom controller busy (epc_busy) bit in the eeprom command register (e2p_cmd) will be set. while the eeprom loader is ac tive, the device ready (ready) bit of the hardware configuration register (hw_cfg) is cleared and no writes to the device should be attempted. the operational flow of the eeprom loader can be seen in figure 12-8 . table 12-3: eeprom cont ents format overview eeprom address description value 0 eeprom valid flag a5h 1 mac address low word [7:0] 1 st byte on the network 2 mac address low word [15:8] 2 nd byte on the network 3 mac address low word [23:16] 3 rd byte on the network 4 mac address low word [31:24] 4 th byte on the network 5 mac address high word [7:0] 5 th byte on the network 6 mac address high word [15:8] 6 th byte on the network 7 configuration strap values valid flag a5h 8 - 16 configuration strap values see table 12-4 17 burst sequence valid flag a5h 18 number of bursts see section 12.4.5, "register data" 19 and above burst data see section 12.4.5, "register data"
? 2015 microchip technology inc. -page 333 figure 12-8: eeprom loader flow diagram byte 0 = a5h n digital_rst, rst# , por, reload y epc_busy = 1 read byte 0 read bytes 1-6 write bytes 1-6 into switch mac address registers read byte 7-16 byte 7 = a5h y write bytes 8-16 into configuration strap registers load registers with current straps and restart phy auto-negotiation read byte 17 byte 17 = a5h do register data loop y load registers with current straps and restart phy auto-negotiation n epc_busy = 0
-page 334 ? 2015 microchip technology inc. 12.4.2 eeprom valid flag following the release of rst# , por, digital_rst or a reload comm and, the eeprom loader starts by reading the first byte of data from the eeprom. if the value of a5h is not read from the first byte, the eeprom loader will load the current configuration strap values into the registers, restart phy auto-negotiation and then terminate, clearing the eeprom controller busy (epc_busy) bit in the eeprom command register (e2p_cmd) . otherwise, the eeprom loader will continue reading sequential bytes from the eeprom. 12.4.3 mac address the next six bytes in the eeprom, after the eeprom valid flag, are written into the switch fabric mac address high register (switch_mac_addrh) and switch fabric mac address lo w register (switch_mac_addrl) . the eeprom bytes are written into the mac addre ss registers in the order specified in ta b l e 1 2 - 3 . 12.4.4 soft-straps the 7 th byte of data to be read from the eeprom is the configur ation strap values valid flag. if this byte has a value of a5h, the next 9 bytes of data (8-16) are written into t he configuration strap registers per the assignments detailed in table 12-4 . if the flag byte is not a5h, these next 9 bytes are skipped (they are still read to maintain the data burst, but are dis- carded). however, the current configurat ion strap values are still loaded into the registers and the phy auto-negotiation is still restarted. refer to section 7.0, "configuration straps," on page 54 for more information on configuration straps. note: bit locations in table 12-4 that do not define a configurat ion strap must be written as 0. 12.4.5 register data optionally following the configuration strap values, the eeprom data may be formatted to allow access to the device?s parallel, directly writable registers. access to indirectly accessible registers is achiev able with an appropriate sequence of writes (at the cost of eeprom space). table 12-4: eeprom configurati on bits byte/bit765 4 321 0 byte 8 bp_en_ strap_1 fd_fc_ strap_1 manual_ fc_strap_1 manual_m- dix_strap_1 auto_mdix- _strap_1 speed_ strap_1 duplex_ strap_1 autoneg_ strap_1 byte 9 bp_en_ strap_2 fd_fc_ strap_2 manual_ fc_strap_2 manual_m- dix_strap_2 auto_mdix- _strap_2 speed_ strap_2 duplex_ strap_2 autoneg_ strap_2 byte 10 bp_en_ strap_0 fd_fc_ strap_0 manual_f- c_strap_0 speed_ strap_0 speed_pol_ strap_0 duplex_ strap_0 duplex- _pol_strap_ 0 byte 11 1588_ enable_ strap led_fun_ strap[2] led_fun_ strap[1] led_fun_ strap[0] eee_ enable_ strap_2 eee_ enable_ strap_1 byte 12 led_en_ strap[5] led_en_ strap[4] led_en_ strap[3] led_en_ strap[2] led_en_ strap[1] led_en_ strap[0] byte 13 i2c_addr_ override_ strap i2c_ address_ strap[6] i2c_ address_ strap[5] i2c_ address_ strap[4] i2c_ address_ strap[3] i2c_ address_ strap[2] i2c_ address_ strap[1] i2c_ address_ strap[0] byte 14 byte 15 byte 16
? 2015 microchip technology inc. -page 335 this data is first preceded with a burst sequence valid flag ( eeprom byte 17). if this byte has a value of a5h, the data that follows is recognized as a sequence of bursts. otherwis e, the eeprom loader is finished, will go into a wait state and clear the eeprom controller busy (epc_busy) bit in the eeprom command register (e2p_cmd) . this can optionally generate an interrupt. the data at eeprom byte 18 and above should be formatted in a sequence of bursts. the first byte is the total number of bursts. following this is a series of bursts, each consisti ng of a starting address, count and the count x 4 bytes of data. this results in the following formula for formatting register data: 8 bits number_of_bursts repeat (number_of_bursts) 16 bits {starting_addre ss[9:2] / count[7:0]} repeat (count) 8 bits data[31:24], 8 bits data[23:16], 8 bits data[15:8], 8 bits data[7:0] note: the starting address is a dword address. appen ding two 0 bits will form the register address. as an example, the following is a 3 burst sequence, with 1, 2 and 3 dwords star ting at register addresses 40h, 80h and c0h respectively: a5h, (burst sequence valid flag) 3h, (number_of_bursts) 16{10h, 1h}, (starting_address1 divided by 4 / count1) 11h, 12h, 13h, 14h, (4 x count1 of data) 16{20h, 2h}, (starting_address2 divided by 4 / count2) 21h, 22h, 23h, 24h, 25h, 26h, 27h, 28h, (4 x count2 of data) 16{30h, 3h}, (starting_address3 divided by 4 / count3) 31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h, 3ah, 3bh, 3ch (4 x count3 of data) in order to avoid over writing the switch csr interface or phy manage ment interface, the eepr om loader waits until the following bits are cleared befor e performing any register write: ? csr busy (csr_busy) bit of the switch fabric csr interface co mmand register (switch_csr_cmd) ? mii busy (miibzy) bit of the phy management interface access register (pmi_access) the eeprom loader checks that the eeprom address space is not exceeded. if so, it will stop and set the eeprom loader address overflow (loader_overflow) bit in the eeprom command register (e2p_cmd) . the address limit is based on the eeprom_size_strap which specifies a range of sizes. the ad dress limit is set to the largest value of the specified range. 12.4.6 eeprom loader finished wait-state once finished with the last burst, the eeprom loader will go into a wait-state and the eeprom controller busy (epc_busy) bit of the eeprom command register (e2p_cmd) will be cleared. this can optionally generate an inter- rupt.
-page 336 ? 2015 microchip technology inc. 12.5 i 2 c master eeprom controller registers this section details the directly addressable i 2 c master eeprom controller relat ed system csrs. these registers should only be used if an eeprom has been connect ed to the device. for an overview of the entire directly addressable register map, refer to section 5.0, "regist er map," on page 29 . table 12-5: i 2 c master eeprom controller registers address register name (symbol) 1b4h eeprom command register (e2p_cmd) 1b8h eeprom data register (e2p_data)
? 2015 microchip technology inc. -page 337 12.5.1 eeprom command re gister (e2p_cmd) this read/write r egister is used to control the read and write operatio ns of the serial eeprom. offset: 1b4h size: 32 bits bits description type default 31 eeprom controller busy (epc_busy) when a 1 is written into this bit, th e operation specified in the epc_com- mand field of this register is perfor med at the specified eeprom address. this bit will remain set until the selected operation is complete. in the case of a read, this indicates that the host can read valid data from the eeprom data register (e2p_data) . the e2p_cmd and e2p_data registers should not be modified until this bit is cleared. in the case where a write is attempted and an eeprom is not present, the epc_busy bit remains set until the eeprom controller timeout (epc_timeout) bit is set. at this time the epc_busy bit is cleared. note: epc_busy is set immediately following power-up, or pin reset, or digital_rst reset. after th e eeprom loader has finished loading, the epc_busy bit is cleared. refer to chapter section 12.4, "eeprom loader," on page 332 for more information. r/w sc 0b
-page 338 ? 2015 microchip technology inc. 30:28 eeprom controller co mmand (epc_command) this field is used to issue commands to the eeprom controller. the eeprom controller will execute a command when the epc_busy bit is set. a new command must not be issued until the previous command completes. the field is encoded as follows: note: only the read, write and reload commands are valid for i 2 c mode. if an unsupported command is attempted, the epc_busy bit will be cleared and epc_timeout will be set. the eeprom operations are defined as follows: read (read location) this command will cause a read of the eeprom location pointed to by the epc_ad- dress bit field. the result of the read is available in the eeprom data register (e2p_data) . write (write location) if erase/write operations are enabled in t he eeprom, this command will cause the contents of the eeprom data register (e2p_data) to be written to the eeprom location selected by the epc_address field. reload (eeprom loader reload) instructs the eeprom loader to reload the device from the eeprom. if a value of a5h is not found in the first address of the eeprom, the eeprom is assumed to be un-programmed and the reload operation will fail. the cfg_loaded bit indicates a successful load. following this command, the device will enter the not ready state. the device ready (ready) bit in the hardware configuration register (hw_cfg) should be polled to determine then the reload is complete. r/w 000b 27:19 reserved ro - 18 eeprom loader address over flow (loader_overflow) this bit indicates that the eeprom loade r tried to read past the end of the eeprom address space. this indica tes misconfigured eeprom data. this bit is cleared when the eeprom loader is restarted with a reload command, or a digital reset (digital_rst). ro 0b bits description type default [30] [29] [28] operation 000 read 0 0 1 reserved 0 1 0 reserved 011 write 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 111 reload
? 2015 microchip technology inc. -page 339 12.5.2 eeprom data register (e2p_data) this read/write register is used in conjunction with the eeprom command register (e2p_cmd) to perform read and write operations with the serial eeprom. 17 eeprom controller ti meout (epc_timeout) this bit is set when a timeout occurs, indicating the last operation was unsuc- cessful. if an eeprom write operation is performed and no response is received from the eeprom within 30 ms, the eeprom controller will time- out and return to its idle state. this bit is also set if the eeprom fail s to respond with t he appropriate acks, if the eeprom slave device holds the cl ock low for more than 30 ms, if the i2c bus is not acquired within 1.92 seconds , or if an unsupported epc_command is attempted. this bit is cleared when written high. r/wc 0b 16 configuration loaded (cfg_loaded) when set, this bit indicates that a valid eeprom was found and the eeprom loader completed normally. this bit is set upon a successful load. it is cleared on power-up, pin and digital_rst resets, or at the start of a reload. this bit is cleared when written high. r/wc 0b 15:0 eeprom controller address (epc_address) this field is used by the eeprom contro ller to address a specific memory location in the serial eeprom. this address mu st be byte aligned. r/w 0000h offset: 1b8h size: 32 bits bits description type default 31:8 reserved ro - 7:0 eeprom data (eeprom_data) this field contains the data read from or written to the eeprom. r/w 00h bits description type default
-page 340 ? 2015 microchip technology inc. 13.0 mii data interfaces this chapter describes the interconnect paths between the various modules including the 3-port switch fabric, the device pins and the physical phys. rmii timing is also detailed in section 13.4, "switch fabric timing requirements" . 13.1 port 0 data path the mii data interface is used to connec t the switch fabric port to the external pins, to select between phy and mac modes and to emulate an rmii phy or mac. 13.1.1 port 0 rmii mac mode when operating in rmii mac mode, the mii data interface mimics the operation of an rmii mac and is used when interfacing to an external phy that does not support the full mii interface. the rmii interface uses a subset of the mii pins. the p0_outd[1:0] , p0_outdv , p0_ind[1:0] , p0_indv and p0_refclk pins are the only mii pins used to com- municate with the external phy in this m ode. rmii mac mode operates at 10 or 100 mbps. 13.1.1.1 reference clock selection the 50 mhz rmii reference clock can be selected from either the p0_refclk pin input or the internal 50 mhz clock. the choice is based on the setting of the rmii clock direction bit of the virtual phy special control/status register (vphy_special_control_status) . a low selects p0_refclk and a high selects the internal 50 mhz clock. the high setting also enables p0_refclk as an output to be used as the reference clock to the phy. 13.1.1.2 clock drive strength when p0_refclk is configured as an output via the rmii clock direction bit of the virtual phy special control/status register (vphy_specia l_control_status) , its drive strength is based on the setting of the rmii clock strength bit of the virtual phy special control/status register (vphy_special_control_status) . a low selects 12 ma, a high selects 16 ma. 13.1.2 port 0 rmii phy mode when operating in rmii phy mode, the mii data interface mi mics the operation of an rmii phy and is used when inter- facing to an external mac that does not support the full mii in terface. the rmii interface us es a subset of the mii pins. the p0_outd[1:0] , p0_outdv , p0_ind[1:0] , p0_indv and p0_refclk pins are the only mii pins used to commu- nicate with the external mac in this mode. this mode provid es loopback test capabilities for the switch fabric and exter- nal mac, as well as collision testing for the switch fabric. note: the rmii standard does not support col lision testing for the external mac. 13.1.2.1 isolate when in rmii phy mode, if the isolate (vphy_iso) bit of the virtual phy basic control register (vphy_basic_ctrl) is set, rmii data path output pins are th ree-stated, the pull-ups and pull-downs ar e disabled and the rmii data path input pins are ignored (disabled into the non-active state and powered down). setting the isolate (vphy_iso) bit does not cause isolation of the mii management pi ns and does not affect rmii mac mode. 13.1.2.2 reference clock selection the 50 mhz rmii reference clock can be selected from either the p0_refclk pin input or the internal 50 mhz clock. the choice is based on the setting of the rmii clock direction bit of the virtual phy special control/status register (vphy_special_control_status) . a low selects p0_refclk and a high selects the internal 50 mhz clock. the high setting also enables p0_refclk as an output to be used as the reference clock to the mac. 13.1.2.3 clock drive strength when p0_refclk is configured as an output via the rmii clock direction bit of the virtual phy special control/status register (vphy_specia l_control_status) , its drive strength is based on the setting of the rmii clock strength bit of the virtual phy special control/status register (vphy_special_control_status) . a low selects 12 ma, a high selects 16 ma.
? 2015 microchip technology inc. -page 341 13.1.2.4 collision test external mac collision testing is not avail able when operating in the rmii phy mode. the collision test (vphy_col_test) bit of the virtual phy basic control register (vph y_basic_ctrl) has no effect on system oper- ation in rmii phy mode. switch fabric collision testing is available and is enabled when the switch collision test bit of the virtual phy special control/status register (vphy_special_control_status) is set. in this test mode , any transmissions from the switch fabric will result in the assertion of an internal collis ion signal to the switch fabric port 0. switch fabric collision test occurs regardless of the setting of the isolate (vphy_iso) bit. 13.1.2.5 loopback mode two forms of loopback testing are available: external mac loopback and switch fabric loopback. external mac loopback is enabled when the loopback (vphy_loopback) bit of the virtual phy basic control reg- ister (vphy_basic_ctrl) is set. transmissions from the external mac are not sent to the switch fabric. instead, they are looped back onto the receive path. transmi ssions from the switch fabric are ignored. switch fabric loopback is enabled when the switch loopback bit of the virtual phy special control/status register (vphy_special_control_status) is set. transmissions from the switch fa bric are not sent to the external mac. instead, they are looped back internally onto the receive path. transmissions from the external mac are ignored. an internal collision signal to the switch f abric is available and is asserted when the switch collision test bit is set. switch fabric loopback occurs regardless of the setting of the isolate (vphy_iso) bit. 13.2 port 1 data path the mii data interface is used to connect the switch fabric port to physical phy a. 13.2.1 port 1 internal phy mode when operating in internal phy mode, the switch fabric mac outputs are routed to internal phy a. similarly, the switch fabric mac inputs are sourced from internal phy a. the d uplex of the switch fabric mac is controlled by the phy. 13.3 port 2 data path the mii data interface is used to connect the switch fabric port to physical phy b. 13.3.1 port 2 internal phy mode when operating in internal phy mode, the switch fabric mac outputs are routed to internal phy b. similarly, the switch fabric mac inputs are sourced from internal phy b. the d uplex of the switch fabric mac is controlled by the phy.
-page 342 ? 2015 microchip technology inc. 13.4 switch fabric timing requirements 13.4.1 rmii interface timing (mac mode) this section specifies the rm ii interface timing when in mac mode. both input and output clock modes are specified. figure 13-1: rmii clock output mode timing (mac mode) table 13-1: rmii clock output mode timing values (mac mode) symbol description min max units notes t clkp p0_outclk period 20 - ns t clkh p0_outclk high time t clkp * 0.4 t clkp * 0.6 ns t clkl p0_outclk low time t clkp * 0.4 t clkp * 0.6 ns t val p0_outd[1:0] , p0_outdv output valid from ris- ing edge of p0_outclk -14.0ns note 5 t ohold p0_outd[1:0] , p0_outdv output hold from ris- ing edge of p0_outclk 3.0 - ns note 5 t su p0_ind[1:0] , p0_iner , p0_indv setup time to rising edge of p0_inclk 4.0 - ns note 5 t ihold p0_ind[1:0] , p0_iner , p0_indv input hold time after rising edge of p0_inclk 1.5 - ns note 5 p0_outclk p0_outd[1:0] p0_outdv t clkh t clkl t clkp t val t ohold (output) t val t val t ohold t su p0_ind[1:0], p0_iner p0_indv t ihold t su t ihold t ihold t su t ihold
? 2015 microchip technology inc. -page 343 note 5: timing was designed for system load between 10 pf and 25 pf. note 6: timing was designed for system load between 10 pf and 25 pf. figure 13-2: rmii clock inpu t mode timing (mac mode) table 13-2: rmii clock input mo de timing values (mac mode) symbol description min max units notes t clkp p0x_outclk period 20 - ns t clkh p0_outclk high time t clkp * 0.35 t clkp * 0.65 ns t clkl p0_outclk low time t clkp * 0.35 t clkp * 0.65 ns t oval p0_outd[1:0] , p0_outdv output valid from ris- ing edge of p0_outclk -14.0ns note 6 t ohold p0_outd[1:0] , p0_outdv output hold from ris- ing edge of p0_outclk 3.0 - ns note 6 t su p0_ind[1:0] , p0_iner , px_indv setup time to rising edge of p0_inclk 4.0 - ns note 6 t ihold p0_ind[1:0] , p0_iner , p0_indv input hold time after rising edge of p0_inclk 1.5 - ns note 6 p0_outclk p0_outd[1:0] p0_outdv t clkh t clkl t clkp t val t ohold (input) t val t val t ohold t su p0_ind[1:0], p0_iner p0_indv t ihold t su t ihold t ihold t su t ihold
-page 344 ? 2015 microchip technology inc. 13.4.2 rmii interface timing (phy mode) this section specifies the rm ii interface timing when in phy mode. both input and output clock modes are specified. note 7: timing was designed for system load between 10 pf and 25 pf. figure 13-3: rmii clock output mode timing (phy mode) table 13-3: rmii clock output mode timing values (phy mode) symbol description min max units notes t clkp p0_outclk period 20 - ns t clkh p0_outclk high time t clkp * 0.4 t clkp * 0.6 ns t clkl p0_outclk low time t clkp * 0.4 t clkp * 0.6 ns t val p0_outd[1:0] , p0_outdv output valid from ris- ing edge of p0_outclk -14.0ns note 7 t ohold p0_outd[1:0] , p0_outdv output hold from ris- ing edge of p0_outclk 3.0 - ns note 7 t su p0_ind[1:0] , p0_indv setup time to rising edge of p0_inclk 4.0 - ns note 7 t ihold p0_ind[1:0] , p0_indv input hold time after ris- ing edge of p0_inclk 1.5 - ns note 7 p0_outclk p0_outd[1:0] p0_outdv t clkh t clkl t clkp t val t ohold (output) t val t val t ohold t su p0_ind[1:0], p0_iner p0_indv t ihold t su t ihold t ihold t su t ihold
? 2015 microchip technology inc. -page 345 note 8: timing was designed for system load between 10 pf and 25 pf. figure 13-4: rmii clock input mode timing (phy mode) table 13-4: rmii clock input mode timing values (phy mode) symbol description min max units notes t clkp p0_outclk period 20 - ns t clkh p0_outclk high time t clkp * 0.35 t clkp * 0.65 ns t clkl p0_outclk low time t clkp * 0.35 t clkp * 0.65 ns t oval p0_outd[1:0] , p0_outdv output valid from ris- ing edge of p0_outclk -14.0ns note 8 t ohold p0_outd[1:0] , p0_outdv output hold from ris- ing edge of p0_outclk 3.0 - ns note 8 t su p0_ind[1:0] , p0_indv setup time to rising edge of p0_inclk 4.0 - ns note 8 t ihold p0_ind[1:0] , p0_indv input hold time after ris- ing edge of p0_inclk 1.5 - ns note 8 p0_outclk p0_outd[1:0] p0_outdv t clkh t clkl t clkp t val t ohold (input) t val t val t ohold t su p0_ind[1:0], p0_iner p0_indv t ihold t su t ihold t ihold t su t ihold
-page 346 ? 2015 microchip technology inc. 14.0 mii management 14.1 functional overview this chapter details the mii management functio nality provided by the device, which includes the smi slave controller , the phy management interface (pmi) and the mii management multiplexer . the smi slave controller is used for cpu management of the device vi a the mii pins and allows cpu access to all system csrs and the phy management interface (pmi) is used to access the internal phys and optional external phy, dependent on the mode of operation. the mii management multiplexer is used to direct the connections of the mii management path based on the selected mode of the device. 14.2 smi slave controller the smi slave controller provides a serial slave interface for an external master to access the device?s internal registers. the smi slave controller uses the same pins and protocol as the ieee 802.3 mii management function and differs only in that smi provides access to all internal registers by using a non-standard extended addr essing map. the smi protocol co-exists with the mii management protocol by using the upper half of the phy address space (16 through 31). all direct and indirect registers can be accessed. the smi management mode is selected when the serial_mngt_mode_strap configuration strap is set to 0b. 14.2.1 device initialization until the device has been initialized to the point where th e various configuration inputs are valid, the smi slave will not respond to or be affected by any external pin activity. 14.2.2 access during and following power management during any power management mode other than d0, reads an d writes are ignored and the smi slave interface will not respond to or be affected by any external pin activity. 14.2.3 smi slave command format the mii management protocol is limited to 16-bit data accesse s. the protocol is also limited to 5 phy address bits and 5 register address bits. the smi frame format can be seen in table 14-1 . the device uses the phy address field bits 3:0 as the system register address bits 9:6 and the register address field as th e system register address bits 5:1. reg- ister address field bit 0 is used as the upper/lower word select. the device requires two back-to-back accesses to each register (with alternate settings of register address field bit 0) which are combined to form a 32-bit access. the access may be performed in any order. note: when accessing the device, the pair of cycles must be atomic. in this case , the first host smi cycle is per- formed to the low/high wo rd and the second host smi cycle is perf ormed to the high/l ow word, forming a 32-bit transaction with no cycles to the device in between. wi th the exception of register a ddress field bit 0, all address and control bits must be the same for both 16-bit cycles of a 32-bit transaction. input data on the mdio pin is sampled on the rising edge of the mdc input clock. output data is sourced on the mdio pin with the rising edge of the clock. the mdio pin is three-stated unless actively driving read data. a read or a write is performed using the frame format shown in table 14-1 . all addresses and data are transferred msb first. data bytes are transferred little endian. when register address bit 0 is 1, bytes 3 & 2 are selected with byte 3 occurring first. when register address bit 0 is 0, by tes 1 & 0 are selected with byte 1 occurring first.
? 2015 microchip technology inc. -page 347 note 1: phy address bit 4 is 1 for smi commands. phy addre ss 3:0 form system register address bits 9:6. the register address field forms the system register address bits 5:1. note 2: the turn-around time (ta) is used to avoid contention during a read cycle. for a read, the device drives the second bit of the turn-aroun d time to 0 and then drives the msb of the read data in the following clock cycle. for a write, the external host drives the first bit of t he turn-around time to 1, the second bit of the turn-around time to 0 and then the msb of the wr ite data in the fo llowing clock cycle. note 3: in the idle condition, the mdio output is three-stated and pulled high externally. 14.2.3.1 read sequence in a read sequence, the host sends the 32-bit preamble, 2- bit start of frame, 2-bit op-code, 5-bit phy address and the 5-bit register address. the next clock is the first bit of t he turn-around time in which the device continues to three-state mdio . on the next rising edge of mdc , the device drives mdio low. for the next 16 rising edges, the device drives the output data. on the final clock, the device once again three-states mdio . the host processor is required to perform two consecutive 16-b it reads to complete a single dword transfer. no order- ing requirements exist. the processor can access either th e low or high word first, as long as the next read is per- formed from the other word. if a read to the same word is performed, the combined data read pair is invalid and should be re-read. this is not a fatal error. the device will simply reset the read counters and restart a new cycle on the next read. note: selected registers are readable as 16-b it registers, as noted in their re gister descriptions. for these regis- ters, only one 16-bit read may be performed without the need to read the other word. note: smi reads from unused register addresses return all zeros. this differs from unused phy registers which leave mdio un-driven. special csr handling live bits since data is read serially, in order to prevent the host from readi ng a potentially changing value (such as a live bit or a counter that spans across two words), 32-bits of register da ta are latched (registered) at the beginning of the first word of a dword transfer and held until the end of the second word of the dword. change on read registers and fifos any register that is affected by a read op eration (e.g. a clear on read bit or fifo) is updated once the output shift of the second word has started. in the event that all bits are not re ad, the register is still affected and any prior data is lost. it is assumed that the second read is from the same register and opposite word. there is no hardware check. change on read live register bits as described above, the current value from a register with live bits (as is the case of any register) is saved before the data is shifted out. although a hardware event that occurs following the data capture would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) once the output shif t has started and the hardware event would be lost. in order to prevent this, the individual csrs defer t he hardware event update until after the read indication. table 14-1: smi frame format preamble start op cod e phy address note 1 register address note 1 turn- around time note 2 data idle note 3 read 32 1?s 01 10 1aaaa _ 9876 aaaaa 54321 z0 dddddddddddddddd 1111110000000000 5432109876543210 z write 32 1?s 01 01 1aaaa _ 9876 aaaaa 54321 10 dddddddddddddddd 1111110000000000 5432109876543210 z
-page 348 ? 2015 microchip technology inc. smi read polling for initialization complete before device initialization or during pow er management, the smi slave interface will not return valid data. to determine when the smi slave is functional, the byte order test register (byte_test) should be polled. once the correct pattern is read, the interface can be consid ered functional. at this point, the device ready (ready) bit in the hardware con- figuration register (hw_cfg) can be polled to determine when the device is fully configured. device initialization may finish, or power management ma y exit, between the two 16-bit halves of a dword access, therefore the device may not see both word accesses. howeve r, the device cannot be left in a state where it expects another 16-bit read to comple te the dword cycle. specific registers may be read during a rese t without leaving the device in such a state. these are the byte order test register (byte_test) , the hardware configuration register (hw_cfg) , the power management control register (pmt_ctrl) and the reset control register (reset_ctl) . 14.2.3.2 write sequence in a write sequence, the host sends the 32-bit preamble, 2-bit start of frame, 2-bit op-code, 5-bit phy address, 5-bit register address, 2-bit turn-around time and finally the 16 bits of data. the mdio pin is three-stated throughout the write sequence. the host processor is required to perfor m two contiguous 16-bit writes to comple te a single dword transfer. no order- ing requirement exists. the host may access either the low or high word first, as long as the next write is performed to the opposite word. it is assumed that the second writ e is to the same register and opposite word. there is no hardware check. note: the host must not perform smi writ es to unused register addresses. there is no hardware check.
? 2015 microchip technology inc. -page 349 14.2.4 smi timing requirements note 4: the smi slave design changes output data a nominal 4 clocks (100mhz) maximum and a nominal 2 clocks (100 mhz) minimum following the rising edge of mdc . note 5: the smi slave design samples input data using the rising edge of mdc . figure 14-1: smi timing table 14-2: smi timing values symbol description min max units notes t clkp mdc period 400 - ns t clkh mdc high time 160 (80%) - ns t clkl mdc low time 160 (80%) - ns t val mdio output valid from rising edge of mdc - 300 ns note 4 t ohold mdio output hold from rising edge of mdc 10 - ns note 4 t su mdio input setup time to rising edge of mdc 10 - ns note 5 t ihold mdio input hold time after rising edge of mdc 5-ns note 5 mdc mdio t clkh t clkl t clkp t ohold mdio t su t ihold (data-out) (data-in) t ohold t val
-page 350 ? 2015 microchip technology inc. 14.3 phy management interface (pmi) the pmi provides an parallel to serial interface used to a ccess the internal physical phys as well as the external phy on the mii pins (in mac modes). 14.3.1 pmi slave command format the pmi operates at 2.5 mhz and implements the ieee 8 02.3 management protocol, prov iding read/write commands for phy configuration. a read or write is performed using the frame format shown in table 14-3 . all addresses and data are transferred msb first. data bytes are transferred little endian. note 6: the turn-around time (ta) is used to avoid bus contention during a read cycle. for a read, the external phy drives the second bit of the turn-around time to 0 and then drives the msb of the read data in the following cycle. for a write, the device drives the first bit of the turn-around time to 1, the second bit of the turn-around time to 0 and then the msb of the write data in the following clock cycle. note 7: in the idle condition, the p0_mdio output is three-stated and pulled high externally. p0_mdc is driven. 14.3.2 phy register host access the phy management interface (pmi) is us ed by the host to access the internal physical phys as well as the external phy on the mii pins (in mac modes). 14.3.3 eeprom loader phy register access the phy management interface a ccess register (pmi_access) and phy management interface data register (pmi_data) are accessible as part of the register data burst sequence of the eeprom loader. refer to section 12.4, "eeprom loader," on page 332 for additional information. table 14-3: mii mana gement frame format preamble start op code phy address register address turn- around time note 6 data idle note 7 read 32 1?s 01 10 aaaaa rrrrr z0 dddddddddddddddd z write 32 1?s 01 01 aaaaa rrrrr 10 dddddddddddddddd z
? 2015 microchip technology inc. -page 351 14.3.4 pmi timing requirements note 8: the pmi design outputs a nominal 400 ns clock with a 50/50 duty cycle. note 9: the pmi design changes output data a no minal 120 ns following the rising edge of mdc . note 10: the pmi design samples input data a nominal 40 ns prior to the rising edge of mdc . figure 14-2: pmi timing table 14-4: pmi timing values symbol description min max units notes t clkp mdc period 400 - ns note 8 t clkh mdc high time 180 (90%) - ns note 8 t clkl mdc low time 180 (90%) - ns note 8 t val mdio output valid from rising edge of mdc - 250 ns note 9 t ohold mdio output hold from rising edge of mdc 50 - ns note 9 t su mdio input setup time to rising edge of mdc 70 - ns note 10 t ihold mdio input hold time after rising edge of mdc 0 - ns note 10 mdc mdio t clkh t clkl t clkp t ohold mdio t su t ihold (data-out) (data-in) t ohold t val
-page 352 ? 2015 microchip technology inc. 14.3.5 phy management interface (pmi) registers the directly addressable pmi registers are used to i ndirectly access the physical phy registers. refer to section 9.2.20, "physical phy registers," on page 102 for additional information on the phy registers. 14.3.5.1 phy management interf ace data register (pmi_data) this register is used in conjunction with the phy management interface access register (pmi_access) to perform read and write operations to the phys. table 14-5: pmi registers address register name (symbol) 0a4h phy management interface data register (pmi_data) 0a8h phy management interface access register (pmi_access) offset: 0a4h size: 32 bits bits description type default 31:16 reserved ro - 15:0 mii data this field contains the value read from or written to the phys. for a write operation, this register should be firs t written with the desired data. for a read operation, the pmi_access register is first writte n and once the command is finished, this register will contain the return data. note: upon a read, the value returned depends on the mii write bit (miiwnr) in the phy management interface access register (pmi_access) . if miiwnr is 0, the data is from the phy. if miiwnr is 1, the data is the value that was last written into this register. note: the eeprom loader can only perform register write operations. r/w 0000h
? 2015 microchip technology inc. -page 353 14.3.5.2 phy management interface access register (pmi_access) this register is used to control the m anagement cycles to the phys. a phy access is initiated when this register is writ- ten. this register is used in conjunction with the phy management interface data register (pmi_data) to perform read and write operations to the phys. offset: 0a8h size: 32 bits bits description type default 31:16 reserved ro - 15:11 phy address (phy_addr) these bits select the phy device being accessed. refer to section 9.1.1, "phy addressing," on page 77 for information on phy address assignments. note: the eeprom loader can only perform register write operations. r/w 00000b 10:6 mii register index (miirinda) these bits select the desired mii register in the phy. refer to section 9.2.20, "physical phy registers," on page 102 for detailed descriptions on all phy registers. note: the eeprom loader can only perform register write operations. r/w 00000b 5:2 reserved ro - 1 mii write (miiwnr) setting this bit informs the phy that the access will be a write operation using the phy management interface data register (pmi_data) . if this bit is cleared, the access will be a read operation, returning data into the phy management interface data register (pmi_data) . note: the eeprom loader can only perform register write operations. note: the eeprom loader typically only performs pmi write operations since it can not read registers. r/w 0b 0 mii busy (miibzy) this bit must be read as 0 before writing to the phy management interface data register (pmi_data) or phy management interface access register (pmi_access) registers. this bit is automatic ally set when this register is written. during a phy register access, this bit will be set, signifying a read or write access is in progress. this is a self -clearing (sc) bit that will return to 0 when the phy register access has completed. during a phy register write, the phy management interface data register (pmi_data) must be kept valid until this bit has cleared. during a phy register read, the phy management interf ace data register (pmi_data) register is valid after this bit has cleared. note: the eeprom loader contains logic which directly checks this bit. ro sc 0b
-page 354 ? 2015 microchip technology inc. 14.4 mii management multiplexer the mii management multiplexer is used to direct the mii management path connections. one master is connected to the slaves dependent on the selected m anagement mode. the mii management mult iplexer also performs the multi- plexing of the read data signals from the slaves an d controls the output e nable of the mii pins. 14.4.1 port 0 management path configurations port 0 can be configured into the following modes of operation: ? port 0 mac mode smi managed ? port 0 mac mode smi managed - device initialization ? port 0 phy mode smi managed ? port 0 phy mode smi managed - device initialization ? port 0 mac mode i2c managed ? port 0 phy mode i2c managed
? 2015 microchip technology inc. -page 355 14.4.1.1 port 0 mac mode smi managed in this mode, physical phys a and b and the smi slave block ar e accessed via an external master attached to the port 0 rmii pins. the virtual phy parallel interface is acce ssible via the smi slave and the eeprom loader. however, this block is not used in this mode. the pmi parallel interface is accessible vi a the smi slave and the eeprom loader. however, this block is not used in this mode once device initialization is complete. figure 14-3 details the mii mode multiplexer management path connections for this mode. figure 14-3: mii mux management path connections - mac mode smi managed smi slave mdi mdo mdio_dir mdc parallel master virtual phy mdi mdo mdio_dir mdc parallel slave phy b mdi mdo mdio_dir mdc phy a mdi mdo mdio_dir mdc management mode selection mii pins mdi mdo mdio_dir mdc_in mdc_out mdc_dir p i n m u x i n g management mode selection pmi mdi mdo mdc parallel slave mdio_en_n p0_mdio p0_mdc
-page 356 ? 2015 microchip technology inc. 14.4.1.2 port 0 mac mode smi managed - device initialization in this mode, during device initiali zation, physical phys a and b are accessed by the pmi. the smi slave block is accessed via an external master attached to the port 0 rmii pins. the virtual phy parallel interface is accessible via the eeprom loader. however, this block is not used in this mode. the pmi parallel interface is accessible via the eeprom loader. the eeprom loader may access phys a and b through the pmi registers. figure 14-4 details the mii mode multiplexer management path connections for this mode. figure 14-4: mii mux management path connections - mac mo de smi managed - device initialization smi slave mdi mdo mdio_dir mdc parallel master virtual phy mdi mdo mdio_dir mdc parallel slave phy b mdi mdo mdio_dir mdc phy a mdi mdo mdio_dir mdc management mode selection mii pins mdi mdo mdio_dir mdc_in mdc_out mdc_dir p i n m u x i n g management mode selection pmi mdi mdo mdc parallel slave mdio_en_n p0_mdio p0_mdc
? 2015 microchip technology inc. -page 357 14.4.1.3 port 0 phy mode smi managed in this mode, physical phys a and b, the virtual phy an d the smi slave block are accessed via an external master attached to the port 0 mii pins. the virtual phy parallel interface is acce ssible via the smi slave and the eeprom loader. the pmi parallel interface is accessible via the smi slave and the eeprom loader. however, this block is not used in this mode once device initialization is complete. figure 14-5 details the mii mode multiplexer management path connections for this mode. figure 14-5: mii mux management path connections - phy mode smi managed smi slave mdi mdo mdio_dir mdc parallel master virtual phy mdi mdo mdio_dir mdc parallel slave phy b mdi mdo mdio_dir mdc phy a mdi mdo mdio_dir mdc management mode selection mii pins mdi mdo mdio_dir mdc_in mdc_out mdc_dir p i n m u x i n g management mode selection pmi mdi mdo mdc parallel slave mdio_en_n p0_mdio p0_mdc
-page 358 ? 2015 microchip technology inc. 14.4.1.4 port 0 phy mode smi ma naged - device initialization during device initialization, physical phys a and b are accessed by the pmi. the virtua l phy and the smi slave block are accessed via an external master attached to the port 0 mii pins. the virtual phy parallel interface is accessible via the eeprom loader. the pmi parallel interface is accessible via the eeprom loader. the eeprom loader may access phys a and b through the pmi registers. figure 14-6 details the mii mode multiplexer management path connections for this mode. figure 14-6: mii mux management path connections - phy mode smi managed - device initialization smi slave mdi mdo mdio_dir mdc parallel master virtual phy mdi mdo mdio_dir mdc parallel slave phy b mdi mdo mdio_dir mdc phy a mdi mdo mdio_dir mdc management mode selection mii pins mdi mdo mdio_dir mdc_in mdc_out mdc_dir p i n m u x i n g management mode selection pmi mdi mdo mdc parallel slave mdio_en_n p0_mdio p0_mdc
? 2015 microchip technology inc. -page 359 14.4.1.5 port 0 mac mode i 2 c managed in this mode, physical phys a and b and the external phy attached to the port 0 mii pins are accessed by the pmi. the pmi parallel interface is accessible via the i 2 c slave and the eeprom loader. the eeprom loader may access phys a and b, as well as the external phy, through the pmi registers. the virtual phy para llel interface is accessible via the smi slave and the eeprom loader. however, this block is not used in this mode. figure 14-7 details the mii mode multiplexer management path connections for this mode. figure 14-7: mii mux management path connections - mac mode i 2 c managed default = mii pins smi slave mdi mdo mdio_dir mdc parallel master virtual phy mdi mdo mdio_dir mdc parallel slave phy b mdi mdo mdio_dir mdc phy a mdi mdo mdio_dir mdc management mode selection mii pins mdi mdo mdio_dir mdc_in mdc_out mdc_dir p i n m u x i n g management mode selection pmi mdi mdo mdc parallel slave mdio_en_n p0_mdio p0_mdc
-page 360 ? 2015 microchip technology inc. 14.4.1.6 port 0 phy mode i 2 c managed in this mode, physical phys a and b are accessed via the pmi. the virtual phy is accessed via an external master attached to the port 0 mii pins. the pmi pa rallel interface is accessible via the i 2 c slave and the eeprom loader. the eeprom loader may access phys a and b through the pmi regi sters. the virtual phy parallel interface is accessible via the i 2 c slave and the eeprom loader. figure 14-8 details the mii mode multiplexer management path connections for this mode. figure 14-8: mii mux management path connections - phy mode i 2 c managed default = 1 smi slave mdi mdo mdio_dir mdc parallel master virtual phy mdi mdo mdio_dir mdc parallel slave phy b mdi mdo mdio_dir mdc phy a mdi mdo mdio_dir mdc management mode selection mii pins mdi mdo mdio_dir mdc_in mdc_out mdc_dir p i n m u x i n g management mode selection pmi mdi mdo mdc parallel slave mdio_en_n p0_mdio p0_mdc
? 2015 microchip technology inc. -page 361 15.0 ieee 1588 15.1 functional overview the device provides hardware support for the ieee 1588-2008 precision time protocol (ptp), allowing clock synchro- nization with remote ethernet de vices, packet time stamping, and time driven event generation. note: support for the ieee 1588 -2002 (v1) packet format is not provided. time stamping is supported on all ports, with an indivi dual ptp timestamp sub-module connected to each port. any port may function as a master or a slave clock per the ie ee 1588-2008 specification, and the device as a whole may function as a transparent or boundary clock. both end-to- end and peer-to-peer link delay mechanisms are supported as are one-step and two-step operations. a 32-bit seconds and 30-bit nanoseconds tunable clock is prov ided that is used as the time source for all ptp timestamp related functions. a 1588 clock events sub-module provi des 1588 clock comparison based interrupt generation and timestamp related gpio event generati on. gpio pins can be used to trigger a timestamp capture when configured as an input, or output a signal based on a 1588 clock target compare event. all features of the ieee 1588 unit can be monitored and confi gured via their respective configuration and status regis- ters. a detailed description of all 1588 csrs is included in section 15.8, "1588 registers" . 15.1.1 ieee 1588-2008 ieee 1588-2008 specifies a precision time protocol (ptp) used by master and slave clock devices to pass time infor- mation in order to achieve clock synchroniza tion. ten network message types are defined: ? sync ? follow_up ? delay_req ? delay_resp ? pdelay_req ? pdelay_resp ? pdelay_resp_follow_up ? announce ? signaling ? management the first seven message types are used for clock synchronization. using these messages, the protocol software may calculate the offset and network delay between timestam ps, adjusting the slave clock frequency as needed. refer to the ieee 1588-2008 protocol for message definitions and proper usage. a ptp domain is segmented into ptp sub-domains, which ar e then segmented into ptp communication paths. within each ptp communication path there is a ma ximum of one master clock, which is th e source of time for each slave clock. the determination of which clock is the master and which cl ock(s) is(are) the slave(s) is not fixed, but determined by the ieee 1588-2008 protocol. similarly, each ptp sub-domain may have only one master clock, referred to as the grand master clock. ptp communication paths are conceptually equivalent to et hernet collision domains and may contain devices which extend the network. however, unlike et hernet collision domains, the ptp communi cation path does not stop at a net- work switch, bridge, or router. this leads to a loss of prec ision when the network switch/bridge/router introduces a vari- able delay. boundary clocks are defined which conceptually by pass the switch/bridge/router (either physically or via device integration). essentially, a boundary clock acts as a sl ave to an upstream master, and as a master to a down stream slave. a boundary clock may contain multiple ports, but a maximum of one slave port is permitted. although boundary clocks solve the issue of the variable delay influencing the synchronization accuracy, they add clock jitter as each boundary clock tracks the clock of its upstream master. another approach that is supported is the concept of transparent clocks. these devices measure the delay they ha ve added when forwarding a message (the residence time) and report this additional delay either in the forw arded message (one-step) or in a subsequent message (two- step). the ptp relies on the knowledge of the path delays between t he master and the slave. with this information, and the knowledge of when the master has sent the packet, a slave can calculate its clock offset from the master and make appropriate adjustments. there are two methods of obtaining the network path delay. using the end-to-end method, packets are exchanged between the slave and the master. an y intermediate variable bridge or switch delays are com-
-page 362 ? 2015 microchip technology inc. pensated by the transparent clock method described above. us ing the round trip time and accounting for the residence time reported, the slave can calculate the mean delay fr om the master. each slave sends and receives its own mes- sages and calculates its own delay. while the end-to-end method is the simplest, it does add burden on the master since the master must process packets from each slave in the system. this is amplified when boundary clocks are replaced by transparent clocks. also, the end-to-e nd delays must be recalculated if ther e is a change in the network topology. using the peer-to-peer method, packets are exchanged only be tween adjacent master, slaves and transparent clocks. each peer pair calculates the receive path delay. as time synchronization packets are forwarded between the master and the slave, the transparent clock adds the pre-measured receive path delay into the residence time. the final receiver adds its receive path delay. using the peer-to-peer me thod, the full path delay is accounted for without the mas- ter having to service each slave. the peer-to-peer method better supports network topo logy changes since each path delay is kept up-to-date regardless of the port status. the ptp implementation consists of the following major function blocks: ? ptp timestamp and residence time correction this block provides time stamping and packet modification functions. ? 1588 clock this block provides a tunable clock that is used as th e time source for all ptp timestamp related functions. ? 1588 clock events this block provides clock comparison-based interrupt generation and timestamp related gpio event generation. ? 1588 gpios this block provides for time stamping gpio input events and for outputting clock comparison-based interrupt sta- tus. ? 1588 interrupt this block provides interrupt generation, masking and status. ? 1588 registers this block provides contains all configuration, control and status registers.
? 2015 microchip technology inc. -page 363 15.2 ptp timestamp and residence time correction this sub-module handles all ptp packet tasks related to recording timestamps of packets, accounting for the frame for- warding delay through the switch and inserting timestamps into packets. modes supported are: ? boundary clock, master and slave, one-step and two-step, end-to-end or peer-to-peer delay - all 1588 packets are to and from the host mac (as directed by switch core) - special host vlan tagging (via switch core) indicates ingress port and desired egress port - rx and tx timestamps saved in registers for s/w - rx timestamp stored in packet for ease of retrieval by s/w - egress timestamp of sync packet inserted on-the-fly for one-step - tx timestamp of delay_req packe t stored in received delay_resp packet for ease of retrieval - correction field and ingress timestamp of pdelay_req packet saved in registers for one-step turnaround time - correction field of pdelay_resp packet automaticall y calculated and inserted on-the-fly for one-step - ptp checksums and ethernet fcs updated on-the-fly - ingress and egress timestamps corrected for latency - asymmetry corrections - peer delay correction on received sync packets ? transparent clock with ordinary clo ck, master and slave, one-step and tw o-step, end-to-end or peer-to-peer delay - peer-to-peer received 1588 packets forwarded to host (p eer-to-peer mode) or to other network port (end-to- end mode) (as directed by switch core) - all other received 1588 packets forwarded to host and other network port (as directed by switch core) - special host vlan tagging (via switch core) indicates ingress port and desired egress port - rx and tx timestamps saved in registers for s/w - rx timestamp stored in packet for ease of retrieval by s/w - residence time correction on forwarded sync, delay_req, pdelay_req and pdelay_resp packets ingress timestamp subtracted from correction field on receive egress timestamp added to correction field on-the-fly during transmit - egress timestamp of host sync packet inserted on -the-fly for one-step (for master ordinary clock) - correction field and ingress timestamp of pdelay_req packet saved in registers for one-step turnaround time (peer-to-peer mode) - correction field of host pdelay_resp packet automa tically calculated and inse rted on-the-fly for one-step (peer-to-peer mode) - ptp checksums and ethernet fcs updated on-the-fly - ingress and egress timestamps corrected for latency - asymmetry corrections - peer delay correction on received sync packets functions include: ? detecting a ptp packet - 802.3/snap or ethernet ii encoding - skipping over vlan tags - ethernet, ipv4 or ipv6 message formats - skipping over ip extension headers - checking the mac and / or the ip addresses ? recording the timestamp of received packets into registers - accounting for the ingress latency ? recording the timestamp of received packets into the packet and updating the layer 3 checksu m and layer 2 fcs fields - accounting for the ingress latency
-page 364 ? 2015 microchip technology inc. ? forwarding or filtering ptp packets as needed to support ordinary, boundary or transparent clock mode ? recording the timestamp of transmitted packets into registers - accounting for the egress latency ? updating the correction field to acco unt for the residence time in the sw itch and updating th e layer 3 checksum and layer 2 fcs - accounting for the peer delay and link asymmetry ? one-step on-the-fly timestamp insertion for sync packe ts and updating the layer 3 checksum and layer 2 fcs ? one-step on-the-fly turnaround time insertion for pdelay_req packets and updating the layer 3 checksum and layer 2 fcs note: support for the ieee 1588 -2002 (v1) packet format is not provided. three instances of this sub-module are used, one for each switch port. when a switch port is connected to an soc mac, the ptp sub-module for that switch port typi cally would not be configured to operate. 15.2.1 receive frame processing 15.2.1.1 ingress time snapshot for each ethernet frame, the receive frame processing detects the sfd field of the frame and temporarily saves the current 1588 clock value. ingress latency the ingress latency is the amount of time between the star t of the frame?s first symbol after the sfd on the network medium and the point when the 1588 clock value is internally captured. it is specified by the rx latency (rx_la- tency[15:0]) field in the 1588 port x latency register (1588_latency_x) and is subtracted from the 1588 clock value at the detection of the sfd. the setting is used to adjust the internally captured 1588 clock value such that the resultant timestamp more accurately co rresponds to the start of the frame?s first symbol after the sfd on the network medium. the ingress latency consists of the receiv e latency of the phy, whether internal or external and the latency of the 1588 frame detection circuitry. the value depends on the port mode. typical values are: ? 100base-tx: 285ns ? 100base-fx: 231ns plus the receive latency of the fiber transceiver ? 10base-t: 1674ns ? 100mbps rmii: 70ns plus any external receive latency ? 10mbps rmii: 440ns plus any external receive latency 15.2.1.2 1588 receive parsing the 1588 receive parsing block parses the incoming frame to identify 1588 ptp messages. note: support for the ieee 1588 -2002 (v1) packet format is not provided. the receive parsing block may be programmed to detect ptp messages encoded in udp/ ipv4, udp/ipv6 and layer 2 ethernet formats via the rx ipv4 enable (rx_ipv4_en) , rx ipv6 enable (rx_ipv6_en) and rx layer 2 enable (rx_layer2_en) bits in the 1588 port x rx parsing configuratio n register (1588_rx_parse_config_x) . vlan tagged and non-vlan tagged frame formats are support ed. multiple vlan tags are handled as long as they all use the standard type of 0x8100. both ethernet ii (type fiel d) and 802.3 (length field) w/ snap frame formats are sup- ported. the following tests are made to determine that the packet is a ptp message. ? mac destination address checking is enabled via the rx mac address enable (rx_mac_addr_en) in the 1588 port x rx parsing configuratio n register (1588_rx_parse_config_x) . for the layer 2 message format, the addresses of 01:1 b:19:00:00:00 or 01:80:c2: 00:00:0e may be enabled via the 1588 port x rx parsing configuratio n register (1588_rx_parse_config_x) . either address is allowed for peer delay and non-peer delay messages. for ipv4/udp messages, any of the iana assigned multicast ip destination addresses for ieee 1588 (224.0.1.129 and 224.0.1.130 through .132), as well as the ip destination address for the peer delay mechanism (224.0.0.107) may be enabled via the 1588 port x rx parsing configurat ion register (1588_rx_parse_con-
? 2015 microchip technology inc. -page 365 fig_x) . these ip addresses map to the 802.3 mac addresses of 01:00:5e: 00:01:81 through 01:00:5e:00:01:84 and 01:00:5e:00:00:6b. any of these addresses are allowed for p eer delay and non-peer delay messages. for ipv6/udp messages, any of the iana assigned multicast ip destination addresses for ieee 1588 (ff0x:0:0:0:0:0:0:181 and ff0x:0:0:0:0:0:0:182 through : 184), as well as the ip destination address for the peer delay mechanism (ff02:0:0:0:0: 0:0:6b) may be enabled via the 1588 port x rx parsing configuration register (1588_rx_parse_config_x) . these ip addresses map to the 802. 3 mac addresses of 33:33:00:00:01:81 through 33:33:00:00:01: 84 and 33:33:00:00:00:6b. any of these addr esses are allowed for peer delay and non- peer delay messages. a user defined mac address defined in the 1588 user mac address high-word register (1588_us- er_mac_hi) and the 1588 user mac address low-dwo rd register (1588_user_mac_lo) may also be indi- vidually enabled for the above formats. ? if the type / length field indicates an ethertype then for the layer 2 message format, the ethertype must equal 0x88f7. for ipv4/udp messages, the ethertype must equal 0x0800. for ipv6/udp messages, the ethertype must equal 0x86dd. ? if the type / length field indicates a length and the next 3 bytes equal 0xaaaa03 (indicating that a snap header is present) and the snap header has a oui equal to 0x000000 then for the layer 2 message format, the ethertype in the snap header must equal 0x88f7. for ipv4/udp messages, the ethertype in the snap header must equal 0x0800. for ipv6/udp messages, the ethertype in the snap header must equal 0x86dd. ? for ipv4/udp messages, the version field in the ipv4 header must equal 4, the ihl field must be 5 and the proto- col field must equal 17 (udp) or 51 (a h). ipv4 options are not supported. ? for ipv6/udp messages, the version field in the ipv6 hea der must equal 6 and the next header field must equal 17 (udp) or one of the ipv6 extension header values (0 - hop-by-hop options, 60 - destination options, 43 - routing, 44 - fragment, 51 - authentication header (ah) ? for ipv4/udp messages, destination ip address checking is enabled via the rx ip address enable (rx_ip_ad- dr_en) in the 1588 port x rx parsing configuratio n register (1588_rx_parse_config_x) . any of the iana assigned multicast ip destination addresses for ieee 1588 ( 224.0.1.129 and 224.0.1.130 through .132), as well as the ip destination address for the peer de lay mechanism (224.0.0.107) may be enabled via the 1588 port x rx parsing configuration register (1588_rx_parse_config_x) . any of these addresses are allowed for peer delay and non-peer delay messages. ? for ipv6/udp messages, destination ip address checking is enabled via the rx ip address enable (rx_ip_ad- dr_en) in the 1588 port x rx parsing configuratio n register (1588_rx_parse_config_x) . any of the iana assigned multicast ip destination addresses for ieee 1588 (ff0x:0:0:0:0:0:0:181 and ff0x:0:0:0:0:0:0:182 through :184), as well as the ip destination address for the peer delay mechanism (f f02:0:0:0:0:0:0:6b) may be enabled via the 1588 port x rx parsing configuration register (1588_rx_parse_config_x) . any of these addresses are allowed for peer delay and non-peer delay messages. ? for ipv4/udp if the protocol field in the fixed header wa s 51 (ah), the next header field is checked for 17 (udp) and the ah header is skipped. ? for ipv6/udp if the next header field in the fixed hea der was one of the ipv6 extens ion header values, the next header field in the extension header is checked for 17 (udp) or one of the ipv6 extension header values. if it is one of the ipv6 extension header values , the process repeats until either a value of 17 (udp) or a value of 59 (no next header) are found or the packet ends. 15.2.1.3 receive message ingress time recording following the determination of packet fo rmat and qualification of the packet as a ptp message above, the ptp header is checked for all of the following. ? the messagetype field of the ptp header is checked and only those messages enabled via the rx ptp mes- sage type enable (rx_ptp_message_en[15:0]) bits in the 1588 port x rx timestamp configuration register
-page 366 ? 2015 microchip technology inc. (1588_rx_timestamp_config_x) will be have their ingress times saved. typically sync, delay_req, pde- lay_req and pdelay_resp messages are enabled. ? the versionptp field of the ptp header is checked against the rx ptp version (rx_ptp_version[3:0]) field in the 1588 port x rx timestamp configuration register (1588_rx_timestamp_config_x) . only those mes- sages with a matching version will be have their ingress times saved. a setting of 0 allows any ptp version. note: support for the ieee 1588 -2002 (v1) packet format is not provided. ? if enabled via the rx ptp domain match en able (rx_ptp_domain_en) bit in the 1588 port x rx timestamp configuration register ( 1588_rx_timestamp_config_x) , the domainnumber field of the ptp header is checked against the rx ptp domain (r x_ptp_domain[7:0]) value in the same register. only those messages with a matching domain will be have their ingress times saved. ? if enabled via the rx ptp alternate master en able (rx_ptp_alt_master_en) bit in the 1588 port x rx time- stamp configuration register (1588_rx_timestamp_config_x) , the alternatemasterflag in the flagfield of the ptp header is checked and only those messages with an alternatemasterflag set to 0 will be have their ingress times saved. at the end of the frame, the frame?s fc s and the udp checksum (for ipv4 and ipv6 formats) are verified. fcs checking can be disabled using the rx ptp fcs check dis able (rx_ptp_fcs_dis) bit in the 1588 port x rx timestamp con- figuration register (1588_rx_timestamp_config_x) . udp checksum checking c an be disabled using the rx ptp udp checksum check disable (rx_ptp_udp_chksum_dis) bit in the same register. note: a ipv4 udp checksum value of 0x00 00 indicates that the checksum is not included and is considered a pass. a ipv6 udp checksum value of 0x0000 is invalid and is considered a fail. note: for ipv6, the udp checksum calculatio n includes the ipv6 pseudo heade r. part of the ipv6 pseudo header is the final ipv6 destination address. if the ipv6 packet does not contain a routing header, t hen the final ipv6 destination address is the destina- tion address contained in the ipv6 header. if the ipv6 packet does contain a routing header, then the final ipv6 destination address is the address in the last element of the routing header. note: the udp checksum is calculated over the entire udp payload as indicat ed by the udp length field and not the assumed ptp packet length. note: the udp checksum calculation does not included layer 2 pad bytes, if any. if the fcs and checksum tests pass: ? the latency adjusted, 1588 clock value, saved above at the start of the frame, is recorded into the 1588 port x rx ingress time seconds register (1588_rx_ingress_sec_x) and 1588 port x rx ingress time nanoseconds register (1588_rx_ingress_ns_x) . ? the messagetype and sequenceid fields and 12-bit crc of t he portidentity field of the ptp header are recorded into the message type (msg_type) , sequence id (seq_id) and source port identity crc (src_prt_crc) fields of the 1588 port x rx message header register (1588_rx_msg_header_x) . the 12-bit crc of the portidentity field is created by using the polynomial of x 12 + x 11 + x 3 + x 2 + x + 1. ? the corresponding maskable 1588 rx timestamp interrupt (1588_rx_ts_int[2:0]) is set in the 1588 interrupt status register (1588_int_sts) . up to four receive events are saved per port with the count shown in the 1588 rx timestamp count (1588_rx- _ts_cnt[2:0]) field in the 1588 port x capture information register (1588_cap_info_x) . additional events are not recorded. when the appropriate 1588 rx timestamp interrupt (1588_rx_ts_int[2:0]) bit is written as a one to clear, 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) will decrement. if there are remaining events, the capture regis- ters will update to the next event and the interrupt will set again. pdelay_req ingress time saving one-step pdelay_resp messages sent by t he host, require their correctionfield to be calculated on-the-fly to include the turnaround time between the ingress of the p delay_req and the egress time of the pdelay_resp. the 1588 port x rx pdelay_req ingress time seconds register (1588_rx_pdreq_sec_x) and the 1588 port x rx pdelay_req ingress time nanosecon ds register (1588_rx_pdreq_ns_x) hold the ingress time of the pdelay_req message.
? 2015 microchip technology inc. -page 367 the 1588 port x rx pdelay_req ingress correction field high register (1588_rx_pdreq_cf_hi_x) and the 1588 port x rx pdelay_req ingress correction field low register (1588_rx_pdreq_cf_low_x) hold the correctionfield of the pdelay_req message. these registers can be set by s/w prio r to sending the pdelay_resp message. alternatively, these registers can be updated by the h/w when the pdelay_req me ssage is received. this function is enabled by the auto update (auto) bit in the 1588 port x rx pdelay_req ingress time nanoseconds register (1588_rx_pdreq_ns_x) independent from the rx ptp message type enabl e (rx_ptp_messag e_en[15:0]) bits. as above (including all applicable notes): ? the versionptp and domainnumber fields and alternat emasterflag in the flagfield of the ptp header are checked, if enabled. note: support for the ieee 1588 -2002 (v1) packet format is not provided. ? at the end of the frame, the frame?s fcs and the udp ch ecksum (for ipv4 and ipv6 formats) are verified, if enabled. if all tests pass, then the pdelay_req message information is updated. 15.2.1.4 ingress pa cket modifications ingress time insertion into packets as an alternate to reading the receive time stamp from regi sters and matching it to the correct frame received in the host mac, the saved, latency adjusted, 15 88 clock value can be stored into the packet. this function is enabled via the rx ptp insert timestamp enable (rx_ptp_insert_ts_en) and rx ptp insert timestamp seconds enable (rx_ptp_insert_ts_sec_en) bits in the 1588 port x rx timestamp insertion config- uration register (1588_rx_ts_insert_config_x) . note: inserting the ingress time into the packet is an addi tional, separately enabled, feature verses the ingress time recording described above. the capture registers are still updated as is the appropriate 1588 rx timestamp interrupt (1588_rx_ts_int[2:0]) bit and the 1588 rx timestamp count (1588_rx- _ts_cnt[2:0]) field. following the determination of packet fo rmat and qualification of the packet as a ptp message above, the ptp header is checked for all of the following. ? the messagetype field of the ptp header is checked and only those messages enabled via the rx ptp mes- sage type enable (rx_ptp_message_en[15:0]) bits in the 1588 port x rx timestamp configuration register (1588_rx_timestamp_config_x) will be have their ingress times inserted. typically sync, delay_req, pde- lay_req and pdelay_resp messages are enabled. ? the versionptp field of the ptp header is checked against the rx ptp version (rx_ptp_version[3:0]) field in the 1588 port x rx timestamp configuration register (1588_rx_timestamp_config_x) . only those mes- sages with a matching version will be have their ingress times inserted. a setting of 0 allows any ptp version. note: support for the ieee 1588 -2002 (v1) packet format is not provided. note: the domainnumber field and alternatemasterflag in th e flagfield of the ptp header are not tested for pur- pose of ingress time insertion. the packet is modified as follows: ? the four bytes of nanoseconds are stored at an offset from the start of the ptp header the offset is specified in rx ptp insert timestamp offset (rx_ptp_insert_ts_offset[5:0]) field in the 1588 port x rx timestamp insertion configurat ion register (1588_rx_ts_insert_config_x) . the lowest two bits of the seconds are stor ed into the upper 2 bits of the nanoseconds. ? if also enabled, bits 3:0 of the seconds are stored into bits 3:0 of a reserved byte in the ptp header. bits 7:4 are set to zero. the offset of this reserved byte is specified by the rx ptp insert timestamp seconds offset (rx_pt- p_insert_ts_sec_offset[5:0]) field in the 1588 port x rx timestamp inse rtion configuration register (1588_rx_ts_insert_config_x) . note: for version 2 of ieee 1588, the four reserved byte s starting at offset 16 should be used for the nanosec- onds. the reserved byte at offset 5 should be used for the seconds.
-page 368 ? 2015 microchip technology inc. delay request egress time insertion into delay reponse packet normally, in ordinary clock operation, the egress times of transmitted delay_req packets are saved and read by the host s/w. to avoid the need to read these timestamps via register access, the egress time of the last transmitted delay_req packet on the port can be inserted into delay_resp packets received on the port. this function is enabled via the rx ptp insert delay request egress in delay response enable (rx_pt- p_insert_dreq_dresp_en) bit in the 1588 port x rx timestamp insertion configuration register (1588_rx- _ts_insert_config_x) . as with any ingress time insertion, de lay_resp messages must be enable in the 1588 port x rx timestamp configu- ration register (1588_rx_timestamp_config_x) and the rx ptp insert timestamp enable (rx_pt- p_insert_ts_en) must be set. note: inserting the delay request egress time into the packet is an additional, separately enabled, feature verses the egress time recording described above. as with ingress time insertion into packets , above: ? the versionptp field of the ptp header is checked a nd the domainnumber field and al ternatemasterflag in the flagfield of the ptp header are not checked. note: support for the ieee 1588 -2002 (v1) packet format is not provided. ? the four bytes of nanoseconds / 2 bits of seconds are stored at the specified offset of the ptp header. ? bits 3:0 of the seconds are stored at the sp ecified offset in the ptp header, if enabled. effectively, this function is the same as the ingress time insertion into packets except that the egress time of the delay_req is inserted instead of the ingress time of the delay_resp. ingress correction field r esidence time adjustment in order to support one-step transparent clock operation, the residence time dela y through the device is accounted for by adjusting the correctionfield of certain packets. this function is enabled per ptp message type via the rx ptp correction field message type enable (rx_pt- p_cf_msg_en[15:0]) bits in the 1588 port x rx correction field modification register (1588_rx_cf_mod_x) . typ- ically the sync message is enabled for both end-to-end and peer-to-peer transpare nt clocks, the delay_req, pdelay_req and pdelay_resp messages are enabled only for end-to-end transparent clocks. following the determination of packet fo rmat and qualification of the packet as a ptp message above, the ptp header is checked. ? the versionptp field of the ptp header is checked against the rx ptp version (rx_ptp_version[3:0]) field in the 1588 port x rx timestamp configuration register (1588_rx_timestamp_config_x) . only those mes- sages with a matching version will be have their correctio n field modified. a setting of 0 allows any ptp version. note: support for the ieee 1588 -2002 (v1) packet format is not provided. note: the domainnumber field and alternatemasterflag in the flagfield of the ptp header are not tested for pur- pose of correction field modification. the correctionfield is modified as follows: note: if the original correctionfield contains a val ue of 0x7fffffffffffffff, it is not modified. if adjustment to the correctionfield would result in a value that is larger than 0x7fffffffffffffff, that value is used instead. ?for sync packets, the value of the rx peer delay (rx_peer_delay[15:0]) field in the 1588 port x asymmetry and peer delay regist er (1588_asym_peerdly_x) (for the particular ingress port) is added to the correction- field. this function is used for one-step peer-to-peer transparen t clocks. if peer-to-peer transparent clock mode is not being used, the register should be set to zero. if one-st ep transparent clock mode is not being used, correction field modifications would not be enabled for sync messages. ?for sync and pdelay_resp packets, the value of the port delay asymmetry (delay_asym[15:0]) field in the 1588 port x asymmetry and peer de lay register (1588_asym_peerdly_x) (for the particular ingress port) is added to the correctionfield.
? 2015 microchip technology inc. -page 369 this function is used for o ne-step transparent clocks. if one-step end-to-end transparen t clock mode is not being used, correction field modifications would not be enabl ed for pdelay_resp messages. if one-step transparent clock mode is not being used, correction field modificati ons would not be enabled for sync or pdelay_resp mes- sages. ? the nanoseconds portion of the ingress time are subtracted from the correctionfield. ? bits 3:0 of the seconds portion of the ingress time are in serted into bits 3:0 of a reserved byte in the ptp header. bit 7 is set to a one as an indication to the transmitter that residence time correction is being done. bits 6:4 are set to zero. the offset of this reserved byte is specified by the rx ptp insert timestamp seconds offset (rx_pt- p_insert_ts_sec_offset[5:0]) field in the 1588 port x rx timestamp inse rtion configuration register (1588_rx_ts_insert_config_x) . note: proper operation of the transmitter portion of the corre ction field residence time adjustment requires that the reserved byte resides after the versionptp field and before the correctionfield. for version 2 of ieee 15 88, the reserved byte at offset 5 should be used for the seconds. note: since the modification of the packet occurs on ingress, any packets that are forwarded to the host software will also have the ingress time subtracted from the orig inal correctionfield. if nec essary, the original correc- tionfield can be reconstructed by adding the ingress time. frame updating frames are modified even if their original fcs or udp checksum is invalid. ? for ipv4, the udp checksum is set to 0. if the original udp checksum was invalid, a receive symbol error is forced and the 1588 port x rx checksum dropped count register (1588 _rx_chksum_dropped_cnt_x) incremented. this can be disabled by the rx ptp bad udp checksum force erro r disable (rx_ptp_bad_udp_chksum_- force_err_dis) field in the 1588 port x rx timestamp inserti on configuration register (1588_rx- _ts_insert_config_x) . note: an original udp checksum value of 0x0000 indica tes that the checksum is no t included and is considered a pass. note: the original udp checksum is calculated over the ent ire udp payload as indicated by the udp length field and not the assumed ptp packet length. note: the original udp checksum ca lculation does not included layer 2 pad bytes, if any. ? for ipv6, the two bytes beyond the end of the ptp messa ge are modified so that th e original udp checksum is correct for the modified payload. these bytes are updated by accumulating the differences between the original frame data and the substituted data usin g the mechanism defined in ietf rfc 1624. if the original udp checksum was invalid, a receive symbol error is forced and the 1588 port x rx checksum dropped count register (1588 _rx_chksum_dropped_cnt_x) incremented. this can be disabled by the rx ptp bad udp checksum force erro r disable (rx_ptp_bad_udp_chksum_- force_err_dis) field in the 1588 port x rx timestamp inserti on configuration register (1588_rx- _ts_insert_config_x) . note: since the two bytes beyond the end of the ptp messa ge are modified based on the differences between the original frame da ta and the substituted data, an invalid incoming checksum would always result in an outgoing checksum error. note: an original udp checksum value of 0x0000 is invalid and is considered a fail. note: for ipv6, the udp checksum calculatio n includes the ipv6 ps eudo header. pa rt of the ipv6 pseudo header is the final ipv6 destination address. if the ipv6 packet does not contain a routing header, t hen the final ipv6 destination address is the destina- tion address contained in the ipv6 header.
-page 370 ? 2015 microchip technology inc. if the ipv6 packet does contain a routing header, then the final ipv6 destination address is the address in the last element of the routing header. note: the original udp checksum is calculated over the ent ire udp payload as indicated by the udp length field and not the assumed ptp packet length. note: the original udp checksum ca lculation does not included layer 2 pad bytes, if any. note: the two bytes beyond the end of the ptp message are located by using the messagelength field from the ptp header. ? the frame fcs is recomputed. if the original fcs was invalid, a bad fcs is forced. ? if the frame has a receive symbol error(s), a receive symbol error indication will be propagated at the same nibble location(s). note: fcs and udp checksums are only up dated if the frame was actually m odified. if no modifications are done, the existing fcs and checksums are left unchanged. 15.2.1.5 ingress me ssage filtering ptp messages can be filtered upon receive. following the det ermination of packet format and qualification of the packet as a ptp message above, the ptp header is checked for any of the following. ? the messagetype field of the ptp header is checked and those messages that have their rx ptp message type filter enable (rx_pt p_msg_fltr_en[15:0]) bits in the 1588 port x rx filter conf iguration register (1588_rx- _filter_config_x) set will be filtered. typically delay_req and delay_resp messages are filtered in peer-to- peer transparent clocks. ? the versionptp field of the ptp header is checked against the rx ptp version (rx_ptp_version[3:0]) field in the 1588 port x rx timestamp configuration register (1588_rx_timestamp_config_x) . if the rx ptp ver- sion filter enable (rx_ptp_version_fltr_en) bit in the 1588 port x rx filter configuration register (1588_rx_filter_config_x) is set, messages with a non-matching version will be filtered. a version setting of 0 allows any ptp version and would not cause filtering. note: support for the ieee 1588 -2002 (v1) packet format is not provided. ? if enabled via the rx ptp domain filter enab le (rx_ptp_domain_fltr_en) bit in the 1588 port x rx filter configuration register (1588_rx_filter_config_x) , messages whose domainnumber field in the ptp header does not match the rx ptp domain (rx_ptp_domain[7:0]) value in the 1588 port x rx timestamp configura- tion register (1588_rx_timestamp_config_x) will be filtered. ? if enabled via the rx ptp alternate master filter e nable (rx_ptp_alt_master_fltr_en) bit in the 1588 port x rx filter configuration regi ster (1588_rx_filter_config_x) , messages whose alternatemasterflag in the flagfield of the ptp header is set will be filtered. at the end of the frame, the frame?s fc s and the udp checksum (for ipv4 and ipv6 formats) are verified. fcs checking can be disabled using the rx ptp fcs check dis able (rx_ptp_fcs_dis) bit in the 1588 port x rx timestamp con- figuration register (1588_rx_timestamp_config_x) . udp checksum checking c an be disabled using the rx ptp udp checksum check disable (rx_ptp_udp_chksum_dis) bit in the same register. note: a ipv4 udp checksum value of 0x00 00 indicates that the checksum is not included and is considered a pass. a ipv6 udp checksum value of 0x0000 is invalid and is considered a fail. note: for ipv6, the udp checksum calculatio n includes the ipv6 pseudo heade r. part of the ipv6 pseudo header is the final ipv6 destination address. if the ipv6 packet does not contain a routing header, t hen the final ipv6 destination address is the destina- tion address contained in the ipv6 header. if the ipv6 packet does contain a routing header, then the final ipv6 destination address is the address in the last element of the routing header. note: the udp checksum is calculated over the entire udp payload as indicat ed by the udp length field and not the assumed ptp packet length. note: the udp checksum calculation does not included layer 2 pad bytes, if any. if the fcs and checksum tests pass, the frame is fi ltered by inserting a receive symbol error and the 1588 port x rx filtered count register (1588_rx_filtered_cnt_x) is incremented.
? 2015 microchip technology inc. -page 371 note: the mac will count this as an errored packet. note: message filtering is an additional, separately enabled , feature verses any packet ingress time recording and packet modification. although these functions typically would not be used together on the same message type. 15.2.2 transmit frame processing 15.2.2.1 egress time snapshot for each ethernet frame, the transmit frame processing det ects the sfd field of the frame and temporarily saves the current 1588 clock value. egress latency the egress latency is the amount of time between the point when the 1588 clock value is internally captured and the start of the frame?s first symbol after the sfd on the network medium. it is specified by the tx latency (tx_la- tency[15:0]) field in the 1588 port x latency register (1588_latency_x) and is added to the 1588 clock value at the detection of the sfd. the setting is used to adjust t he internally captured 1588 clock value such that the resultant timestamp more accurately co rresponds to the start of the frame?s first symbol after the sfd on the network medium. the egress latency consists of the transmit latency of the ph y, whether internal or external and the latency of the 1588 frame detection circuitry. the value depends on the port mode. typical values are: ? 100base-tx: 95ns ? 100base-fx: 68ns plus the transmit latency of the fiber transceiver ? 10base-t: 1139ns ? 100mbps rmii: 20ns plus any external transmit latency ? 10mbps rmii: 20ns plus any external transmit latency 15.2.2.2 1588 transmit parsing the 1588 transmit parsing block parses the outgoing frame to identify 1588 ptp messages. note: support for the ieee 1588 -2002 (v1) packet format is not provided. the transmit parsing block may be programmed to detect ptp messages encoded in udp/ipv4, udp/ipv6 and layer 2 ethernet formats via the tx ipv4 enable (tx_ipv4_en) , tx ipv6 enable (tx_ipv6_en) and tx layer 2 enable (tx_layer2_en) bits in the 1588 port x tx parsing configurat ion register (1588_tx_parse_config_x) . vlan tagged and non-vlan tagged frame formats are support ed. multiple vlan tags are handled as long as they all use the standard type of 0x8100. both ethernet ii (type fiel d) and 802.3 (length field) w/ snap frame formats are sup- ported. the following tests are made to determine that the packet is a ptp message. ? mac destination address checking is enabled via the tx mac address enable (tx_mac_addr_en) in the 1588 port x tx parsing configuratio n register (1588_tx_parse_config_x) . for the layer 2 message format, the addresses of 01:1 b:19:00:00:00 or 01:80:c2: 00:00:0e may be enabled via the 1588 port x tx parsing configuration register (1588_tx_parse_config_x) . either address is allowed for peer delay and non-peer delay messages. for ipv4/udp messages, any of the iana assigned multicast ip destination addresses for ieee 1588 (224.0.1.129 and 224.0.1.130 through .132), as well as the ip destination address for the peer delay mechanism (224.0.0.107) may be enabled via the 1588 port x tx parsing configurat ion register (1588_tx_parse_con- fig_x) . these ip addresses map to the 802.3 mac addresses of 01:00:5e: 00:01:81 through 01:00:5e:00:01:84 and 01:00:5e:00:00:6b. any of these addresses are allowed for p eer delay and non-peer delay messages. for ipv6/udp messages, any of the iana assigned multicast ip destination addresses for ieee 1588 (ff0x:0:0:0:0:0:0:181 and ff0x:0:0:0:0:0:0:182 through : 184), as well as the ip destination address for the peer delay mechanism (ff02:0:0:0:0: 0:0:6b) may be enabled via the 1588 port x tx parsing configuration register (1588_tx_parse_config_x) . these ip addresses map to the 802. 3 mac addresses of 33:33:00:00:01:81 through 33:33:00:00:01: 84 and 33:33:00:00:00:6b. any of these addr esses are allowed for peer delay and non- peer delay messages. a user defined mac address defined in the 1588 user mac address high-word register (1588_us-
-page 372 ? 2015 microchip technology inc. er_mac_hi) and the 1588 user mac address low-dwo rd register (1588_user_mac_lo) may also be indi- vidually enabled for the above formats. ? if the type / length field indicates an ethertype then for the layer 2 message format, the ethertype must equal 0x88f7. for ipv4/udp messages, the ethertype must equal 0x0800. for ipv6/udp messages, the ethertype must equal 0x86dd. ? if the type / length field indicates a length and the next 3 bytes equal 0xaaaa03 (indicating that a snap header is present) and the snap header has a oui equal to 0x000000 then for the layer 2 message format, the ethertype in the snap header must equal 0x88f7. for ipv4/udp messages, the ethertype in the snap header must equal 0x0800. for ipv6/udp messages, the ethertype in the snap header must equal 0x86dd. ? for ipv4/udp messages, the version field in the ipv4 hea der must equal 4, the ihl field must be 5 and the proto- col field must equal 17 (udp) or 51 (a h). ipv4 options are not supported. ? for ipv6/udp messages, the version field in the ipv6 hea der must equal 6 and the next header field must equal 17 (udp) or one of the ipv6 extension header values (0 - hop-by-hop options, 60 - destination options, 43 - routing, 44 - fragment, 51 - authentication header (ah) ? for ipv4/udp messages, destination ip address checking is enabled via the tx ip address enable (tx_ip_ad- dr_en) in the 1588 port x tx parsing configurati on register (1588_tx_parse_config_x) . any of the iana assigned multicast ip destination addresses for ieee 1588 ( 224.0.1.129 and 224.0.1.130 through .132), as well as the ip destination address for the peer delay mechanism (224.0.0.107) may be enabled via the 1588 port x tx parsing configuration register (1588_tx_parse_config_x) . any of these addresses are allowed for peer delay and non-peer delay messages. ? for ipv6/udp messages, destination ip address checking is enabled via the tx ip address enable (tx_ip_ad- dr_en) in the 1588 port x tx parsing configurati on register (1588_tx_parse_config_x) . any of the iana assigned multicast ip destination addresses for ieee 1588 (ff0x:0:0:0:0:0:0:181 and ff0x:0:0:0:0:0:0:182 through :184), as well as the ip destination address for the peer delay mechanism (f f02:0:0:0:0:0:0:6b) may be enabled via the 1588 port x tx parsing configurat ion register (1588_tx_parse_config_x) . any of these addresses are allowed for peer delay and non-peer delay messages. ? for ipv4/udp if the protocol field in the fixed header wa s 51 (ah), the next header field is checked for 17 (udp) and the ah header is skipped. ? for ipv6/udp if the next header field in the fixed hea der was one of the ipv6 extens ion header values, the next header field in the extension header is checked for 17 (udp) or one of the ipv6 extension header values. if it is one of the ipv6 extension header values, the process repeats until either a value of 17 (udp) or a value of 59 (no next header) are found or the packet ends. 15.2.2.3 transmit messa ge egress time recording following the determination of packet fo rmat and qualification of the packet as a ptp message above, the ptp header is checked for all of the following. ? the messagetype field of the ptp header is c hecked and only those messages enabled via the tx ptp message type enable (tx_pt p_message_en[15:0]) bits in the 1588 port x tx timestamp configuration register (1588_tx_timestamp_config_x) will be have their egress times saved. typically sync, delay_req, pde- lay_req and pdelay_resp messages are enabled. ? the versionptp field of the pt p header is checked against the tx ptp version (tx_ptp_version[3:0]) field in the 1588 port x tx timestamp configuration register (1588_tx_timestamp_config_x) . only those mes- sages with a matching version will be have their egre ss times saved. a setting of 0 allows any ptp version. note: support for the ieee 1588-2002 (v1) packet format is not provided. ? if enabled via the tx ptp domain match enable (tx_ptp_domain_en) bit in the 1588 port x tx timestamp configuration register ( 1588_tx_timestamp_config_x) , the domainnumber field of the ptp header is checked against the tx ptp domain (tx_ptp_domain[7:0]) value in the same register. only those messages with a matching domain will be have their egress times saved. ? if enabled via the tx ptp alternate master e nable (tx_ptp_ alt_master_en) bit in the 1588 port x tx time-
? 2015 microchip technology inc. -page 373 stamp configuration register (1588_tx_timestamp_config_x) , the alternatemasterflag in the flagfield of the ptp header is checked and only those messages with an alternatemasterflag set to 0 will be have their egress times saved. at the end of the frame, the frame?s fc s and the udp checksum (for ipv4 and ipv6 formats) are verified. fcs checking can be disabled using the tx ptp fcs check dis able (tx_ptp_fcs_dis) bit in the 1588 port x tx timestamp con- figuration register (1588 _tx_timestamp_config_x) . udp checksum checking can be disabled using the tx ptp udp checksum check disable (tx_ptp_udp_chksum_dis) bit in the same register. note: a ipv4 udp checksum value of 0x00 00 indicates that the checksum is not included and is considered a pass. a ipv6 udp checksum value of 0x0000 is invalid and is considered a fail. note: for ipv6, the udp checksum calculatio n includes the ipv6 ps eudo header. pa rt of the ipv6 pseudo header is the final ipv6 destination address. if the ipv6 packet does not contain a routing header, t hen the final ipv6 destination address is the destina- tion address contained in the ipv6 header. if the ipv6 packet does contain a routing header, then the final ipv6 destination address is the address in the last element of the routing header. note: the udp checksum is calculated over the entire udp payload as indicat ed by the udp length field and not the assumed ptp packet length. note: the udp checksum calculation does not included layer 2 pad bytes, if any. if the fcs and checksum tests pass: ? the latency adjusted, 1588 clock value, saved above at the start of the frame, is recorded into the 1588 port x tx egress time seconds register (1588_tx_egress_sec_x) and 1588 port x tx egress time nanoseconds register (1588_tx_egress_ns_x) . ? the messagetype and sequenceid fields and 12-bit crc of t he portidentity field of the ptp header are recorded into the message type (msg_type) , sequence id (seq_id) and source port identity crc (src_prt_crc) fields of the 1588 port x tx message header register (1588_tx_msg_header_x) . the 12-bit crc of the portidentity field is created by using the polynomial of x 12 + x 11 + x 3 + x 2 + x + 1. ? the corresponding maskable 1588 tx timestamp interrupt (1588_tx_ts_int[2:0]) is set in the 1588 interrupt status register (1588_int_sts) . up to four transmit events are saved per port with the count shown in the 1588 tx timestamp count (1588_tx- _ts_cnt[2:0]) field in the 1588 port x capture information register (1588_cap_info_x) . additional events are not recorded. when the appropriate 1588 tx timestamp interrupt (1588_tx_ts_int[2:0]) bit is written as a one to clear, 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) will decrement. if there are remain ing events, the capture registers will update to the next event and the interrupt will set again. time stamps from forwarded packets the transmitter will also save egress times for frames that are forwarded from another port. typically, these are of no use to the host s/w and would need to be discarded. sinc e these messages also typically have their correction field adjusted for residence time, they can be di stinguished from messages from the host. if egress correction field r esidence time adjustment , below, is performed on a message, egress times are not saved if the tx ptp suppress timestamps when corre ction field adjusted (tx_ptp_supp_cf_ts) bit in the 1588 port x tx modification register (1588_tx_mod_x) is set. delay_req egress time saving normally, in ordinary clock operation, the egress time of transmitted delay_req packets are saved and read by the host s/w. to avoid the need to read these timestamps via register access, the egress time of the last transmitted delay_req packet on the port can be inserted into delay_resp packets received on the port. the 1588 port x tx delay_req egress time seconds register (1588_tx_dreq_sec_x) and the 1588 port x tx delay_req egress time nanoseconds register (1588_tx_dreq_ns_x) hold the egress time of the delay_req mes- sage. these registers are updated by the h/w when the delay_req message is transmitted independent of the settings in the tx ptp message type enable (tx_ptp_message_en[15:0]) bits. as above (including all applicable notes):
-page 374 ? 2015 microchip technology inc. ? the versionptp and domainnumber fields and alternat emasterflag in the flagfield of the ptp header are checked, if enabled. note: support for the ieee 1588 -2002 (v1) packet format is not provided. ? at the end of the frame, the frame?s fcs and the udp ch ecksum (for ipv4 and ipv6 formats) are verified, if enabled. if all tests pass, then the delay_req message information is updated and available for the receive function. 15.2.2.4 egress packet modifications modifications to frames on egress are divided into two cat egories, those to support one-st ep transparent clock residence time corrections and those to support one-s tep operations from the host software. bit 7 of the ptp header?s reserved byte (the byte which is also used to hold the ingress time seconds) is used to indicate packets that need to have their correction field adjusted for resi dence time. this bit is set on ingress when the correction field adjustment process is started. when bit 7 of the ptp header?s reserved byte is cleared, th e alternate function, if any, for the message type is to be performed, if it is enabled. the host s/w should normally have bit 7 cleared. note: the offset of the reserved byte is specified by the tx ptp 1 reserved byte offset (tx_pt p_1_rsvd_off- set[5:0]) field in the 1588 port x tx modification register (1588_tx_mod_x) . proper operation of the transmitter re quires that the reserved byte resides after the versionptp field and before the correctionfield. for version 2 of ieee 1588, the reserved byte at offset 5 should be used. egress correction field r esidence time adjustment in order to support one-step transparent clock operation, the residence time dela y through the device is accounted for by adjusting the correctionfield of certain packets. this function is enabled per ptp message type via the tx ptp correction field message type enable (tx_pt- p_cf_msg_en[15:0]) bits in the 1588 port x tx modification register (1588_tx_mod_x) . typically the sync message is enabled for both end-to-end and peer-to-peer transparent clocks, the delay_req, pde- lay_req and pdelay_resp messages are enabled only for end-to-end transparent clocks. as described above, messages from t he host s/w would normally have bit 7 of the ptp header?s reserved byte clear and are not modified in this manner. typically, bit 7 is only set on ingress when the correction field adjustment process is started. note: the host s/w should normally keep bit 7 of the ptp header?s reserved byte clear for sync, delay_req, pdelay_req and pdelay_resp messages so that residence time adjustment is not performed. following the determination of packet fo rmat and qualification of the packet as a ptp message above, the ptp header is checked. ? the versionptp field of the pt p header is checked against the tx ptp version (tx_ptp_version[3:0]) field in the 1588 port x tx timestamp configuration register (1588_tx_timestamp_config_x) . only those mes- sages with a matching version will have their correction field modified. a setting of 0 allows any ptp version. note: support for the ieee 1588 -2002 (v1) packet format is not provided. note: the domainnumber field and alternatemasterflag in the flagfield of the ptp header are not tested for pur- pose of correction field modification. the correctionfield is modified as follows: note: if the original correctionfield contains a val ue of 0x7fffffffffffffff, it is not modified. if adjustment to the correctionfield would result in a value that is larger than 0x7fffffffffffffff, that value is used instead. ?for delay_req and pdelay_req packets, the value of the port delay asymmetry (delay_asym[15:0]) field in the 1588 port x asymmetry and peer de lay register (1588_asym_peerdly_x) (for the particular egress port) is subtracted from the correctionfield. this function is used for one-step end-to-end tr ansparent clocks. if o ne-step end-to-end transparent clock mode is
? 2015 microchip technology inc. -page 375 not being used, correction field modifications would no t be enabled for delay_req and pdelay_req messages. ? the nanoseconds portion of the egress time are added to the correctionfield. ? in order to detect and correct for a potential rollover of the nanoseconds portion the clock, egress seconds bits 3:0 minus ingress seconds bits 3:0 (without borrow) is added to the correctionfield. the ingress time is available in bits 3:0 of a reserved byte in the ptp header. note: the offset of the reserved byte is specified by the tx ptp 1 reserved byte offset (tx_pt p_1_rsvd_off- set[5:0]) field in the 1588 port x tx modification register (1588_tx_mod_x) . proper operation of the transmitter re quires that the reserved byte resides after the versionptp field and before the correctionfield. for version 2 of ieee 1588, the reserved byte at offset 5 should be used. egress time insertion - sync message alernate function while functioning as an ordinary clock master, one-step tran smission of sync messages from the host s/w requires the actual egress time to be inserted into the ten byte, origin timestamp field. the 32-bit nanoseconds portion and the lower 32 bits of the seconds portion come from the latency adjust ed, 1588 clock value, saved above at the start of the frame. the upper 16 bits of seconds are taken from the 1588 tx one-step sync upper se conds register (1588_tx_one_- step_sync_sec) . the host software is responsible for maintaining this register if required. note: inserting the egress time into the packet is an additional, separately enabled, feature verses the egress time recording described above. this function is enabled via the tx ptp sync message egress time insertion (tx_ptp_sync_ts_insert) bit in the 1588 port x tx modification register (1588_tx_mod_x) and is used only on frames which have bit 7 of the ptp header?s reserved byte cleared. note: the offset of the reserved byte is specified by the tx ptp 1 reserved byte offset (tx_pt p_1_rsvd_off- set[5:0]) field in the 1588 port x tx modification register (1588_tx_mod_x) . proper operation of the transmitter re quires that the reserved byte resides after the versionptp field and before the correctionfield. for version 2 of ieee 1588, the reserved byte at offset 5 should be used. following the determination of packet fo rmat and qualification of the packet as a ptp message above, the ptp header is checked. ? the versionptp field of the pt p header is checked against the tx ptp version (tx_ptp_version[3:0]) field in the 1588 port x tx timestamp configuration register (1588_tx_timestamp_config_x) . only those mes- sages with a matching version will have their egress ti me inserted. a setting of 0 allows any ptp version. note: the domainnumber field and alternatemasterflag in the flagfield of the ptp header are not tested. note: support for the ieee 1588 -2002 (v1) packet format is not provided. egress correction field turnaround time adjustment - pdelay_resp message alternate function one-step pdelay_resp messages sent by t he host, require their correctionfield to be calculated on-the-fly to include the turnaround time between the ingress of the p delay_req and the egress time of the pdelay_resp. pdelay_resp.cf = pdelay_req.cf + pdelay_resp.egress time - pdelay_req.ingress time. note: adjusting the correction field in the packet is an addi tional, separately enabled, feature verses the egress time recording described above. note: if the original correctionfield contains a va lue of 7fffffffffffffff, it is not modified. if adjustment to the correctionfield would result in a value that is larger than 7fffffffffffffff, that value is used instead. the 1588 port x rx pdelay_req ingress time seconds register (1588_rx_pdreq_sec_x) and the 1588 port x rx pdelay_req ingress time nanosecon ds register (1588_rx_pdreq_ns_x) hold the ingress time of the pdelay_req message.
-page 376 ? 2015 microchip technology inc. the 1588 port x rx pdelay_req ingress correction field high register (1588_rx_pdreq_cf_hi_x) and the 1588 port x rx pdelay_req ingress correction field low register (1588_rx_pdreq_cf_low_x) hold the correctionfield of the pdelay_req message. these registers are set by s/w prior to sending the pd elay_resp message or by th e automatic updating described above in pdelay_req ingress time saving . the egress time is the latency adjusted, 1588 clock valu e, saved above at the start of the pdelay_resp frame. note: since only four bits worth of seconds of the pdelay_r eq ingress time are stored, the host must send the pdelay_resp within 16 seconds. this function is enabled via the tx ptp pdelay_resp message turnaround time insertion (tx_ptp_pdre- sp_ta_insert) bit in the 1588 port x tx modification register (1588_tx_mod_x) and is used only on frames which have bit 7 of the ptp header?s reserved byte cleared. as with egress time insertion above: ? the versionptp field of the ptp header is checked a nd the domainnumber field and al ternatemasterflag in the flagfield of the ptp header are not checked note: support for the ieee 1588 -2002 (v1) packet format is not provided. clearing reserved fields if the frame is modified on egress for co rrection field residence time adjustment: ? the reserved byte at the location specified by the tx ptp 1 reserved byte of fset (tx_ptp_ 1_rsvd_off- set[5:0]) is cleared. ? the four reserved bytes used for ingress time insertion into packets are cleared if the tx ptp clear four byte reserved field (tx_ptp_clr_4_rsvrd) bits in the 1588 port x tx modification register (1588_tx- _mod_x) is set. note: the offset of the four reserved bytes is specified in tx ptp 4 reserved byte s offset (tx_ptp_4_rs- vd_offset[5:0]) . frame updating frames are modified even if their original fcs or udp checksum is invalid. ? for ipv4, the udp checksum is set to 0 under the following conditions. if the tx ptp clear udp/ipv4 checksum enable (tx_ptp_cl r_udpv4_chksum) bit in the 1588 port x tx modification register 2 (1588_tx_mod2_x) is set, the udp checksum is set to 0 for sync messages if sync egress time insertion is enabled and for pdelay_resp messages if pdelay_resp correction field turnaround time adjustment is enabled. the ptp_version field is also checked. ? when residence time correction is performed, the udp checksum is alre ady set to 0 by the ingress port. ? for ipv6, the two bytes beyond the end of the ptp message are modified to correct for the udp checksum. these bytes are updated by accumulating the differences between the original frame data and the substituted data using the mechanism defined in ietf rfc 1624. the existing two bytes are included in the calculation and are updated. it is assumed that the original udp checksum is valid and is not checked. note: since the two bytes beyond the end of the ptp messa ge are modified based on the differences between the original frame data and the substituted data, an in valid incoming checksum wo uld result in an outgoing checksum error. note: the two bytes beyond the end of the ptp message are located by using the messagelength field from the ptp header. ? the frame fcs is recomputed it is assumed that the original fcs is valid and is not checked. ? if the frame has a transmit symbol error(s), a transmit sym bol error indication will be propagated at the same nib- ble location(s) note: the fcs and ipv6/udp checksum are updated and the reserved byte clear ed only if the frame was actually modified. the ipv4/udp checksum is cleared as indicated above and could be the only modification in the message.
? 2015 microchip technology inc. -page 377 if the ipv4/udp checksum is cl eared, the fcs is recomputed. if no modifications are done, the existing fcs, checksums and reserved bytes are left unchanged. 15.3 1588 clock the tunable 1588 clock is the time source for all ptp related functions of the device. the block diagram is shown in figure 15-1 . the 1588 clock consists of a 32-bit wide seconds portion and a 30-bit wide nanoseconds portion. running at a nominal reference frequency of 100mhz, the nanoseconds portion is normally incremented by a value of 10 every reference clock period. upon reaching or exceeding its maximum value of 10^9, the nanoseconds portion rolls over to or past zero and the seconds portion is incremented. the 1588 clock can be read by setting the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) . this saves the current value of the 1588 clock into the 1588 clock seconds register (1588_clock_sec) , 1588 clock nanoseconds register (1588_clock_ns) and 1588 clock sub-nanoseconds register (1588_clock_subns) where it can be read. although the ieee 1588-2008 specification calls for a 48-bit se conds counter, the hardware only supports 32 bits. for purposes of event timestamping, residence time correction or other comparisons, the 136 year rollover time of 32 bits is sufficient. rollover can be detected and corrected by compar ing the two values of interest. to support one-step oper- ations, the device can insert the egress timestamp into th e origin timestamp field of sync messages. however, the host must maintain the 1588 tx one-step sync upper seconds register (1588_tx_one_step_sync_sec) . the host should avoid sending a sync message if there is a possibility t hat the 32-bit seconds counter will reach its rollover value before the message is transmitted. a 32-bit sub-nanoseconds counter is used to precisely tune t he rate of the 1588 clock by accounting for the difference between the nominal 10ns and the actual rate of the master clock. every re ference clock period the sub-nanoseconds counter is incremented by the clock rate adjustment value (1588_clock_rate_adj_value) in the 1588 clock rate adjustment register (1588_clock_rate_adj) , specified in 2 -32 nanoseconds. when the sub-nanoseconds counter rolls over past zero, the nanoseconds portion of th e 1588 clock is incremented by 9 or 11 instead of the normal figure 15-1: 1588 clock block diagram ieee 1588 clock carry 32 bit seconds + 9, 10, 11 inc 30 bit nanoseconds 32 bit subnanoseconds + 30 bit rate adjustment carry + / - + step value host 30 bit temp rate adjustment 32 bit temp rate duration
-page 378 ? 2015 microchip technology inc. value of 10. the choice to speed up or slow down is determined by the clock rate adjustment direction (1588_clock_rate_adj_dir) bit. the ability to adjust for 1 ns approximately every 43 seconds allows for a tuning precision of approximately 2.3 -9 percent. the maximum adjustment is 1 n s every 4 clocks (40 ns) or 2.5 percent. in addition to adjusting the frequency of the 1588 clock, the host may directly set the 1588 clock, make a one-time step adjustment of the 1588 clock or specify a temporary rate. the choice of method depends on needed adjustment. for initial adjustments, direct or one-ti me step adjustments may be best. for on- going minor adjustments, the temporary rate adjustment may be best. ideally, the frequency will be matc hed and once the 1588 clock is synchronized, no further adjustments would be needed. in order to perform a direct writing of the 1588 clock, the desired value is written into the 1588 clock seconds register (1588_clock_sec) , 1588 clock nanoseconds register (1588_clock_ns) and 1588 clock sub-nanoseconds register (1588_clock_subns) . the clock load (1588_clock_load) bit in the 1588 command and control reg- ister (1588_cmd_ctl) is then set. in order to perform a one-time positive or negative adjus tment to the seconds portion of the 1588 clock, the desired change and direction are written into the 1588 clock step adjustment register (1588_clock_step_adj) . the clock step seconds (1588_clock_step_seconds) bit in the 1588 command and control register (1588_cmd_ctl) is then set. the internal sub-nanoseconds counter and the nanos econds portion of the 1588 cl ock are not affected. if a nanoseconds portion rollover coincides with the 1588 clock adjustment, the 1588 clock adjustment is applied in addi- tion to the seconds increment. in order to perform a one-time positiv e adjustment to the nanoseconds portion of the 1588 clock, the desired change is written into the 1588 clock step adjustment r egister (1588_clock_step_adj) . the clock step nanoseconds (1588_clock_step_nanoseconds) bit in the 1588 command and control register (1588_cmd_ctl) is then set. if the addition to the nanoseconds portion results in a rollover past zero, then the seconds portion of the 1588 clock is incremented. the normal (9, 10 or 11 ns) increment to th e nanoseconds portion is suppressed for one clock. this can be compensated for by specifying an addition value 10ns higher. a side benefit is that using an addition value of 0 effec- tively pauses the 1588 clock for 10ns while a value less than 10 slows the clock down just briefly. the internal sub- nanoseconds counter of the 1588 clock is not affected by the adjustment, however, if a sub-nanoseconds counter roll- over coincides with the 1588 clock adjustment it will be missed. in order to perform a temporary rate adjus tment of the 1588 clock, the desired te mporary rate and direction are written into the 1588 clock temporary rate adjustment register (1588_clock_temp_rate_adj) and the duration of the temporary rate, specified in referenc e clock cycles, is written into the 1588 clock temporary rate duration register (1588_clock_temp_rate_duration) . the clock temporary rate (1588_clock_temp_rate) bit in the 1588 command and control register (1588_cmd_ctl) is then set. once the temporar y rate duration expires, the clock temporary rate (1588_clock_temp_rate) bit will self-clear and the 1588 clock rate adjustment register (1588_clock_rate_adj) will once again control the 1588 clock rate. this method of adjusting the 1588 clock may be preferred since it avoids large disc rete changes in the 1588 clock value. for a maximum setting in both the 1588 clock temporary rate adjustment register (1588_clock_temp_rate_adj) and 1588 clock temporary rate dura- tion register (1588_clock_temp_rate_duration) , the 1588 clock can be adjusted by approximately 1 second.
? 2015 microchip technology inc. -page 379 15.4 1588 clock events the 1588 clock events block is responsible for generating and controlling all 1588 clock related events. two clock event channels, a and b, are availabl e. the block diagram is shown in figure 15-2 . for each clock event channel, a comparator compar es the 1588 clock with a clock target loaded in the 1588 clock target x seconds register (1588_clock_target_sec_x) and 1588 clock target x nanoseconds register (1588_clock_target_ns_x) . the clock target register pair requires two 32-bit write cycles, one to each half, befo re the register pair is affected. the writes may be in any order. there is a register pair for each clock event channel (a and b). the clock target can be read by setting the clock target read (1588_clock_target_read) bit in the 1588 com- mand and control register (1588_cmd_ctl) . this saves the current value of the both clock targets (a and b) into the 1588 clock target x seconds register (1588_clock_target_sec_x) and 1588 clock target x nanoseconds reg- ister (1588_clock_target_ns_x) where they can be read. when the 1588 clock reaches or passes the clock target for a clock event channel, a clock event occurs which triggers the following: ? the maskable interrupt for that clock event channel ( 1588 timer interrupt a (1588_timer_int_a) or 1588 timer interrupt b (1588_timer_int_b) ) is set in the 1588 interrupt status register (1588_int_sts) . ?the reload/add a (reload_add_a) or reload/add b (reload_add_b) bit in the 1588 general configuration register (1588_general_config) is checked to determine the new clock target behavior: ?reload_add = 1: the new clock target is loaded from the reload / add registers ( 1588 clock target x reload / add seconds register (1588_clock_target_reload_sec_x) and 1588 clock target x reload / add nanoseconds register (1588_clock_target_reload_ns_x) ). ?reload_add = 0: the clock target is incremented by the reload / add registers ( 1588 clock target x reload / add seconds register (1588_clock_target_reload_sec_x) and 1588 clock target x reload / add nanoseconds register (1588_clock_target_reload_ns_x) ). the clock target nanoseconds rolls over at 10^9 and the carry is added to the clock target seconds. the clock target reload / add register pair requires two 32-bit write cycles, one to each half, before the register pair is affected. the writes may be in any order. there is a register pair for each clock event channel (a and b). note: writing the 1588 clock may cause the interrupt event to occur if the new 1588 clock value is set equal to or greater than the current clock target. the clock target reload function (reload_add = 1) allows the host to pre-load the next trigger time in advance. the add function (reload_add = 0), allows for a automatic repeatable event. figure 15-2: 1588 cl ock event block diagram ieee 1588 clock events compare >= load / add host 1588 clock reload / add a or b clock target a or b irq flag a or b gpio events gpio clears
-page 380 ? 2015 microchip technology inc. 15.5 1588 gpios in addition to time stamping ptp packets, the 1588 clock val ue can be saved into a set of clock capture registers based on the gpio inputs. the gpio inputs can also be used to clear the 1588 clock target compare event interrupt. when configured as outputs, gpios can be used to output a signal based on an 1588 clock target compare events. note: the ieee 1588 unit supports up to 8 gpio signals. 15.5.1 1588 gpio inputs 15.5.1.1 gpio even t clock capture when the gpio pins are configur ed as inputs, and enabled with the gpio rising edge capture enable 7-0 (gpio_re_- capture_enable[7:0]) or gpio falling edge capture enable 7-0 (gpio_fe_capture_enable[7:0]) bits in the 1588 gpio capture conf iguration register (1588_gpio_cap_config) , a rising or falling edge, respectively, will cap- ture the 1588 clock into the 1588 gpio x rising edge clock seconds capture register (1588_gpio_re_- clock_sec_cap_x) and the 1588 gpio x rising edge clock nanoseconds capture register (1588_gpio_re_clock_ns_cap_x) or 1588 gpio x falling edge clock sec onds capture register (1588_gpi- o_fe_clock_sec_cap_x) and the 1588 gpio x falling edge clock nanoseconds capture register (1588_gpi- o_fe_clock_ns_cap_x) where x equals the number of the active gpio input. gpio inputs must be stable for greater than 40 ns to be recognized as capture events and are edge sensitive. the gpio inputs have a fixed capture latency of 65 ns that can be accounted for by the host driver. the gpio inputs have a capture latency uncertainty of +/-5 ns. the corresponding, mask able, interrupt flags 1588 gpio rising edge interrupt (1588_gpio_re_int[7:0]) or 1588 gpio falling edge interrupt (1588_gpio_fe_int[7:0]) in the 1588 interrupt status register (1588_int_sts) will also be set. this is in addition to the interrupts available in the general purpose i/o interrupt status and enable register (gpio_int_sts_en) . a lock enable bit is provided for each timestamp enabled gpio, lock enable gpio rising edge (lock_gpio_re) and lock enable gpio falli ng edge (lock_gpio_fe) in the 1588 gpio capture configurat ion register (1588_gpio_- cap_config) , which prevents the corresponding gpio clock captur e registers from being overwritten if the gpio interrupt in 1588 interrupt status register (1588_int_sts) is already set. 15.5.1.2 gpio timer interrupt clear the gpio inputs can also be configured to clear the 1588 timer interrupt a (1588_timer_int_a) or 1588 timer inter- rupt b (1588_timer_int_b) in the 1588 interrupt status register (1588_int_sts) by setting the corresponding enable and select bits in the 1588 general configuration register (1588_general_config) . the polarity of the gpio input is determined by the gpio interrupt/1588 polari ty 7-0 (gpio_pol[7:0]) bits in the gen- eral purpose i/o configur ation register (gpio_cfg) . gpio inputs must be active for greater than 40 ns to be recognized as interrupt clear events and are edge sensitive. 15.5.2 1588 gpio outputs upon detection of a clock target a or b compare event, the corresponding clock event channel can be configured to output a 100 ns pulse, toggle its output, or reflect its 1588 timer interrupt bit. the selection is made using the clock event channel a mode (clock_event_a) and clock event channel b mode (clock_event_b) bits of the 1588 general configuration register (1588_general_config) . a gpio pin is configured as a 1588 ev ent output by setting the corresponding 1588 gpio output enable 7-0 (1588_g- pio_oe[7:0]) bits in the general purpose i/o configur ation register (gpio_cfg) . these bits override the gpio direc- tion bits of the general purpose i/o data & direction register (gpio_data_dir) and allow for gpio output generation based on the 1588 clock target compare event. the c hoice of the event channel is controlled by the 1588 gpio chan- nel select 7-0 (gpio_ch_sel[7:0]) bits in the general purpose i/o configuration register (gpio_cfg) . note: the 1588 gpio output enable 7-0 (1588_gpio_oe[7:0]) bits do not override the gpio buffer type 7-0 (gpiobuf[7:0]) in the general purpose i/o configuration register (gpio_cfg) . the clock event polarity, which determines whether the 1588 gpio output is active high or active low, is controlled by the gpio interrupt/1588 polarity 7-0 (gpio_pol[7:0]) bits in the general purpose i/o configuration register (gpi- o_cfg) . the gpio outputs have a latency of approximately 40 ns wh en using ?100 ns pulse? or ?i nterrupt bit? modes and 30 ns when using ?toggle? mode. on chip delays contribu te an uncertainty of +/-4ns to these values.
? 2015 microchip technology inc. -page 381 15.6 software triggered clock capture as an alternative, the gpio capture r egisters can be used by host software to recorded software events by specifying the gpio register set in the 1588 manual capture select 3-0 (1588_manual_capture_sel[3:0]) and setting the 1588 manual capture (1588_manual_capture) bit in the 1588 command and control register (1588_cmd_ctl) . this also causes the corresponding bit in the 1588 interrupt status register (1588_int_sts) to set. note: the interrupts available in the general purpose i/o interrupt status and enable register (gpi- o_int_sts_en) are not set by the using this method. note: the lock enable gpio rising edge (lock_gpio_re) and lock enable gpio falling edge (lock_gpi- o_fe) bits do not apply to manual clock capture. the full set of gpio capture registers is always available regardless of the number of gpios supported by the device. 15.7 1588 interrupt the ieee 1588 unit provid es multiple interrupt conditions. these includ e timestamp indi cation on the tr ansmitter and receiver side of each port, individual gpio input timestam p interrupts, and a clock comparison event interrupts. all 1588 interrupts are located in the 1588 interrupt status register (1588_int_sts) and are fully maskable via their respective enable bits in the 1588 interrupt enable register (1588_int_en) . all 1588 interrupts are anded with their indi vidual enables and then ored, generating the 1588 interrupt event (1588_evnt) bit of the interrupt status register (int_sts) . when configured as inputs, the gpios have the added functionality of clearing the 1588 timer interrupt a (1588_tim- er_int_a) or 1588 timer interrupt b (1588_timer_int_b) bits of the 1588 interrupt status register (1588_int_sts) as described in section 15.5.1.2 . refer to section 8.0, "system interrupts," on page 67 for additional information on the device interrupts.
-page 382 ? 2015 microchip technology inc. 15.8 1588 registers this section details the directly addr essable ptp timestamp related registers. each port has a ptp timestamp block with related registers. these sets of registers are identical in functionality for each port, and thus their register descriptions have been consoli dated. in these cases, the register names will be amended with a lowercase ?x? in place of the port designation. the wildc ard ?x? should be replaced with ?0?, ?1? or ?2? respectively. for gpio related registers, the wildcard ?x? should be replaced with ?0? through ?7?. similarly, for clock compare events, the wildcard ?x? should be replaced with ?a? or ?b?. port and gpio registers share a comm on address space. port vs. gpio re gisters are selected by using the bank select (bank_sel[2:0] in the 1588 bank port gpio select re gister (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. the gpio accessed (?x?) is set by the gpio select (gpio_- sel[2:0]) field. note: the ieee 1588 unit supports 8 gpio signals. for an overview of the entire directly addressable register map, refer to section 5.0, "register map," on page 29 . table 15-1: 1588 control and status registers bank select address offset register name (symbol) na 100h 1588 command and control register (1588_cmd_ctl) na 104h 1588 general configuration register (1588_general_config) na 108h 1588 interrupt status register (1588_int_sts) na 10ch 1588 interrupt enable register (1588_int_en) na 110h 1588 clock seconds register (1588_clock_sec) na 114h 1588 clock nanoseconds register (1588_clock_ns) na 118h 1588 clock sub-nanoseconds register (1588_clock_subns) na 11ch 1588 clock rate adjustment register (1588_clock_rate_adj) na 120h 1588 clock temporary rate adjustm ent register (1588_clock_temp_rate_- adj) na 124h 1588 clock temporary rate duration register (1588_clock_temp_rate_du- ration) na 128h 1588 clock step adjustment register (1588_clock_step_adj) na 12ch 1588 clock target x seconds register (1588_clock_target_sec_x) x=a na 130h 1588 clock target x nanoseconds register (1588_clock_target_ns_x) x=a na 134h 1588 clock target x reload / add seconds register (1588_clock_target_re- load_sec_x) x=a na 138h 1588 clock target x reload / add n anoseconds register (1588_clock_tar- get_reload_ns_x) x=a na 13ch 1588 clock target x seconds register (1588_clock_target_sec_x) x=b na 140h 1588 clock target x nanoseconds register (1588_clock_target_ns_x) x=b na 144h 1588 clock target x reload / add seconds register (1588_clock_target_re- load_sec_x) x=b
? 2015 microchip technology inc. -page 383 na 148h 1588 clock target x reload / add n anoseconds register (1588_clock_tar- get_reload_ns_x) x=b na 14ch 1588 user mac address high-word register (1588_user_mac_hi) na 150h 1588 user mac address low-dword register (1588_user_mac_lo) na 154h 1588 bank port gpio select register (1588_bank_port_gpio_sel) 0 158h 1588 port x latency register (1588_latency_x) 0 15ch 1588 port x asymmetry and peer delay register (1588_asym_peerdly_x) 0 160h 1588 port x capture information register (1588_cap_info_x) 1 158h 1588 port x rx parsing configuration register (1588_rx_parse_config_x) 1 15ch 1588 port x rx timestamp configur ation register (1588_rx_timestamp_con- fig_x) 1 160h 1588 port x rx timestamp inserti on configuration register (1588_rx- _ts_insert_config_x) 1 164h 1588 port x rx correction field modification register (1588_rx_cf_mod_x) 1 168h 1588 port x rx filter configurati on register (1588_rx_filter_config_x) 1 16ch 1588 port x rx ingress time seconds register (1588_rx_ingress_sec_x) 1 170h 1588 port x rx ingress time nanoseconds register (1588_rx_ingress_ns_x) 1 174h 1588 port x rx message header register (1588_rx_msg_header_x) 1 178h 1588 port x rx pdelay_req ingress time seconds register (1588_rx_p- dreq_sec_x) 1 17ch 1588 port x rx pdelay_req ingress time nanoseconds register (1588_rx_p- dreq_ns_x) 1 180h 1588 port x rx pdelay_req ingress correction field high register (1588_rx_p- dreq_cf_hi_x) 1 184h 1588 port x rx pdelay_req ingress correction field low register (1588_rx_p- dreq_cf_low_x) 1 188h 1588 port x rx checksum dropped count register (1588_rx_chksum_- dropped_cnt_x) 1 18ch 1588 port x rx filtered count register (1588_rx_filtered_cnt_x) 2 158h 1588 port x tx parsing configuratio n register (1588_tx_parse_config_x) 2 15ch 1588 port x tx timestamp configur ation register (1588_tx_timestamp_con- fig_x) 2 164h 1588 port x tx modification register (1588_tx_mod_x) 2 168h 1588 port x tx modification register 2 (1588_tx_mod2_x) 2 16ch 1588 port x tx egress time seconds register (1588_tx_egress_sec_x) table 15-1: 1588 control and status registers (continued) bank select address offset register name (symbol)
-page 384 ? 2015 microchip technology inc. 2 170h 1588 port x tx egress time nanoseconds register (1588_tx_egress_ns_x) 2 174h 1588 port x tx message header register (1588_tx_msg_header_x) 2 178h 1588 port x tx delay_req egress time seconds register (1588_tx- _dreq_sec_x) 2 17ch 1588 port x tx delay_req egress time nanoseconds register (1588_tx- _dreq_ns_x) 2 180h 1588 tx one-step sync upper seconds register (1588_tx_one_step_syn- c_sec) 3 15ch 1588 gpio capture configuratio n register (1588_gpio_cap_config) 3 16ch 1588 gpio x rising edge clock sec onds capture register (1588_gpio_re_- clock_sec_cap_x) 3 170h 1588 gpio x rising edge clock nanoseconds capture register (1588_gpi- o_re_clock_ns_cap_x) 3 178h 1588 gpio x falling edge clock seconds capture register (1588_gpio_fe_- clock_sec_cap_x) 3 17ch 1588 gpio x falling edge clock nanoseconds capture register (1588_gpi- o_fe_clock_ns_cap_x) table 15-1: 1588 control and status registers (continued) bank select address offset register name (symbol)
? 2015 microchip technology inc. -page 385 15.8.1 1588 command and cont rol register (1588_cmd_ctl) offset: 100h size: 32 bits bank: na bits description type default 31:14 reserved ro - 13 clock target read (1 588_clock_target_read) writing a one to this bit causes the current values of both of the 1588 clock targets (a and b) to be saved into the 1588 clock target x seconds register (1588_clock_target_sec_x) and the 1588 clock target x nanosec- onds register (1588_clock_target_ns_x) so they can be read. writing a zero to this bit has no affect. wo sc 0b 12:9 1588 manual capture select 3- 0 (1588_manual_capture_sel[3:0]) these bits specify which gpio 1588 clock capture registers are used during a manual capture. bit 3 selects the rising edge (0) or falling edge (1) registers. bits 2-0 select the gpio number. note: all 8 gpio register sets are available. r/w 0000b 8 1588 manual capture (1588_manual_capture) writing a one to this bit causes the current value of the 1588 clock to be saved into the gpio 1588 clock capture registers specified above. the corresponding bit in the 1588 interrupt status register (1588_int_sts) is also set. writing a zero to this bit has no affect. wo sc 0b 7 clock temporary rate (1588_clock_temp_rate) writing a one to this bit enables the use of the temporary clock rate adjust- ment specified in the 1588 clock temporary rate adjustment register (1588_clock_temp_rate_adj) for the duration specified in the 1588 clock temporary rate duration register (1588_clock_temp_rate_du- ration) . writing a zero to this bit has no affect. wo sc 0b 6 clock step nanoseconds (1588_clock_step_nanoseconds) writing a one to this bit adds the value of the clock step adjustment value (1588_clock_step_adj_value) field in the 1588 clock step adjustment register (1588_ clock_step_adj) to the nanoseconds portion of the 1588 clock. writing a zero to this bit has no affect. wo sc 0b
-page 386 ? 2015 microchip technology inc. note 1: the default value of this field is determined by the configuration strap 1588_enable_strap . 5 clock step seconds (1588_clock_step_seconds) writing a one to this bit adds or subtracts the value of the clock step adjust- ment value (1588_clock_step_adj_value) field in the 1588 clock step adjustment register (1588_clock_step_adj) to or from the seconds por- tion of the 1588 clock. the choice of adding or subtracting is set using the clock step adjustment directi on (1588_clock_step_adj_dir) bit. writing a zero to this bit has no affect. wo sc 0b 4 clock load (1588_clock_load) writing a one to this bit writes the value of the 1588 clock seconds register (1588_clock_sec) , the 1588 clock nanoseconds register (1588_clock_ns) and the 1588 clock sub-nanoseconds register (1588_clock_subns) into the 1588 clock. writing a zero to this bit has no affect. wo sc 0b 3 clock read (1588_clock_read) writing a one to this bit causes the current value of the 1588 clock to be saved into the 1588 clock seconds register (1588_clock_sec) , the 1588 clock nanoseconds register (1588_clock_ns) and the 1588 clock sub- nanoseconds register (1588_clock_subns) so it can be read. writing a zero to this bit has no affect. wo sc 0b 2 1588 enable (1588_enable) writing a one to this bit will enable the 1588 unit. reading this bit will return the current enabled value. writing a zero to this bit has no affect. note: ports are individually enabled with the time-stamp unit 2-0 enable bits in the 1588 general configuration register (1588_general_config) . r/w sc note 1: 1 1588 disable (1588_disable) writing a one to this bit will cause the 1588 enable (1588_enable) to clear once all current frame processing is completed. no new frame processing will be started if this bit is set. writing a zero to this bit has no affect. wo sc 0b 0 1588 reset (1588_reset) writing a one to this bit resets the 1588 h/w, state machines and registers and disables the 1588 unit. any frame modifications in progress are halted at the risk of causing frame data or fcs errors. 1588_reset should only be used once the 1588 unit is disabled as indicated by the 1588 enable (1588_enable) bit. note: writing a zero to this bit has no affect. wo sc 0b bits description type default
? 2015 microchip technology inc. -page 387 15.8.2 1588 general configuration register (1588_general_config) offset: 104h size: 32 bits bank: na bits description type default 31:19 reserved ro - 18 time-stamp unit 2 enable (tsu_enable_2) this bit enables the receive and transmit functions of time-stamp unit 2. the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) bit must also be set. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 17 time-stamp unit 1 enable (tsu_enable_1) this bit enables the receive and transmit functions of time-stamp unit 1. the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) bit must also be set. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 16 time-stamp unit 0 enable (tsu_enable_0) this bit enables the receive and transmit functions of time-stamp unit 0. the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) bit must also be set. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 15 gpio 1588 timer interru pt b clear enable (gpio_1588_timer_int_b_clear_en) this bit enables the selected gpio to clear the 1588_timer_int_b bit of the 1588 interrupt status register (1588_int_sts) . the gpio input is selected using the gpio 1588 timer interrupt b clear select (gpio_1588_timer_int_b_clear_sel[2:0]) bits in this register. the polarity of the gpio input is determined by gpio interrupt/1588 polarity 7-0 (gpio_pol[7:0]) in the general purpose i/o co nfiguration register (gpio_cfg) . note: the gpio must be configured as an input for this function to operate. for the clear function, gpio inputs are edge sensitive and must be active for greater than 40 ns to be recognized. r/w 0b 14:12 gpio 1588 timer interrupt b clear select (gpio_1588_timer_int_b_clear_sel[2:0]) these bits determine which gpio is used to clear the 1588 timer interrupt b (1588_timer_int_b) bit of the 1588 interrupt status register (1588_int_sts) . note: the ieee 1588 unit supp orts 8 gpio signals. r/w 000b
-page 388 ? 2015 microchip technology inc. 11 gpio 1588 timer interru pt a clear enable (gpio_1588_timer_int_a_clear_en) this bit enables the selected gpio to clear the 1588 timer interrupt a (1588_timer_int_a) bit of the 1588 interrupt status register (1588_int_sts) . the gpio input is selected using the gpio 1588 timer interrupt a clear select (gpio_1588_timer_int_a_clear_sel[2:0]) bits in this register. the polarity of the gpio input is determined by gpio interrupt/1588 polarity 7-0 (gpio_pol[7:0]) in the general purpose i/o configuration register (gpio_cfg) . note: the gpio must be configured as an input for this function to operate. for the clear function, gpio inputs are edge sensitive and must be active for greater than 40 ns to be recognized. r/w 0b 10:8 gpio 1588 timer interrupt a clear select (gpio_1588_timer_int_a_clear_sel[2:0]) these bits determine which gpio is used to clear the 1588_timer_int_a bit of the 1588 interrupt status r egister (1588_int_sts) . note: the ieee 1588 unit supp orts 8 gpio signals. r/w 000b 7:6 reserved ro - 5:4 clock event channel b mode (clock_event_b) these bits determine the output on clock event channel b when a clock tar- get compare event occurs. 00: 100ns pulse output 01: toggle output 10: 1588_timer_int_b bit value in 1588_int_sts_en register output 11: reserved note: the general purpose i/o configuration register (gpio_cfg) is used to enable the clock event onto the gpio pins as well as to set the polarity and output buffer type. r/w 00b 3:2 clock event channel a mode (clock_event_a) these bits determine the output on clock event channel a when a clock tar- get compare event occurs. 00: 100ns pulse output 01: toggle output 10: 1588_timer_int_a bit value in 1588_int_sts_en register output 11: reserved note: the general purpose i/o configuration register (gpio_cfg) is used to enable the clock event onto the gpio pins as well as to set the polarity and output buffer type. r/w 00b bits description type default
? 2015 microchip technology inc. -page 389 1 reload/add b (reload_add_b) this bit determines the course of acti on when a clock target compare event for clock event channel b occurs. when set, the 1588 clock target x seconds register (1588_clock_tar- get_sec_x) and 1588 clock target x nanoseconds register (1588_clock_target_ns_x) are loaded from the 1588 clock target x reload / add seconds register (1588_clock_target_reload_sec_x) and 1588 clock target x reload / add nanoseconds register (1588_clock_target_reload_ns_x) x=b. when low, the clock target registers are incremented by the clock target reload registers. 0: increment upon a clock target compare event 1: reload upon a clock target compare event r/w 0b 0 reload/add a (reload_add_a) this bit determines the course of acti on when a clock target compare event for clock event channel a occurs. when set, the 1588 clock target x seconds register (1588_clock_tar- get_sec_x) and 1588 clock target x nanoseconds register (1588_clock_target_ns_x) are loaded from the 1588 clock target x reload / add seconds register (1588_clock_target_reload_sec_x) and 1588 clock target x reload / add nanoseconds register (1588_clock_target_reload_ns_x) x=a. when low, the clock target registers are incremented by the clock target reload registers. 0: increment upon a clock target compare event 1: reload upon a clock target compare event r/w 0b bits description type default
-page 390 ? 2015 microchip technology inc. 15.8.3 1588 interrupt status register (1588_int_sts) this read/write register contains the 1588 interrupt status bits. writing a 1 to a interrupt status bits acknowledge s and clears the individual interrupt. if enabled in the 1588 interrupt enable register (1588_int_en) , these interrupt bits are cascaded into the 1588 interrupt event (1588_evnt) bit of the interrupt status register (int_sts) . status bits will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt. the 1588 interrupt event enable (1588_evnt_en) bit of the interrupt enable register (int_en) must also be set in order for an actual system level interrupt to occur. refer to section 8.0, "system interrupts," on page 67 for additional information. offset: 108h size: 32 bits bank: na bits description type default 31:24 1588 gpio falling edge interrupt (1588_gpio_fe_int[7:0]) this interrupt indicates that a falling event occurred and the 1588 clock was captured. note: as 1588 capture inputs, gpio inputs are edge sensitive and must be low for greater than 40 ns to be recognized as interrupt inputs. these bits can also be set due to a manual capture via 1588 manual capture (1588_manual_capture) . r/wc 00h 23:16 1588 gpio rising edge interru pt (1588_gpio_re_int[7:0]) this interrupt indicates that a rising event occurred and the 1588 clock was captured. note: as 1588 capture inputs, gpio inputs are edge sensitive and must be high for greater than 40 ns to be recognized as interrupt inputs. these bits can also be set due to a manual capture via 1588 manual capture (1588_manual_capture) . r/wc 00h 15 reserved ro - 14:12 1588 tx timestamp interrupt (1588_tx_ts_int[2:0]) this interrupt (one bit per port) indicates that a ptp packet was transmitted and its egress time stored. up to four events, as indicated by the 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) field in the 1588 port x capture information register (1588_cap_info_x) , are buffered per port. r/wc 000b 11 reserved ro - 10:8 1588 rx timestamp interrupt (1588_rx_ts_int[2:0]) this interrupt (one bit per port) indicates that a ptp packet was received and its ingress time and associated data stored. up to four events, as indicated by the 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) field in the 1588 port x capture information register (1588_cap_info_x) , are buffered per port. r/wc 000b 7:2 reserved ro -
? 2015 microchip technology inc. -page 391 1 1588 timer interrupt b (1588_timer_int_b) this interrupt indicates that the 1588 clock equaled or passed the clock event channel b clock target value in the 1588 clock target x seconds register (1588_cl ock_target_sec_x) and 1588 clock target x nano- seconds register (1588_clock_target_ns_x) x=b. note: this bit is also cleared by an active edge on a gpio if enabled. for the clear function, gpio input s are edge sensitive and must be active for greater than 40 ns to be recognized as a clear input. r/wc 0b 0 1588 timer interrupt a (1588_timer_int_a) this interrupt indicates that the 1588 clock equaled or passed the clock event channel a clock target value in the 1588 clock target x seconds register (1588_cl ock_target_sec_x) and 1588 clock target x nano- seconds register (1588_clock_target_ns_x) x=a. note: this bit is also cleared by an active edge on a gpio if enabled. for the clear function, gpio input s are edge sensitive and must be active for greater than 40 ns to be recognized as a clear input. r/wc 0b bits description type default
-page 392 ? 2015 microchip technology inc. 15.8.4 1588 interrupt enable register (1588_int_en) this read/write register contains the 1588 interrupt enable bits. if enabled, these interrupt bits are cascaded into the 1588 interrupt event (1588_evnt) bit of the interrupt status reg- ister (int_sts) . writing a 1 to an interrupt enable bits will enable the corresponding interrupt as a source. status bits will still reflect the status of the interr upt source regardless of whether the source is enabled as an interrupt in this reg- ister. the 1588 interrupt event enable (1588_evnt_en) bit of the interrupt enable register (int_en) must also be set in order for an actual system leve l interrupt to occur. refer to section 8.0, "system interrupts," on page 67 for additional information. offset: 10ch size: 32 bits bank: na bits description type default 31:24 1588 gpio falling edge interrupt enable (1588_gpio_fe_en[7:0]) r/w 00h 23:16 1588 gpio rising edge interrupt enable (1588_gpio_re_en[7:0]) r/w 00h 15 reserved ro - 14:12 1588 tx timestamp enable (1588_tx_ts_en[2:0]) r/w 000b 11 reserved ro - 10:8 1588 rx timestamp enable (1588_rx_ts_en[2:0]) r/w 000b 7:2 reserved ro - 1 1588 timer b interrupt enable (1588_timer_en_b) r/w 0b 0 1588 timer a interrupt enable (1588_timer_en_a) r/w 0b
? 2015 microchip technology inc. -page 393 15.8.5 1588 clock seconds register (1588_clock_sec) this register contains the seconds po rtion of the 1588 clock. it is used to read the 1588 clock following the setting of the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) and to directly change the 1588 clock when the clock load (1588_clock_load) bit is set. note: the value read is the saved value of the 1588 clock when the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) is set. offset: 110h size: 32 bits bank: na bits description type default 31:0 clock seconds (1588_clock_sec) this field contains the seconds portion of the 1588 clock. r/w 00000000h
-page 394 ? 2015 microchip technology inc. 15.8.6 1588 clock nanoseconds register (1588_clock_ns) this register contains the nan oseconds portion of the 1588 clock. it is used to read the 1588 clock following the setting of the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) and to directly change the 1588 clock when the clock load (1588_clock_load) bit is set. note: the value read is the saved value of the 1588 clock when the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) is set. offset: 114h size: 32 bits bank: na bits description type default 31:30 reserved ro - 29:0 clock nanoseconds (1588_clock_ns) this field contains the nanoseconds portion of the 1588 clock. r/w 00000000h
? 2015 microchip technology inc. -page 395 15.8.7 1588 clock sub-nanoseconds register (1588_clock_subns) this register contains the sub-nanoseconds portion of the 1588 clock. it is used to read the 1588 clock following the setting of the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) and to directly change the 1588 clock when the clock load (1588_clock_load) bit is set. note: the value read is the saved value of the 1588 clock when the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) is set. offset: 118h size: 32 bits bank: na bits description type default 31:0 clock sub-nanoseconds (1588_clock_subns) this field contains the sub-nanoseconds portion of the 1588 clock. r/w 00000000h
-page 396 ? 2015 microchip technology inc. 15.8.8 1588 clock rate adjustmen t register (1588 _clock_rate_adj) this register is used to adjust the rate of the 1588 clo ck. every 10 ns, 1588 clock is normally incremented by 10 ns. this register is used to occasionally change that increment to 9 or 11 ns. offset: 11ch size: 32 bits bank: na bits description type default 31 clock rate adjustment direction (1588_clock_rate_adj_dir) this field specifies if the 1588 rate ad justment causes the 1588 clock to be faster or slower than the reference clock. 0 = slower (1588 clock increments by 9 ns) 1 = faster (1588 clock increments by 11 ns) r/w 0b 30 reserved ro - 29:0 clock rate adjustment value (1588_clock_rate_adj_value) this field indicates an adjustment to the reference clock period of the 1588 clock in units of 2 -32 ns. on each 10 ns reference clock cycle, this value is added to the 32-bit sub-nanoseconds portion of the 1588 clock. when the sub-nanoseconds portion wraps around to zero, the 1588 clock will be adjusted by 1ns. r/w 00000000h
? 2015 microchip technology inc. -page 397 15.8.9 1588 clock temporary rate adjustment register (1588_clock_te mp_rate_adj) this register is used to temp orarily adjust the rate of the 1588 clock. ev ery 10 ns, 1588 clock is normally incremented by 10 ns. this register is used to occasio nally change that increment to 9 or 11 ns. offset: 120h size: 32 bits bank: na bits description type default 31 clock temporary rate adjustment direction (1588_clock_temp_rate_adj_dir) this field specifies if the 1588 tempor ary rate adjustment causes the 1588 clock to be faster or slower than the reference clock. 0 = slower (1588 clock increments by 9 ns) 1 = faster (1588 clock increments by 11 ns) r/w 0b 30 reserved ro - 29:0 clock temporary rate adjustment value (1588_clock_temp_rate_adj_value) this field indicates a temporary adjustment to the reference clock period of the 1588 clock in units of 2 -32 ns. on each 10ns reference clock cycle, this value is added to the 32-bit sub-nanoseconds portion of the 1588 clock. when the sub-nanoseconds portion wraps around to zero, the 1588 clock will be adjusted by 1ns (a 9 or 11 ns increment instead of the normal 10ns). r/w 00000000h
-page 398 ? 2015 microchip technology inc. 15.8.10 1588 clock temporary rate duration register (1588_clock_temp_rate_duration) this register specifies the active duratio n of the temporary clock rate adjustment. offset: 124h size: 32 bits bank: na bits description type default 31:0 clock temporary rate duration (1588_clock_temp_rate_duration) this field specifies the dur ation of the temporary rate adjustment in reference clock cycles. r/w 00000000h
? 2015 microchip technology inc. -page 399 15.8.11 1588 clock step adjustment register (1588_clock_step_adj) this register is used to perform a one-time adjustment to ei ther the seconds portion or the nanoseconds portion of the 1588 clock. the amount and di rection can be specified. offset: 128h size: 32 bits bank: na bits description type default 31 clock step adjustment direction (1588_clock_step_adj_dir) this field specifies if the clock step adjustment value (1588_clock_- step_adj_value) is added to or subtracted from the 1588 clock. 0 = subtracted 1 = added note: only addition is supported for the nanoseconds portion of the 1588 clock r/w 0b 30 reserved ro - 29:0 clock step adjustment value (1588_clock_step_adj_value) when the nanoseconds portion of the 1 588 clock is being adjusted, this field specifies the amount to add. this is in lieu of the normal 9, 10 or 11 ns incre- ment. when the seconds portion of the 1588 clock is being adjusted, the lower 4 bits of this field specify the amount to add to or subtract. r/w 00000000h
-page 400 ? 2015 microchip technology inc. 15.8.12 1588 clock target x seconds register (1588_clock_target_sec_x) this read/write regi ster combined with 1588 clock target x nanoseconds r egister (1588_clock_target_ns_x) form the 1588 clock target value. the 1588 clock target value is compared to the current 1588 clock value and can be used to trigger an interrupt upon at match. refer to section 15.4, "1588 clock events" for additional information. note: both this register and the 1588 clock target x nanoseconds r egister (1588_clock_target_ns_x) must be written for either to be affected. note: the value read is the saved value of the 1588 clock target when the clock target read (1588_clock_target_read) bit in the 1588 command and control register (1588_cmd_ctl) is set. note: when the clock target read (1588_clock_target_read) bit is set, the previous value written to this register is overwritten. normally, a read command should not be requested in between writing this register and the 1588 clock target x nanoseconds register (1588_clock_target_ns_x) . offset: channel a: 12ch size: 32 bits channel b: 13ch bank: channel a: na channel b: na bits description type default 31:0 clock target seconds (clock_target_sec) this field contains the seconds portion of the 1588 clock compare value. r/w 00000000h
? 2015 microchip technology inc. -page 401 15.8.13 1588 clock target x nanoseconds register (1588_ clock_target_ns_x) this read/write register combined with 1588 clock target x seconds regi ster (1588_clock_target_sec_x) form the 1588 clock target value. the 1588 clock target value is compared to the current 1588 clock value and can be used to trigger an interrupt upon at match. refer to section 15.4, "1588 clock events" for additional information. note: both this register and the 1588 clock target x seconds register (1588_clock_target_sec_x) must be written for either to be affected. note: the value read is the saved value of the 1588 clock target when the clock target read (1588_clock_target_read) bit in the 1588 command and control register (1588_cmd_ctl) is set. note: when the clock target read (1588_clock_target_read) bit is set, the previous value written to this register is overwritten. normally, a read command should not be requested in between writing this register and the 1588 clock target x seconds register (1588_clock_target_sec_x) . offset: channel a: 130h size: 32 bits channel b: 140h bank: channel a: na channel b: na bits description type default 31:30 reserved ro - 29:0 clock target nanoseconds (clock_target_ns) this field contains the nanoseconds portion of the 1588 clock compare value. r/w 00000000h
-page 402 ? 2015 microchip technology inc. 15.8.14 1588 clock target x re load / add seconds register (1588_clock_targ et_reload_sec_x) this read/write register combined with 1588 clock target x reload / add nanoseconds register (1588_clock_tar- get_reload_ns_x) form the 1588 clock target reload value. the 1588 clock target reload is the value that is reloaded or added to the 1588 clock compare value when a clock compare event occurs. refer to section 15.4, "1588 clock events" for additional information. note: both this register and the 1588 clock target x reload / add nanoseconds register (1588_clock_tar- get_reload_ns_x) must be written for either to be affected. offset: channel a: 134h size: 32 bits channel b: 144h bank: channel a: na channel b: na bits description type default 31:0 clock target reload seconds (clock_target_reload_sec) this field contains the seconds portion of the 1588 clock target reload value that is reloaded to the 1588 clock compare value. r/w 00000000h
? 2015 microchip technology inc. -page 403 15.8.15 1588 clock target x relo ad / add nanoseconds register (1588_clock_target_reload_ns_x) this read/write regi ster combined with 1588 clock target x reload / add seconds register (1588_clock_tar- get_reload_sec_x) form the 1588 clock target reload value. the 1588 clock target reload is the value that is reloaded or added to the 1588 clock compare value when a clock compare event occurs. refer to section 15.4, "1588 clock events" for additional information. note: both this register and the 1588 clock target x reload / add seconds register (1588_clock_tar- get_reload_sec_x) must be written for either to be affected. offset: channel a: 138h size: 32 bits channel b: 148h bank: channel a: na channel b: na bits description type default 31:30 reserved ro - 29:0 clock target reload nanoseconds (clock_target_reload_ns) this field contains the nanoseconds po rtion of the 1588 clock target reload value that is reloaded to the 1588 clock compare value. r/w 00000000h
-page 404 ? 2015 microchip technology inc. 15.8.16 1588 user mac address high -word register (1588_user_mac_hi) this read/write regist er combined with the 1588 user mac address low-dword register (1588_user_mac_lo) forms the 48-bit user defined mac a ddress. the auxiliary mac address can be enabled for each protocol via their respective user defined mac address enable bit in the 1588 port x rx parsing configuration register (1588_rx- _parse_config_x) . offset: 14ch size: 32 bits bank: na bits description type default 31:16 reserved ro - 15:0 user mac address high (user_mac_hi) this field contains the high 16 bits of the user defined mac address used for ptp packet detection. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0000h
? 2015 microchip technology inc. -page 405 15.8.17 1588 user mac address low-dw ord register (1 588_user_mac_lo) this read/write register combined with the 1588 user mac address high-word register (1588_user_mac_hi) forms the 48-bit user defined mac a ddress. the auxiliary mac address can be enabled for each protocol via their respective user defined mac address enable bit in the 1588 port x rx parsing configuration register (1588_rx- _parse_config_x) . offset: 150h size: 32 bits bank: na bits description type default 31:0 user mac address low (user_mac_lo) this field contains the low 32 bits of the user defined mac address used for ptp packet detection. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 00000000h
-page 406 ? 2015 microchip technology inc. 15.8.18 1588 bank port gp io select register (15 88_bank_port_gpio_sel) offset: 154h size: 32 bits bank: na bits description type default 31:11 reserved ro - 10:8 gpio select (gpio_sel[2:0]) this field specifies which gpio the various gpio x registers will access. r/w 000b 7:6 reserved ro - 5:4 port select (port_sel[1:0]) this field specifies which port the va rious port x registers will access. r/w 00b 3 reserved ro - 2:0 bank select (bank_sel[2:0] this field specifies which bank of registers is accessed. 000: ports general 001: ports rx 010: ports tx 011: gpios 1xx: reserved r/w 000b
? 2015 microchip technology inc. -page 407 15.8.19 1588 port x latency register (1588_latency_x) note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. note 2: the proper value for rmii mode needs to be set, via s/w or eeprom, based upon the speed and clock direction. note 3: the default value is appropriate for 100base-tx m ode. for other modes (100base-fx or 10base-t) the proper value needs to be set, via s/w or eeprom. note 4: the default value is appropriate for 100base-tx m ode. for other modes (100base-fx or 10base-t) the proper value needs to be set, via s/w or eeprom. offset: 158h size: 32 bits bank: 0 bits description type default 31:16 tx latency (tx_latency[15:0]) this field specifies the egress delay in nanoseconds between the ptp time- stamp point and the network medium. the setting is used to adjust the inter- nally captured 1588 clock value such that the resultant timestamp more accurately corresponds to the start of the frame?s first symbol after the sfd on the network medium. the value depends on the port mode. typical values are: ? 100base-tx: 95ns ? 100base-fx: 68ns plus the receiv e latency of the fiber transceiver ? 10base-t: 1139ns ? 100mbps rmii: 20ns plus any external receive latency ? 10mbps rmii: 20ns plus any external receive latency note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 20 for port 0 note 2 95 for port 1 note 3 95 for port 2 note 4 15:0 rx latency (rx_latency[15:0]) this field specifies the ingress delay in nanoseconds between the network medium and the ptp timestamp point. the setting is used to adjust the inter- nally captured 1588 clock value such t hat the resultant timestamp more accu- rately corresponds to the start of the frame?s first symbol after the sfd on the network medium. the value depends on the port mode. typical values are: ? 100base-tx: 285ns ? 100base-fx: 231ns plus the receiv e latency of the fiber transceiver ? 10base-t: 1674ns ? 100mbps rmii: 70ns plus any external receive latency ? 10mbps rmii: 440ns plus any external receive latency note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 20 for port 0 note 2 285 for port 1 note 3 285 for port 2 note 4
-page 408 ? 2015 microchip technology inc. 15.8.20 1588 port x asymmetry and peer delay register (1588_asym_peerdly_x) note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 15ch size: 32 bits bank: 0 bits description type default 31:16 port delay asymmetry (delay_asym[15:0]) this field specifies the previously known delay asymmetry in nanoseconds. this is a signed 2?s complement number. positive values occur when the master-to-slave or responder-to-reque stor propagation time is longer than the slave-to-master or requestor-t o-responder propagation time. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0000h 15:0 rx peer delay (r x_peer_delay[15:0]) this field specifies the measured pee r delay in nanoseconds used during peer-to-peer mode. r/w 0000h
? 2015 microchip technology inc. -page 409 15.8.21 1588 port x capt ure information regist er (1588_cap_info_x) this read only register provides information about the receive and transmit capture buffers. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 160h size: 32 bits bank: 0 bits description type default 31:7 reserved ro - 6:4 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) this field indicates how many transmit ti mestamps are available to be read. it is incremented when a ptp packet is transmitted and decremented when the appropriate 1588 tx timestamp interr upt (1588_tx_ts_int[2:0]) bit is writ- ten with a 1. ro 000b 3 reserved ro - 2:0 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) this field indicates how many receive timestamps are available to be read. it is incremented when a ptp packet is received and decremented when the appropriate 1588 rx timestamp interrupt (1588_rx_ts_int[2:0]) bit is writ- ten with a 1. ro 000b
-page 410 ? 2015 microchip technology inc. 15.8.22 1588 port x rx parsing configura tion register (1588_rx_parse_config_x) this register is used to configure the ptp receive message detection. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 158h size: 32 bits bank: 1 bits description type default 31:15 reserved ro - 14 rx layer 2 address 1 enable (rx_layer2_add1_en) this bit enables the layer 2 mac address of 01:80:c2:00:00:0e for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 13 rx layer 2 address 2 enable (rx_layer2_add2_en) this bit enables the layer 2 mac ad dress of 01:1b:19:00:00:00 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 12 rx address 1 enable (rx_add1_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:81 and ipv4 desti- nation address of 224.0.1.129 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:81 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:181 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 11 rx address 2 enable (rx_add2_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:82 and ipv4 desti- nation address of 224.0.1.130 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:82 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:182 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b
? 2015 microchip technology inc. -page 411 10 rx address 3 enable (rx_add3_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:83 and ipv4 desti- nation address of 224.0.1.131 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:83 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:183 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 9 rx address 4 enable (rx_add4_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:84 and ipv4 desti- nation address of 224.0.1.132 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:84 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:184 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 8 rx address 5 enable (rx_add5_en) this bit enables the ipv4 mac address of 01:00:5e:00:00:6b and ipv4 desti- nation address of 224.0.0.107 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:00:6b and ipv6 desti- nation address of ff02:0:0: 0:0:0:0:6b for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 7 rx user defined layer 2 mac address enable (rx_layer2_user_mac_en) this bit enables a user defined layer 2 mac address in ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 6 rx user defined ipv6 mac addr ess enable (rx_ipv6_user_mac_en) this bit enables a user defined ipv6 mac address in ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 5 rx user defined ipv4 mac addr ess enable (rx_ipv4_user_mac_en) this bit enables the user defined ipv4 mac address in ptp messages. the address is defined via the 1588 user mac address high-word register (1588_user_mac_hi) and the 1588 user mac address low-dword register (1588_user_mac_lo) . note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b bits description type default
-page 412 ? 2015 microchip technology inc. 4 rx ip address enable (rx_ip_addr_en) this bit enables the checking of the ip destination address in ptp messages for both ipv4 and ipv6 formats. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 3 rx mac address enable (rx_mac_addr_en) this bit enables the checking of the mac destination address in ptp mes- sages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 2 rx layer 2 enable (rx_layer2_en) this bit enables the detection of the layer 2 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 1 rx ipv6 enable (rx_ipv6_en) this bit enables the detection of the udp/ipv6 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 0 rx ipv4 enable (rx_ipv4_en) this bit enables the detection of the udp/ipv4 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b bits description type default
? 2015 microchip technology inc. -page 413 15.8.23 1588 port x rx timest amp configuration register (1588_rx_timest amp_config_x) this register is used to configure ptp receive message timestamping. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 15ch size: 32 bits bank: 1 bits description type default 31:24 rx ptp domain (r x_ptp_domain[7:0]) this field specifies the ptp domain in use. if rx ptp domain match enable (rx_ptp_domain_en) is set, the domainnumber in the ptp message must matches the value in this field in order to recorded the ingress time. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 00h 23 rx ptp domain match en able (rx_ptp_domain_en) when this bit is set, the domainnumber in the ptp message is checked against the value in rx ptp domain (r x_ptp_domain[7:0]) . note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 22 rx ptp alternate master en able (rx_ptp_alt_master_en) when this bit is set, the alternatemas terflag in the ptp message is checked for a zero value. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 21 rx ptp udp checksum check di sable (rx_ptp_udp_chksum_dis) when this bit is cleared, ingress ti mes are not saved and ingress messages are not filtered if the frame has an in valid udp checksum. when this bit is set, the udp checksu m check is bypassed and the ingress time is saved and ingress messages are filtered regardless. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 20 rx ptp fcs check disab le (rx_ptp_fcs_dis) when this bit is cleared, ingress ti mes are not saved and ingress messages are not filtered if the fr ame has an invalid fcs. when this bit is set, the fcs check is bypassed. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b
-page 414 ? 2015 microchip technology inc. 19:16 rx ptp version (r x_ptp_version[3:0]) this field specifies the ptp version in use. a setting of 0 allows any ptp ver- sion. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 2h 15:0 rx ptp message type enable (rx_ptp_message_en[15:0]) these bits individually enable timestamping of their respective message types. bit 0 of this field corresponds to a message type value of 0 (sync), bit 1 to message type value 1 (delay_req), etc. typically sync, delay_req, pdelay _req and pdelay_resp messages are enabled. r/w 0000h bits description type default
? 2015 microchip technology inc. -page 415 15.8.24 1588 port x rx timestamp insertion configuration register (1588_rx_ts_insert_config_x) this register is used to configure ptp message timestamp insertion. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 160h size: 32 bits bank: 1 bits description type default 31:18 reserved ro - 17 rx ptp insert delay request egress in delay response enable (rx_ptp_insert_dreq_dresp_en) when this bit is set, the egress time of the last delay_req packet is inserted into received delay_resp packets. this bit has no affect if rx_ptp_inser t_ts_en is a low or if detection of the delay_resp message type is not enabled. r/w 0b 16 rx ptp bad udp checksu m force error disable (rx_ptp_bad_udp_chksum_force_err_dis) when this bit is cleared, ingress packets that have an invalid udp checksum will have a receive symbol error forced if the packet is modified for timestamp or correction field reasons. when this bit is set, the ud p checksum check is bypassed. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 15 rx ptp insert timestamp seconds enable (rx_ptp_insert_ts_sec_en) when rx_ptp_insert_ts_en is set, this bit enables bits 3:0 of the sec- onds portion of the receive ingress time to be inserted into the ptp message. this bit has no affect if rx_ptp_insert_ts_en is a low. r/w 0b 14 reserved ro - 13:8 rx ptp insert timestamp seconds offset (rx_ptp_insert_t s_sec_offset[5:0]) this field specifies the offset into the ptp header where the seconds portion of the receive ingress time is inserted. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 000101b 7 rx ptp insert timestamp en able (rx_ptp_insert_ts_en) when set, receive ingr ess times are inserted into the ptp message. r/w 0b 6 reserved ro -
-page 416 ? 2015 microchip technology inc. 5:0 rx ptp insert timestamp offset (rx_ptp_insert_ ts_offset[5:0]) this field specifies the offset into th e ptp header where the receive ingress time is inserted. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 010000b bits description type default
? 2015 microchip technology inc. -page 417 15.8.25 1588 port x rx correction field mo dification register (1588_rx_cf_mod_x) this register is used to configure rx ptp message correction field modifications. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 164h size: 32 bits bank: 1 bits description type default 31:16 reserved ro - 15:0 rx ptp correction field message type enable (rx_ptp_cf_msg_en[15:0]) these bits individually enable correction field modification of their respective message types. bit 0 of this field corre sponds to a message type value of 0 (sync), bit 1 to message type value 1 (delay_req), etc. typically sync, delay_req, pdelay _req and pdelay_resp messages are enabled r/w 000fh
-page 418 ? 2015 microchip technology inc. 15.8.26 1588 port x rx filter configurati on register (1588_rx_filter_config_x) this register is used to configure ptp message filtering. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 168h size: 32 bits bank: 1 bits description type default 31:19 reserved ro - 18 rx ptp alternate master filter enable (rx_ptp_alt_master_fltr_en) this bit enables message filtering bas ed on the alternatemasterflag flagfield bit. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 17 rx ptp domain filter enab le (rx_ptp_domain_fltr_en) this bit enables message filtering based on the ptp domain. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 16 rx ptp version filter enab le (rx_ptp_version_fltr_en) this bit enables message filtering based on the ptp version. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 15:0 rx ptp message type filter enable (rx_ptp_msg_fltr_en[15:0]) these bits enable individual message filt ering. bit 0 of this field corresponds to a message type value of 0 (sync), bit 1 to message type value 1 (delay_req), etc. typically delay_req and delay_resp messages are filtered for peer-to-peer transparent clocks. r/w 0000h
? 2015 microchip technology inc. -page 419 15.8.27 1588 port x rx ingress time seconds register (1588_rx_ingress_sec_x) this read only register combined with the 1588 port x rx ingress time na noseconds register (1588_rx_in- gress_ns_x) contains the rx timestamp captures. up to four captures are buffered. note: values are only valid if the 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 16ch size: 32 bits bank: 1 bits description type default 31:0 timestamp seconds (ts_sec) this field contains the seconds portion of the receive ingress time. ro 00000000h
-page 420 ? 2015 microchip technology inc. 15.8.28 1588 port x rx ingress time na noseconds register (1588_rx_ingress_ns_x) this read only register combined with the 1588 port x rx ingress time seconds register (1588_rx_in- gress_sec_x) contains the rx timestamp capture. up to four captures are buffered. note: values are only valid if the 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 170h size: 32 bits bank: 1 bits description type default 31:30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds portion of the receive ingress time. ro 00000000h
? 2015 microchip technology inc. -page 421 15.8.29 1588 port x rx message header register (1588_rx_msg_header_x) this read only register contains the rx message header. up to four captures are buffered. note: values are only valid if the 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 174h size: 32 bits bank: 1 bits description type default 31:20 source port identity crc (src_prt_crc) this field contains the 12-bit crc of the sourceportidentity field of the received ptp packet. ro 000h 19:16 message type (msg_type) this field contains the messagetype field of the received ptp packet. ro 0h 15:0 sequence id (seq_id) this field contains the sequenceid field of the received ptp packet. ro 0000h
-page 422 ? 2015 microchip technology inc. 15.8.30 1588 port x rx pdelay_req ingress time seconds register (1588_rx_pdreq_sec_x) this register combined with the 1588 port x rx pdelay_req ingress ti me nanoseconds register (1588_rx_p- dreq_ns_x) contains the ingress time of the last pdelay_req me ssage. this register is automatically updated if the auto update (auto) bit is set. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 178h size: 32 bits bank: 1 bits description type default 31:4 reserved ro - 3:0 timestamp seconds (ts_sec) this field contains the seconds portion of the receive ingress time. r/w 0h
? 2015 microchip technology inc. -page 423 15.8.31 1588 port x rx pdelay_req ingress time nanoseconds register (1588_rx_pdreq_ns_x) this register combined with the 1588 port x rx pdelay_req ingress time seconds register (1588_rx_p- dreq_sec_x) contains the ingress time of the last pdelay_req me ssage. this register is automatically updated if the auto update (auto) bit is set. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 17ch size: 32 bits bank: 1 bits description type default 31 auto update (auto) if this bit is set, the ts_ns field in this register, the ts_sec field in 1588_rx_pdreq_sec_x and the cf field in 1588_rx_pdreq_cf_hi_x / 1588_rx_pdreq_cf_lo_x are updated when a pdelay_req message is received. when cleared, s/w is responsible to maintain those fields. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds portion of the receive ingress time. r/w 00000000h
-page 424 ? 2015 microchip technology inc. 15.8.32 1588 port x rx pdelay_req ingr ess correction field high register (1588_rx_pdreq_cf_hi_x) this register combined with the 1588 port x rx pdelay_req ingress corre ction field low register (1588_rx_p- dreq_cf_low_x) contains the correction field from the last pd elay_req message. only the nanoseconds portion is used. this register is automatically updated if the auto update (auto) bit is set. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 180h size: 32 bits bank: 1 bits description type default 31:0 correction field (cf[63:32]) this field contains the upper 32 bits of the correction field. r/w 00000000h
? 2015 microchip technology inc. -page 425 15.8.33 1588 port x rx pdelay_req in gress correction fi eld low register (1588_rx_pdreq_cf_low_x) this register combined with the 1588 port x rx pdelay_req ingress corre ction field high register (1588_rx_p- dreq_cf_hi_x) contains the correction field fr om the last pdelay_req message. only the nanoseconds portion is used. this register is automatically updated if the auto update (auto) bit is set. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 184h size: 32 bits bank: 1 bits description type default 31:16 correction field (cf[31:16]) this field contains the low middle 16 bits of the correction field. r/w 0000h 15:0 reserved ro -
-page 426 ? 2015 microchip technology inc. 15.8.34 1588 port x rx chec ksum dropped count register (1588_rx_chksum_dropped_cnt_x) this register counts the number of packets dropped at ingress due to a bad udp checksum. the packet will also be counted as an error by the receiving mac. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 188h size: 32 bits bank: 1 bits description type default 31:0 bad checksum dropped count (bad_chksum_dropped_cnt[31:0]) this field is a count of packets drop ped at ingress due to a bad udp check- sum. it can be cleared by writing a zero value at the risk of losing any previ- ous count. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 481 hours. r/w 00000000h
? 2015 microchip technology inc. -page 427 15.8.35 1588 port x rx fi ltered count register (1588_rx_filtered_cnt_x) this register counts the number of packets filtered at ingress due to ingress message filtering . the packet will also be counted as an error by the receiving mac. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 18ch size: 32 bits bank: 1 bits description type default 31:0 filtered count (filtered_cnt[31:0]) this field is a count of packets dropped at ingress due to ingress message filtering . it can be cleared by writing a zero value at the risk of losing any pre- vious count. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. r/w 00000000h
-page 428 ? 2015 microchip technology inc. 15.8.36 1588 port x tx parsing configur ation register (1588_tx_parse_config_x) this register is used to configur e the ptp transmit message detection. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 158h size: 32 bits bank: 2 bits description type default 31:15 reserved ro - 14 tx layer 2 address 1 enable (tx_layer2_add1_en) this bit enables the layer 2 mac address of 01:80:c2:00:00:0e for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 13 tx layer 2 address 2 enable (tx_layer2_add2_en) this bit enables the layer 2 mac ad dress of 01:1b:19:00:00:00 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 12 tx address 1 enable (tx_add1_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:81 and ipv4 desti- nation address of 224.0.1.129 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:81 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:181 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 11 tx address 2 enable (tx_add2_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:82 and ipv4 desti- nation address of 224.0.1.130 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:82 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:182 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b
? 2015 microchip technology inc. -page 429 10 tx address 3 enable (tx_add3_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:83 and ipv4 desti- nation address of 224.0.1.131 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:83 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:183 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 9 tx address 4 enable (tx_add4_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:84 and ipv4 desti- nation address of 224.0.1.132 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:84 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:184 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 8 tx address 5 enable (tx_add5_en) this bit enables the ipv4 mac address of 01:00:5e:00:00:6b and ipv4 desti- nation address of 224.0.0.107 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:00:6b and ipv6 desti- nation address of ff02:0:0: 0:0:0:0:6b for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 7 tx user defined layer 2 mac address enable (tx_layer2_user_mac_en) this bit enables a user defined layer 2 mac address in ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 6 tx user defined ipv6 mac address enable (tx_ipv6_user_mac_en) this bit enables a user defined ipv6 mac address in ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 5 tx user defined ipv4 mac address enable (tx_ipv4_user_mac_en) this bit enables the user defined ipv4 mac address in ptp messages. the address is defined via the 1588 user mac address high-word register (1588_user_mac_hi) and the 1588 user mac address low-dword register (1588_user_mac_lo) . note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b bits description type default
-page 430 ? 2015 microchip technology inc. 4 tx ip address enable (tx_ip_addr_en) this bit enables the checking of the ip destination address in ptp messages for both ipv4 and ipv6 formats. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 3 tx mac address enable (tx_mac_addr_en) this bit enables the checking of the mac destination address in ptp mes- sages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 2 tx layer 2 enable (tx_layer2_en) this bit enables the detection of the layer 2 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 1 tx ipv6 enable (tx_ipv6_en) this bit enables the detection of the udp/ipv6 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 0 tx ipv4 enable (tx_ipv4_en) this bit enables the detection of the udp/ipv4 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b bits description type default
? 2015 microchip technology inc. -page 431 15.8.37 1588 port x tx timest amp configuration register (1588_tx_timestamp_config_x) this register is used to configure ptp transmit message timestamping. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 15ch size: 32 bits bank: 2 bits description type default 31:24 tx ptp domain (tx_ptp_domain[7:0]) this field specifies the ptp domain in use. if tx ptp domain match enable (tx_ptp_domain_en) is set, the domainnumber in the ptp message must match the value in this field in order to recorded the egress time. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 00h 23 tx ptp domain match en able (tx_ptp_domain_en) when this bit is set, the domainnumber in the ptp message is checked against the value in tx ptp domain (t x_ptp_domain[7:0]) . note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 22 tx ptp alternate master en able (tx_ptp_alt_master_en) when this bit is set, the alternatemas terflag in the ptp message is checked for a zero value. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 21 tx ptp udp checksum check di sable (tx_ptp_udp_chksum_dis) when this bit is cleared, egress times are not saved if the frame has an invalid udp checksum. when this bit is set, the udp checksum check is bypassed and the egress time is saved regardless. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 20 tx ptp fcs check disa ble (tx_ptp_fcs_dis) when this bit is cleared, egress times are not saved if the frame has an invalid fcs. when this bit is set, the fcs check is bypassed. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b
-page 432 ? 2015 microchip technology inc. 19:16 tx ptp version (tx_ ptp_version[3:0]) this field specifies the ptp version in use. a setting of 0 allows any ptp ver- sion. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 2h 15:0 tx ptp message type enable (tx_ptp_message_en[15:0]) these bits individually enable timestamping of their respective message types. bit 0 of this field corresponds to a message type value of 0 (sync), bit 1 to message type value 1 (delay_req), etc. typically sync, delay_req, pdelay _req and pdelay_resp messages are enabled r/w 0000h bits description type default
? 2015 microchip technology inc. -page 433 15.8.38 1588 port x tx modification register (1588_tx_mod_x) this register is used to configure tx ptp message modifications. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 164h size: 32 bits bank: 2 bits description type default 31 tx ptp clear four byte reserved field (tx_ptp_clr_4_rsvrd) this bit enables the clearing of the four byte reserved field if the frame was modified on transmission. r/w 0b 30 tx ptp suppress timestamps when correction field adjusted (tx_ptp_supp_cf_ts) this bit prevents egress times from being saved if correction field modifica- tion is done. this is used to suppres s timestamps from frames forwarded across the switch. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 29 tx ptp pdelay_resp message turnaround time insertion (tx_ptp_pdresp_ta_insert) note: this bit enables the turnaround time between the received pdelay_req and the transmitted pdelay_resp to be inserted into the correction field of pdelay_r esp messages sent by the host. r/w 0b 28 tx ptp sync message egress time insertion (tx_ptp_sync_ts_insert) this bit enables the egress time to be inserted into the origintimestamp field of sync messages sent by the host. r/w 0b 27:22 tx ptp 4 reserved bytes offset (tx_ptp_4_rsvd_offset[5:0]) this field specifies the offset into th e ptp header of the four reserved bytes which the transmitter would clear if enabled. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 010000b 21:16 tx ptp 1 reserved byte offset (tx_ptp_1_rsvd_offset[5:0]) this field specifies the offset into th e ptp header where the transmitter can retrieve the seconds portion of the ingress time. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 000101b
-page 434 ? 2015 microchip technology inc. 15:0 tx ptp correction field message type enable (tx_ptp_cf_msg_en[15:0]) these bits individually enable correction field modification of their respective message types. bit 0 of this field corre sponds to a message type value of 0 (sync), bit 1 to message type value 1 (delay_req), etc. typically sync, delay_req, pdelay _req and pdelay_resp messages are enabled r/w 000fh bits description type default
? 2015 microchip technology inc. -page 435 15.8.39 1588 port x tx modification register 2 (1588_tx_mod2_x) this register is used to configure tx ptp message modifications. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 168h size: 32 bits bank: 2 bits description type default 31:1 reserved ro - 0 tx ptp clear udp/ipv4 checksum enable (tx_ptp_clr_udpv4_chksum) this bit enables the clearing of the udp/ipv4 checksum when pdelay_resp message turnaround time insertion or sync message egress time insertion is enabled. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b
-page 436 ? 2015 microchip technology inc. 15.8.40 1588 port x tx egress time seconds register (1588_tx_egress_sec_x) this read only register combined with the 1588 port x tx egress time nanoseconds register (1588_tx- _egress_ns_x) contains the tx timestamp captures. up to four captures are buffered. note: values are only valid if the 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 16ch size: 32 bits bank: 2 bits description type default 31:0 timestamp seconds (ts_sec) this field contains the seconds portion of the transmit egress time. ro 00000000h
? 2015 microchip technology inc. -page 437 15.8.41 1588 port x tx egress time na noseconds register (1588_tx_egress_ns_x) this read only register combined with the 1588 port x tx egress time seconds register (1588_tx_egress_sec_x) contains the tx timestamp capture. up to four captures are buffered. note: values are only valid if the 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 170h size: 32 bits bank: 2 bits description type default 31:30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds portion of the transmit egress time. ro 00000000h
-page 438 ? 2015 microchip technology inc. 15.8.42 1588 port x tx message head er register (1588_tx_msg_header_x) this read only register contains the tx mess age header. up to four captures are buffered. note: values are only valid if the 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 174h size: 32 bits bank: 2 bits description type default 31:20 source port identity crc (src_prt_crc) this field contains the 12-bit crc of t he sourceportidentity field of the trans- mitted ptp packet. ro 000h 19:16 message type (msg_type) this field contains the messagetype field of the transmitted ptp packet. ro 0h 15:0 sequence id (seq_id) this field contains the sequenceid field of the transmitted ptp packet. ro 0000h
? 2015 microchip technology inc. -page 439 15.8.43 1588 port x tx delay_re q egress time seconds register (1588_tx_dreq_sec_x) this register combined with the 1588 port x tx delay_req egress time nanoseconds register (1588_tx- _dreq_ns_x) contains the egress time of the last delay_req me ssage. the contents of this field are normally only used to insert the egress time into received delay_resp messages. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 178h size: 32 bits bank: 2 bits description type default 31:4 reserved ro - 3:0 timestamp seconds (ts_sec) this field contains the seconds portion of the transmit egress time. ro 0h
-page 440 ? 2015 microchip technology inc. 15.8.44 1588 port x tx delay_req egress time nanoseconds register (1588_tx_dreq_ns_x) this register combined with the 1588 port x tx delay_req egress time seconds register (1588_tx_dreq_sec_x) contains the egress time of the last delay_req message. the co ntents of this field are normally only used to insert the egress time into receiv ed delay_resp messages. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the port accessed (?x?) is set by the port select (port_sel[1:0]) field. offset: 17ch size: 32 bits bank: 2 bits description type default 31:30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds portion of the transmit egress time. ro 00000000h
? 2015 microchip technology inc. -page 441 15.8.45 1588 tx one-step sy nc upper seconds register (1588_tx_one_step_sync_sec) this register contains the highest 16 bits of the originti mestamp which is inserted into sync messages when one-step timestamp insertion is enabled. note: this is a static field that is maintained by the host. it is not incremented when the lower 32 bits of the 1588 clock rollover. note: this register applies to all ports. offset: 180h size: 32 bits bank: 2 bits description type default 31:16 reserved ro - 15:0 clock seconds high (1588_clock_sec_hi) this field contains the highest 16 bits of seconds of the 1588 clock. r/w 0000h
-page 442 ? 2015 microchip technology inc. 15.8.46 1588 gpio capture configurati on register (1588_gpio_cap_config) note: port and gpio registers share a common address space. gpio registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . note: the ieee 1588 unit supports 8 gpio signals. offset: 15ch size: 32 bits bank: 3 bits description type default 31:24 lock enable gpio falling edge (lock_gpio_fe) these bits enable/disables the gpio falling edge lock. this lock prevents a 1588 capture from overwriting the clock value if the gpio interrupt in the 1588 interrupt status re gister (1588_int_sts) is already set due to a previ- ous capture. 0: disables gpio falling edge lock 1: enables gpio falling edge lock r/w ffh 23:16 lock enable gpio rising edge (lock_gpio_re) these bits enable/disables the gpio rising edge lock. this lock prevents a 1588 capture from overwriting the clock value if the gpio interrupt in the 1588 interrupt status re gister (1588_int_sts) is already set due to a previ- ous capture. 0: disables gpio rising edge lock 1: enables gpio rising edge lock r/w ffh 15:8 gpio falling edge capture enable 7-0 (gpio_fe_capture_enable[7:0]) these bits enable the falling edge of th e respective gpio input to capture the 1588 clock value and to set the respective 1588_gpio interrupt in the 1588 interrupt status regi ster (1588_int_sts) . 0: disables gpio capture 1: enables gpio capture note: the gpio must be configured as an input for this function to operate. gpio inputs are edge sensitive and must be low for greater than 40 ns to be recognized. r/w 00h 7:0 gpio rising edge capture enable 7-0 (gpio_re_capture_enable[7:0]) these bits enable the rising edge of the respective gpio input to capture the 1588 clock value and to set the respective 1588_gpio interrupt in the 1588 interrupt status regi ster (1588_int_sts) . 0: disables gpio capture 1: enables gpio capture note: the gpio must be configured as an input for this function to operate. gpio inputs are edge sensitive and must be high for greater than 40 ns to be recognized. r/w 00h
? 2015 microchip technology inc. -page 443 15.8.47 1588 gpio x rising edge clock seconds capture register (1588_gpio_re_clock_sec_cap_x) this read only regist er combined with the 1588 gpio x rising edge clock nanoseconds capture register (1588_g- pio_re_clock_ns_cap_x) forms the gpio rising edge timestamp capture. note: values are only valid if the appropriate 1588 gpio rising edge interrupt (1588_gpio_re_int[7:0]) in the 1588 interrupt status register (1588_int_sts) indicates that a timestamp is available. note: unless the corresponding lock enable gpio rising edge (lock_gpio_re) bit is set, a new capture may occur between reads of this register and the 1588 gpio x rising edge clock nanoseconds capture reg- ister (1588_gpio_re_clock_ns_cap_x) . software techniques are required to avoid reading intermedi- ate values. note: port and gpio registers share a common address space. gpio registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select re gister (1588_bank_port_gpio_sel) . the gpio accessed (?x?) is set by the gpio select (gpio_sel[2:0]) field. note: all 8 gpio register sets are available. offset: 16ch size: 32 bits bank: 3 bits description type default 31:0 timestamp seconds (ts_sec) this field contains the seconds portion of the timestamp upon the rising edge of a gpio or upon a software commanded manual capture. ro 00000000h
-page 444 ? 2015 microchip technology inc. 15.8.48 1588 gpio x rising edge cl ock nanoseconds capture register (1588_gpio_re_clock_ns_cap_x) this read only register combined with the 1588 gpio x rising edge clock seconds capture register (1588_gpi- o_re_clock_sec_cap_x) forms the gpio rising edge timestamp capture. note: values are only valid if the appropriate 1588 gpio rising edge interrupt (1588_gpio_re_int[7:0]) in the 1588 interrupt status register (1588_int_sts) indicates that a timestamp is available. note: unless the corresponding lock enable gpio rising edge (lock_gpio_re) bit is set, a new capture may occur between reads of this register and the 1588 gpio x rising edge clo ck seconds capture register (1588_gpio_re_clock_sec_cap_x) . software techniques are required to avoid reading intermediate values. note: port and gpio registers share a common address space. gpio registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select re gister (1588_bank_port_gpio_sel) . the gpio accessed (?x?) is set by the gpio select (gpio_sel[2:0]) field. note: all 8 gpio register sets are available. offset: 170h size: 32 bits bank: 3 bits description type default 31:30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds por tion of the timestamp upon the rising edge of a gpio or upon a software commanded manual capture. ro 00000000h
? 2015 microchip technology inc. -page 445 15.8.49 1588 gpio x falling edge clock seconds c apture register (1588_gpio_fe_clock_sec_cap_x) this read only register combined with the 1588 gpio x falling edge clock nanos econds capture register (1588_g- pio_fe_clock_ns_cap_x) forms the gpio falling edge timestamp capture. note: values are only valid if the appropriate 1588 gpio falling edge interrupt (1588_gpio_fe_int[7:0]) in the 1588 interrupt status register (1588_int_sts) indicates that a timestamp is available. note: unless the corresponding lock enable gpio falling edge (lock_gpio_fe) bit is set, a new capture may occur between reads of this register and the 1588 gpio x falling edge clock nanoseconds capture reg- ister (1588_gpio_fe_clock_ns_cap_x) . software techniques are required to avoid reading intermedi- ate values. note: port and gpio registers share a common address space. gpio registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select re gister (1588_bank_port_gpio_sel) . the gpio accessed (?x?) is set by the gpio select (gpio_sel[2:0]) field. note: all 8 gpio register sets are available. offset: 178h size: 32 bits bank: 3 bits description type default 31:0 timestamp seconds (ts_sec) this field contains the seconds portion of the timestamp upon the falling edge of a gpio or upon a software commanded manual capture. ro 00000000h
-page 446 ? 2015 microchip technology inc. 15.8.50 1588 gpio x falling edge cl ock nanoseconds capture register (1588_gpio_fe_clock_ns_cap_x) this read only register combined with the 1588 gpio x falling edge clock seconds capture register (1588_gpi- o_fe_clock_sec_cap_x) forms the gpio falling edge timestamp capture. note: values are only valid if the appropriate 1588 gpio falling edge interrupt (1588_gpio_fe_int[7:0]) in the 1588 interrupt status register (1588_int_sts) indicates that a timestamp is available. note: unless the corresponding lock enable gpio falling edge (lock_gpio_fe) bit is set, a new capture may occur between reads of this register and the 1588 gpio x falling edge clock seconds capture register (1588_gpio_fe_clock_sec_cap_x) . software techniques are required to avoid reading intermediate values. note: port and gpio registers share a common address space. gpio registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select re gister (1588_bank_port_gpio_sel) . the gpio accessed (?x?) is set by the gpio select (gpio_sel[2:0]) field. note: all 8 gpio register sets are available. offset: 17ch size: 32 bits bank: 3 bits description type default 31:30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds portion of the timestamp upon the falling edge of a gpio or upon a software commanded manual capture. ro 00000000h
? 2015 microchip technology inc. ds00001926b-page 447 LAN9354 16.0 general purpose timer & free-running clock this chapter details the general purpos e timer (gpt) and the free-running clock. 16.1 general purpose timer the device provides a 16-bit programm able general purpose timer that can be used to generate periodic system inter- rupts. the resolution of this timer is 100 s. the gpt loads the general purpose timer count register (gpt_cnt) with the value in the general purpose timer pre-load (gpt_load) field of the general purpose timer confi guration register (gpt_cfg) when the general pur- pose timer enable (timer_en) bit of the general purpose timer configuration register (gpt_cfg) is asserted (1). on a chip-level reset or when the general purpose timer enable (timer_en) bit changes from asserted (1) to de- asserted (0), the general purpose timer pre-load (gpt_load) field is initialized to ffffh. the general purpose timer count register (gpt_cnt) is also initialized to ffffh on reset. once enabled, the gpt counts down until it reaches 0000h. at 0000h, the counter wraps around to ffffh, asserts the gp timer (gpt_int) interrupt status bit in the interrupt status register (int_sts) , asserts the irq interrupt (if gp timer interrupt enable (gpt_int_en) is set in the interrupt enable register (int_en) ) and continues counting. gp timer (gpt_int) is a sticky bit. once this bit is asserted, it can only be cleared by writing a 1 to the bit. refer to section 8.2.6, "general purpose timer interrupt," on page 70 for additional informati on on the gpt interrupt. software can write a pre-load value into the general purpose timer pre-load (gpt_load) field at any time (e.g., before or after the general purpose timer enable (timer_en) bit is asserted). the general purpose timer count reg- ister (gpt_cnt) will immediately be set to the new value and continue to count down (if enabled) from that value. 16.2 free-running clock the free-running clock (frc) is a simple 32-bit up-counter that operates from a fixed 25 mhz clock. the current frc value can be read via the free running 25mhz counter register (free_run) . on assertion of a chip-level reset, this counter is cleared to zero. on de-asse rtion of a reset, the counter is incr emented once for every 25 mhz clock cycle. when the maximum count has been reached, the counter rolls over to zeros. the frc does not generate interrupts. note: the free running counter can take up to 160 ns to clear after a reset event. 16.3 general purpose timer and free-running clock registers this section details the directly addressable general purpos e timer and free-running clock related system csrs. for an overview of the entire directly addressable register map, refer to section 5.0, "register map," on page 29 . table 16-1: miscellaneous registers address register name (symbol) 08ch general purpose timer conf iguration register (gpt_cfg) 090h general purpose timer count register (gpt_cnt) 09ch free running 25mhz counter register (free_run)
LAN9354 ds00001926b-page 448 ? 2015 microchip technology inc. 16.3.1 general purpose timer configuration register (gpt_cfg) this read/write register configures the device?s general purpose timer (gpt). the gpt ca n be configured to generate host interrupts at the interval defined in this register. the current value of the gpt can be monitored via the general purpose timer count register (gpt_cnt) . refer to section 16.1, "general purpose timer," on page 447 for additional information. offset: 08ch size: 32 bits bits description type default 31:30 reserved ro - 29 general purpose timer enable (timer_en) this bit enables the gpt. when set, the gpt enters the run state. when cleared, the gpt is halted. on the 1 to 0 transition of this bit, the gpt_load field of this register will be preset to ffffh. 0: gpt disabled 1: gpt enabled r/w 0b 28:16 reserved ro - 15:0 general purpose timer pre-load (gpt_load) this value is pre-loaded into the gpt. th is is the starting value of the gpt. the timer will begin decrementing from this value when enabled. r/w ffffh
? 2015 microchip technology inc. ds00001926b-page 449 LAN9354 16.3.2 general purpose timer count register (gpt_cnt) this read-only register reflects the curr ent general purpose timer (gpt) value. th e register should be used in conjunc- tion with the general purpose timer configuration register (gpt_cfg) to configure and monitor the gpt. refer to section 16.1, "general purpose timer," on page 447 for additional information. offset: 090h size: 32 bits bits description type default 31:16 reserved ro - 15:0 general purpose timer current count (gpt_cnt) this 16-bit field represents the current value of the gpt. ro ffffh
LAN9354 ds00001926b-page 450 ? 2015 microchip technology inc. 16.3.3 free running 25mhz counter register (free_run) this read-only register reflects the current va lue of the free-running 25mhz counter. refer to section 16.2, "free-run- ning clock," on page 447 for additional information. offset: 09ch size: 32 bits bits description type default 31:0 free running counter (fr_cnt) this field reflects the current value of the free-running 32-bit counter. at reset, the counter starts at zero and is incremented by one every 25 mhz cycle. when the maximum c ount has been reac hed, the counter will rollover to zero and continue counting. note: the free running counter can take up to 160ns to clear after a reset event. ro 00000000h
? 2015 microchip technology inc. -page 451 17.0 gpio/led controller 17.1 functional overview the gpio/led controller provides 8 confi gurable general purpose input/output pins, gpio[7:0] . these pins can be indi- vidually configured to function as inputs, push-pull outputs or open drain outputs and each is capable of interrupt gen- eration with configurable polarity. alternatively, 6 gpio pins can be configured as led outputs, enabling these pins to drive ethernet status leds for external indication of variou s attributes of the ports. al l gpios also provide extended 1588 functionality. refer to section 15.5, "1588 gpios," on page 380 for additional details. gpio and led functionality is configured via the gpio/led system control and status registers (csrs). these reg- isters are defined in section 17.4, "gpio/led registers," on page 454 . 17.2 gpio operation the gpio controller is comprised of 8 programmable input/outpu t pins. these pins are individually configurable via the gpio csrs. on application of a chip-level reset: ? all gpios are set as inputs ( gpio direction 7-0 (gpiodir[7:0]) cleared in general purpose i/o data & direction register (gpio_data_dir) ) ? all gpio interrupts are disabled ( gpio interrupt enable[7:0] (gpio[7:0]_int_en) cleared in general purpose i/o interrupt status and enable register (gpio_int_sts_en) ? all gpio interrupts are configured to low logic level triggering ( gpio interrupt/1588 polari ty 7-0 (gpio_pol[7:0]) cleared in general purpose i/o configuration register (gpio_cfg) ) note: gpio[5:0] may be configured as led outputs by default, dependent on the led_en_strap[5:0] configuration straps. refer to section 17.3, "led operation" for additional information. the direction and buffer type of all gpios are configured via the general purpose i/o config uration register (gpi- o_cfg) and general purpose i/o data & direction register (gpio_data_dir) . the direction of each gpio, input or output, should be configured first via its respective gpio direction 7-0 (gpiodir[7:0]) bit in the general purpose i/o data & direction register (gpio_data_dir) . when configured as an output, the output buffer type for each gpio is selected by the gpio buffer type 7-0 (gpiobuf[7:0]) bits in the general purpose i/o configuration register (gpi- o_cfg) . push/pull and open-drain output bu ffers are supported for each gpio. when functioning as an open-drain driver, the gpio output pin is driven low when the corresponding gpio data 7-0 (gpiod[7:0]) bit in the general pur- pose i/o data & direction register (gpio_data_dir) is cleared to 0 and is not driven when set to 1. when a gpio is enabled as a push/pull output, the valu e output to the gpio pin is set via the corresponding gpio data 7-0 (gpiod[7:0]) bit in the general purpose i/o data & direction register (gpio_data_dir) . for gpios configured as inputs, the corresponding gpio data 7-0 (gpiod[7:0]) bit reflects the current state of the gpio input. in gpio mode, the input buffers are disabled when the pin is set to an output and the pull-ups are normally enabled. note: upon reset, gpios that were output s may generate an active interrupt stat us as the system settles - typically when a low gpio pin slowly rises due to the internal pull-up. the interrupt status bits within the general purpose i/o interrupt status and en able register (gpio_int_sts_en) should be cleared as part of the device initialization software routine. 17.2.1 gpio interrupts each gpio provides the ability to trig ger a unique gpio interrupt in the general purpose i/o interrupt status and enable register (gpi o_int_sts_en) . reading the gpio interrupt[7:0] (gpio[7:0]_int) bits of this register provides the cur- rent status of the corresponding interrupt and eac h interrupt is enabled by setting the corresponding gpio interrupt enable[7:0] (gpio[7:0]_int_en) bit. the gpio/led controller aggregates the enabled interrupt values into an internal signal that is sent to the system inte rrupt controller and is reflected via the interrupt status register (int_sts) gpio interrupt event (gpio) bit. for more information on interrupts, refer to section 8.0, "system interrupts," on page 67 . as interrupts, gpio inputs are level sensitive and must be active for greater than 40 ns to be recognized. 17.2.1.1 gpio in terrupt polarity the interrupt polarity can be set for each individual gpio via the gpio interrupt/1588 polari ty 7-0 (gpio_pol[7:0]) bits in the general purpose i/o configuration register (gpio_cfg) . when set, a high logic level on the gpio pin will set the corresponding interrupt bit in the general purpose i/o interrupt status and enable register (gpio_int_sts_en) . when cleared, a low logic level on the gpio pin will set the corresponding interrupt bit.
-page 452 ? 2015 microchip technology inc. 17.3 led operation gpio[5:0] can be individually selected to function as a led. these pins are configured as led outputs by setting the corresponding led enable 5-0 (led_en[5:0]) bit in the led configuration register (led_cfg) . when configured as an led, the pin is either a push-pull or open-drain / open-source output and th e gpio related input buffer and pull-up are disabled. the default configuration, including polarity, is determined by input straps or eeprom entries. refer to section 7.0, "configurat ion straps," on page 54 for additional information. the functions associated with each led pin are configurable via the led function 2-0 (led_fun[2:0]) bits of the led configuration register (led_cfg) . these bits allow the configuration of each led pin to indicate various port related functions. the behaviors of each led for each led function 2-0 (led_fun[2:0]) configuration are described in the following tables. detailed definitions for each led indication type are provided in section 17.3.1 and section 17.3.2 . the default values of the led function 2-0 (led_fun[2:0]) and led enable 5-0 (led_en[5:0]) bits of the led con- figuration register (led_cfg) are determined by the led_fun_strap[2:0] and led_en_strap[5:0] configuration straps. for more information on the led configuration register (led_cfg) and its related straps, refer to section 17.4.1, "led configuration register (led_cfg)," on page 455 . all led outputs may be disabled by setting the led disable (led_dis) bit in the power management control register (pmt_ctrl) . open-drain / open-source leds are un-driven. push-pull leds are still driven but are set to their inactive state. table 17-1: led operation as a function of led_fun[2:0] = 000b - 011b 000b 001b 010b 011b led5 (gpio5) link / activity port 2 100link / activity port 2 tx port 0 activity port 2 led4 (gpio4) full-duplex / collision port 2 full-duplex / collision port 2 link / activity port 2 link port 2 led3 (gpio3) speed port 2 10link / activity port 2 speed port 2 speed port 2 led2 (gpio2) link / activity port 1 100link / activity port 1 rx port 0 activity port 1 led1 (gpio1) full-duplex / collision port 1 full-duplex / collision port 1 link / activity port 1 link port 1 led0 (gpio0) speed port 1 10link / activity port 1 speed port 1 speed port 1
? 2015 microchip technology inc. -page 453 the various led indication functions listed in the pr evious tables are described in the following sections. 17.3.1 led function definitions when led_fun[2:0] = 000b - 101b the following led rules apply when led function 2-0 (led_fun[2:0]) is 000b through 101b: ? ?active? is defined as the pin being driven to the opposit e value latched at reset on the related hard-straps. the led polarity cannot be modified via soft-straps. ? ?inactive? is defined as the pin not being driven. ? the input buffers and pull-ups are disabled on the shared gpio/led pins. the following led function definitions apply when led function 2-0 (led_fun[2:0]) is 000b through 101b: ? tx - the signal is pulsed active for 80 ms to indicate activi ty from the switch fabric to the external mii pins. this signal is then made inactive for a minimum of 80 ms, after which the process will repeat if tx activity is again detected. note: link indication does not affect this function. ? rx - the signal is pulsed active for 80 ms to indicate activity from the external mii pins to the switch fabric. this signal is then made inactive for a minimum of 80 ms, afte r which the process will repeat if rx activity is again detected. note: link indication does not affect this function. ? activity - the signal is pulsed active for 80ms to indicate transmit or receive activity on the port. the signal is then made inactive for a minimum of 80ms, after which t he process will repeat if rx or tx activity is again detected. note: the idle condition is inactive in contrast to that of the link / activity function. note: the signal will be held inactive if the internal phy does not have a valid link. link indication does not affect this function in external (mii/rmii) modes. ? link - a steady active output indicates th at the port has a valid link (10mbps or 100mbps), while a steady inactive output indicates no link on the port. ? link / activity - a steady active output indicate s that the port has a valid link, while a steady inactive output indi- cates no link on the port. when the port has a valid link, the signal is pulsed inactive for 80 ms to indicate transmit or receive activity on the port. the signal is then made active for a minimum of 80 ms, after which the process will repeat if rx or tx activity is again detected. ? 100link - a steady active output indicates the port has a va lid link and the speed is 100 mbps. the signal will be table 17-2: led operation as a function of led_fun[2:0] = 100b - 111b 100b 101b 110b 111b led5 (gpio5) activity port 2 activity port 2 reserved tx_en port 0 led4 (gpio4) link port 2 10link port 2 tx_en port 2 led3 (gpio3) full-duplex / collision port 2 100link port 2 rx_dv port 2 led2 (gpio2) activity port 1 activity port 1 rx_dv port 0 led1 (gpio1) link port 1 10link port 1 tx_en port 1 led0 (gpio0) full-duplex / collision port 1 100link port 1 rx_dv port 1
-page 454 ? 2015 microchip technology inc. held inactive if the port does not have a valid link or the speed is not 100 mbps. ? 100link / activity - a steady active output indicates the port has a valid link and the speed is 100 mbps. the sig- nal is pulsed inactive for 80 ms to indicate tx or rx acti vity on the port. the signal is then driven active for a min- imum of 80 ms, after which the process will repeat if rx or tx activity is again detected. the signal will be held inactive if the port does not have a valid link or the speed is not 100 mbps. ? 10link - a steady active output indicates the port has a valid link and the speed is 10 mbps. this signal will be held inactive if the port does not have a valid link or the speed is not 10 mbps. ? 10link / activity - a steady active output indica tes the port has a valid link and the speed is 10 mbps. the signal is pulsed inactive for 80 ms to indicate transmit or receive activity on the port. the signal is then driven active for a minimum of 80 ms, after which the process will repeat if rx or tx activity is again detected. this signal will be held inactive if the port does not have a valid link or the speed is not 10 mbps. ? full-duplex / collision - a steady active output indicates the port is in full-duplex mode. in half-duplex mode, the signal is pulsed active for 80 ms to indicate a network co llision. the signal is then made inactive for a minimum of 80 ms, after which the process will repeat if another collision is detected. the signal will be held inactive if the port does not have a valid link. ? speed - a steady active output indicates a valid link with a speed of 100 mbps. a steady inactive output indicates a speed of 10 mbps. the signal will be held inactive if the port does not have a valid link. 17.3.2 led function definitions when led_fun[2:0] = 111b when led function 2-0 (led_fun[2:0]) is 111b , the following led rules apply: ? the led pins are push-pull drivers. ? the led pin is driven high when the function signal is hi gh and is driven low when the function signal is low. ? the input buffers and pull-ups are disabled on the shared gpio/led pins. when led function 2-0 (led_fun[2:0]) is 111b, the following led function definitions apply: ? tx_en - non-stretched tx_en signal from the switch fabric. note: link indication does not affect this function. ? rx_dv - non-stretched rx_dv signal to the switch fabric. note: link indication does not affect this function. 17.4 gpio/led registers this section details the directly addr essable general purpose i/o (gpio) and led related system csrs. for an over- view of the entire directly addressable register map, refer to section 5.0, "register map," on page 29 . table 17-3: gpio/led registers address register name (symbol) 1bch led configuration register (led_cfg) 1e0h general purpose i/o configuration register (gpio_cfg) 1e4h general purpose i/o data & direction register (gpio_data_dir) 1e8h general purpose i/o interrupt status and enable register (gpio_int_sts_en)
? 2015 microchip technology inc. -page 455 17.4.1 led configuratio n register (led_cfg) this read/write regist er configures the gpio[5:0] pins as led pins and sets their functionality. note 1: the default value of this field is determined by the configuration strap led_fun_strap[2:0] . note 2: the default value of this field is determined by the configuration strap led_en_strap[5:0] . offset: 1bch size: 32 bits bits description type default 31:11 reserved ro - 10:8 led function 2-0 (led_fun[2:0]) these bits control the function associated with each led pin as shown in section 17.3, "led operation," on page 452 . note: in order for these assignments to be valid, the particular pin must be enabled as an led output pin via the led_en bits of this register. r/w note 1 7:6 reserved ro - 5:0 led enable 5-0 (led_en[5:0]) this field toggles the functionality of the gpio[5:0] pins between gpio and led. 0: enables the associated pin as a gpio signal 1: enables the associated pin as a led output when configured as led outputs, the pins are either push-pull or open-drain/ open-source outputs and the pull-ups and input buffers are disabled. push- pull is selected when led_fun[2:0] = 111b, otherwise, they are open-drain/ open-source. when open-drain/open-sour ce, the polarity of the pins depends upon the strap value sampled at reset. if a high is sampled at reset, then this signal is active low. note: the polarity is determined by the strap value sampled on reset (a hard-strap) and not the soft-strap va lue (of the shared strap) set via eeprom. when configured as a gpio output, the pins are configured per the general purpose i/o configuration register (gpio_cfg) and the general purpose i/ o data & direction register (gpio_data_dir) . the polarity of the pins does not depend upon the strap value sampled at reset. r/w note 2
-page 456 ? 2015 microchip technology inc. 17.4.2 general purpose i/o conf iguration register (gpio_cfg) this read/write register configures the gpio input and output pins. the pol arity of the gpio pins is configured here as well as the ieee 1588 timestamping and clo ck compare event output properties. refer to section 15.5, "1588 gpios," on page 380 for additional 1588 information. offset: 1e0h size: 32 bits bits description type default 31:24 1588 gpio channel select 7-0 (gpio_ch_sel[7:0]) these bits select the 1588 channel to be output on the corresponding gpio[7:0]. refer to section 15.5, "1588 gpios," on page 380 for additional information. 0: sets 1588 channel a as the output for the corresponding gpio pin 1: sets 1588 channel b as the output for the corresponding gpio pin r/w 00h 23:16 gpio interrupt/1588 polari ty 7-0 (gpio_pol[7:0]) these bits set the interrupt input polar ity and 1588 clock event output polarity of the 8 gpio pins. the configured le vel (high/low) will set the corresponding gpio_int bit in the general purpose i/o interrupt status and enable regis- ter (gpio_int_sts_en) . 1588 clock events will be output active at the con- figured level (high/low). these bits also determine the polarity of the gpio 1588 timer interrupt clear inputs. refer to section 15.5, "1588 gpios," on page 380 for additional infor- mation. 0: sets low logic level trigger on corresponding gpio pin 1: sets high logic level trigger on corresponding gpio pin r/w 00h 15:8 1588 gpio output enable 7-0 (1588_gpio_oe[7:0]) these bits configure the 8 gpio pins to output 1588 clock compare events. 0: disables the output of 1588 clock compare events 1: enables the output of 1588 clock compare events note: these bits override the direction bits in the general purpose i/o data & direction register (gpio_data_dir) register. however, the gpio buffer type 7-0 (gpiobuf[7:0]) in the general purpose i/o configuration register (gpio_cfg) is not overridden. r/w 00h
? 2015 microchip technology inc. -page 457 7:0 gpio buffer type 7-0 (gpiobuf[7:0]) this field sets the buffer types of the 8 gpio pins. 0: corresponding gpio pin configured as an open-drain driver 1: corresponding gpio pin configured as a push/pull driver as an open-drain driver, the output pin is driven low when the corresponding data register is cleared, and is not driven when the corresponding data regis- ter is set. as an open-drain driver used for 1588 clock events, the corresponding gpio_pol_x bit determines when the corresponding pin is driven per the following table: r/w 00h bits description type default gpiox clock event polarity 1588 clock event pin state 0 no not driven 0 yes driven low 1 no driven low 1 yes not driven
-page 458 ? 2015 microchip technology inc. 17.4.3 general purpose i/o data & di rection register (gpio_data_dir) this read/write register configures the direction of the gpio pins and contains the gpio input and output data bits. offset: 1e4h size: 32 bits bits description type default 31:24 reserved ro - 23:16 gpio direction 7-0 (gpiodir[7:0]) these bits set the input/output direction of the 8 gpio pins. 0: gpio pin is configured as an input 1: gpio pin is configured as an output r/w 00h 15:8 reserved ro - 7:0 gpio data 7-0 (gpiod[7:0]) when a gpio pin is enabled as an output, the value written to this field is out- put on the corresponding gpio pin. upon a read, the value returned depends on the current direction of the pin. if the pin is an input, the data reflects the current state of the corresponding gpio pin. if the pin is an output, the data is the value that was last written into this register. the pin direction is dete rmined by the gpiodir bits of this reg- ister and the 1588_gpio_oe bits in the general purpose i/o configuration register (gpio_cfg) . r/w 00h
? 2015 microchip technology inc. -page 459 17.4.4 general purpose i/o interr upt status and enable register (gpio_int_sts_en) this read/write register contains the gpio interrupt status bits. writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. if enabled, these interrupt bits are cascaded into the gpio interrupt event (gpio) bit of the interrupt status register (int_sts) . writing a 1 to any of the interrupt enable bits will enable the corresponding interrupt as a so urce. status bits will still reflect the status of the int er- rupt source regardless of whether the source is enabled as an interrupt in this register. the gpio interrupt event enable (gpio_en) bit of the interrupt enable register (int_en) must also be set in order for an actual system level interrupt to occur. refer to section 8.0, "system interrupts," on page 67 for additional information. offset: 1e8h size: 32 bits bits description type default 31:24 reserved ro - 23:16 gpio interrupt enable[7 :0] (gpio[7:0]_int_en) when set, these bits enable the corresponding gpio interrupt. note: the gpio interrupts must also be enabled via the gpio interrupt event enable (gpio_en) bit of the interrupt enable register (int_en) in order to cause the interrupt pin ( irq ) to be asserted. r/w 00h 15:8 reserved ro - 7:0 gpio interrupt[7:0] (gpio[7:0]_int) these signals reflect the interrupt stat us as generated by the gpios. these interrupts are configured through the general purpose i/o configuration register (gpio_cfg) . note: as gpio interrupts, gpio inputs are level sensitive and must be active greater than 40 ns to be recognized as interrupt inputs. r/wc 00h
LAN9354 ds00001926b-page 460 ? 2015 microchip technology inc. 18.0 miscellaneous this chapter describes miscellaneous functions an d registers that are present in the device. 18.1 miscellaneous system configuration & status registers this section details the remainder of the directly addre ssable system csrs. these registers allow for monitoring and configuration of various device functions such as the chip id/revision, byte order testi ng, and hardware configuration. for an overview of the entire directly addressable register map, refer to section 5.0, "register map," on page 29 . table 18-1: miscellaneous registers address register name (symbol) 050h chip id and revision (id_rev) 064h byte order test register (byte_test) 074h hardware configuration register (hw_cfg)
? 2015 microchip technology inc. ds00001926b-page 461 LAN9354 18.1.1 chip id and revision (id_rev) this read-only register contains the id and revision fields for the device. note 1: default value is dependent on device revision. offset: 050h size: 32 bits bits description type default 31:16 chip id this field indicates the chip id. ro 9354 15:0 chip revision this field indicates the design revision. ro note 1
LAN9354 ds00001926b-page 462 ? 2015 microchip technology inc. 18.1.2 byte order test register (byte_test) this read-only register can be used to determine the byte ordering of the current configuration. for host interfaces that are disabled during the reset state, the byte_test register can be used to determine when the device has exited the reset state. note: this register can be read while the device is in the re set or not ready / power savings states without leaving the host interface in an intermediate state. if the ho st interface is in a reset state, returned data may be invalid. however, during reset, the returned data will not match the normal valid data pattern. note: it is not necessary to read all fours bytes of this r egister. dword access rules do not apply to this register. offset: 064h size: 32 bits bits description type default 31:0 byte test (byte_test) this field reflects the current byte ordering ro 87654321h
? 2015 microchip technology inc. ds00001926b-page 463 LAN9354 18.1.3 hardware configuration register (hw_cfg) this register allows the configuration of various hardware features. note: this register can be read while the device is in the re set or not ready / power savings states without leaving the host interface in an intermediate state. if the ho st interface is in a reset state, returned data may be invalid. note: it is not necessary to read all fours bytes of this r egister. dword access rules do not apply to this register. offset: 074h size: 32 bits bits description type default 31:28 reserved ro - 27 device ready (ready) when set, this bit indicates that the device is ready to be accessed. upon power-up, rst# reset, return from power savings states, or digital reset, the host processor may interrogate this fiel d as an indication that the device has stabilized and is fully active. this rising edge of this bit will assert the device ready (ready) bit in the interrupt status register (int_sts) and can cause an interrupt if enabled. note: with the exception of the hw_cfg, pmt_ctrl, byte_test, and reset_ctl registers, read access to any internal resources is forbidden while the ready bit is cleared. writes to any address are invalid until this bit is set. note: this bit is identical to bit 0 of the power management control register (pmt_ctrl) . ro 0b 26 amdix_en strap state port b this bit reflects the state of the aut o_mdix_strap_2 strap that connects to the phy. the strap value is loaded with the level of the auto_mdix_strap_2 during reset and can be re-written by the eeprom loader. the strap value can be overridden by bit 15 and 13 of the port b phy x special control/sta- tus indication register (phy_special_control_stat_ind_x) phy spe- cial control/status indication register. ro note 2 25 amdix_en strap state port a this bit reflects the state of the aut o_mdix_strap_1 strap that connects to the phy. the strap value is loaded with the level of the auto_mdix_strap_1 during reset and can be re-written by the eeprom loader. the strap value can be overridden by bit 15 and 13 of the port a phy x special control/sta- tus indication register (phy_special_control_stat_ind_x) . ro note 3 24:22 reserved ro - 21:16 reserved ro - 15:14 reserved ro - 13:12 reserved ro - 11:0 reserved ro -
LAN9354 ds00001926b-page 464 ? 2015 microchip technology inc. note 2: the default value of this field is de termined by the configuration strap auto_mdix_strap_2 . see section 6.3, "power management," on page 45 for more information. note 3: the default value of this field is de termined by the configuration strap auto_mdix_strap_1 . see section 6.3, "power management," on page 45 for more information.
? 2015 microchip technology inc. ds00001926b-page 465 LAN9354 19.0 jtag 19.1 jtag a ieee 1149.1 compliant tap controller suppor ts boundary scan and various test modes. the device includes an integrated jtag boundary-scan test por t for board-level testing. the interface consists of four pins ( tdo , tdi , tck and tms ) and includes a state machine, data register array, and an instruction register. the jtag pins are described in table 3-10, ?jtag pin descriptions,? on page 25 . the jtag interface conforms to the ieee stan- dard 1149.1 - 2001 standard test access port (tap) and boundary-scan architecture . all input and output data is synchronous to the tck test clock input. tap input signals tms and tdi are clocked into the test logic on the rising edge of tck , while the output signal tdo is clocked on the falling edge. jtag pins are multiplexed with th e gpio/led and eeprom pins. the jtag functionality is selected when the test- mode pin is asserted. the implemented ieee 1149.1 instructions and their op codes are shown in ta b l e 1 9 - 1 . note: the jtag device id is 00131445h note: all digital i/o pins support ieee 1149.1 operation. analog pins and the osci / osco pins do not support ieee 1149.1 operation. table 19-1: ieee 1149.1 op codes instruction op code comment bypass 0 16'h0000 mandatory instruction bypass 1 16'hffff mandatory instruction sample/preload 16'hfff8 mandatory instruction extest 16'hffe8 mandatory instruction clamp 16'hffef optional instruction id_code 16'hfffe optional instruction highz 16'hffcf optional instruction int_dr_sel 16'hfffd private instruction
LAN9354 ds00001926b-page 466 ? 2015 microchip technology inc. 19.1.1 jtag timing requirements this section specifies the jtag timing of the device. note: timing values are with respect to an equivalent test load of 25 pf. figure 19-1: jtag timing table 19-2: jtag timing values symbol description min max units notes t tckp tck clock period 40 ns t tckhl tck clock high/low time t tckp *0.4 t tckp *0.6 ns t su tdi , tms setup to tck rising edge 5 ns t h tdi , tms hold from tck rising edge 5 ns t dov tdo output valid from tck falling edge 15 ns t doinvld tdo output invalid from tck falling edge 0 ns tck (input) tdi , tms (inputs) t tckhl t tckp t tckhl t su t h t dov tdo (output) t doinvld
? 2015 microchip technology inc. ds00001926b-page 467 LAN9354 20.0 operational characteristics 20.1 absolute maximum ratings* supply voltage ( vdd12tx1 , vdd12tx2 , oscvdd12 , vddcr ) ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +1.5 v supply voltage ( vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 , vddio ) ( note 1 ) . . . . . . . . . . . . . 0 v to +3.6 v ethernet magnetics supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to +3.6 v positive voltage on input signal pins, with respect to ground ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . vddio + 2.0 v negative voltage on input signal pins, with respect to ground ( note 3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v positive voltage on osci , with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.6 v storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c lead temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 hbm esd performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . jedec class 3a note 1: when powering this device from laboratory or system powe r supplies, it is important that the absolute max- imum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exis ts, it is suggested to use a clamp circuit. note 2: this rating does not apply to the following pins: osci , rbias note 3: this rating does not apply to the following pins: rbias *stresses exceeding those listed in th is section could cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condition exceeding those indicated in section 20.2, "operating conditions**" , section 20.5, "dc specifications" , or any other applicable section of this specif ication is not implied. note, device signals are not 5 volt tolerant. 20.2 operating conditions** supply voltage ( vdd12tx1 , vdd12tx2 , oscvdd12 , vddcr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14 v to +1.26 v analog port supply voltage ( vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 ) . . . . . . . . . . . . . . . +3.0 v to +3.6 v i/o supply voltage ( vddio ) ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.62 v to +3.6 v ethernet magnetics supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25 v to +3.6 v ambient operating temperature in still air (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 4 note 4: 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version. **proper operation of the device is guar anteed only within the ranges specified in this section. after the device has com- pleted power-up, vddio and the magnetics power supply must maintain their voltage level with 10%. varying the volt- age greater than 10% after the device has completed power-up can cause errors in device operation. note: do not drive input signals without power supplied to the device.
LAN9354 ds00001926b-page 468 ? 2015 microchip technology inc. 20.3 package thermal specifications note: thermal parameters are measured or estimated fo r devices in a multi-layer 2s2p pcb per jesdn51. 20.4 current consumption and power consumption this section details t he device?s typical supply cu rrent consumption and power di ssipation for 10base-t, 100base-tx and power management modes of operation with the internal regulator enabled and disabled. table 20-1: 56-pin qfn package thermal parameters parameter symbol value units comments thermal resistance junction to ambient ? ja 24.7 c/w measured in still air thermal resistance junction to bottom of case ? jt 0.1 c/w measured in still air thermal resistance junction to top of case ? jc 1.8 c/w airflow 1 m/s table 20-2: maximum power dissipation mode maximum power (mw) internal regulator disabled , 2.5 v ethernet magnetics 752 internal regulator disabled , 3.3 v ethernet magnetics 927 internal regulator enabled, 2.5 v ethernet magnetics 973 internal regulator enabled, 3.3 v ethernet magnetics 1148 note: each mode in the current consumption and power dissipation tables assumes all phys are in the corre- sponding mode of operation.
? 2015 microchip technology inc. ds00001926b-page 469 LAN9354 20.4.1 internal regulator disabled table 20-3: current consumption and po wer dissipation (regs. disabled) 3.3 v device current (ma) (a) note 5 , note 7 1.2 v device current (ma) (b) note 6 , note 7 tx magnetics current (ma) (c) note 8 device power with 2.5 v magnetics (mw) note 9 , note 10 device power with 3.3 v magnetics (mw) note 9 , note 11 reset ( rst#) typ. 23.7 29.0 0.0 113 113 d0, 100base-tx with traffic (no eee) typ. 60.3 75.1 81.0 492 557 d0, 100base-tx idle (w/o eee) typ. 60.4 71.0 81.0 487 552 d0, 100base-tx idle (with eee) typ. 58.2 59.1 0.0 263 263 d0, 10base-t with traffic typ. 22.9 57.0 198.0 639 798 d0, 10base-t idle typ. 22.8 54.1 198.0 636 794 d0, phy energy detect power down typ. 12.3 50.6 0.0 102 102 d0, phy general power down typ. 5.4 51.1 0.0 80 80 d1, 100base-tx idle (w/o eee) typ. 59.3 41.3 81.0 448 513 d1, 100base-tx idle (with eee) typ. 54.6 29.8 0.0 216 216 d1, 10base-t idle typ. 19.1 23.9 198.0 587 746 d1, phy energy detect power down typ. 8.8 17.9 0.0 50.5 50.5 d1, phy general power down typ. 1.5 18.3 0.0 27 27 d2, 100base-tx idle (w/o eee) typ. 56.8 41.4 81.0 440 505 d2, 100base-tx idle (with eee) typ. 54.6 30.0 0.0 217 217 d2, 10base-t idle typ. 19.1 24.0 198.0 587 746
LAN9354 ds00001926b-page 470 ? 2015 microchip technology inc. note 5: vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 , vddio note 6: vdd12tx1 , vdd12tx2 , oscvdd12 , vddcr note 7: current measurements do not include power applied to the magnetics or the optional external leds. note 8: the ethernet component current is ind ependent of the supply rail voltage (2.5v or 3.3v) of the transformer. two internal phy copper tp operation is assumed. current is half if onl y one phy is enabled or if one phy is using 100base-fx mode. current is zero if neither phy is enabled or if both phys are using 100base- fx mode. note 9: this includes the power dissipated by the transmit ter by way of the current through the transformer. note 10: 3.3*(a) + 1.2*(b) + (2.5)*(c) @ typ note 11: 3.3*(a) + 1.2*(b) + (3.3)*(c) @ typ 20.4.2 internal regulator enabled d2, phy energy detect power down typ. 8.7 6.5 0.0 37 37 d2, phy general power down typ. 1.5 6.9 0.0 14 14 d3, phy general power down typ. 1.5 3.5 0.0 10 10 table 20-4: current consumption and power dissipation (regs. enabled) 3.3 v device current (ma) (a) note 12 , note 13 , note 14 tx magnetics current (ma) (c) note 15 device power with 2.5 v magnetics (mw) note 16 , note 17 device power with 3.3 v magnetics (mw) note 16 , note 18 reset ( rst#) typ. 54.0 0.0 179 179 d0, 100base-tx with traffic (no eee) typ. 136.9 81.0 655 720 d0, 100base-tx idle (w/o eee) typ. 132.8 81.0 641 706 d0, 100base-tx idle (with eee) typ. 118.1 0.0 390 390 d0, 10base-t with traffic typ. 80.5 198.0 761 920 d0, 10base-t idle typ. 77.0 198.0 750 908 d0, phy energy detect power down typ. 63.1 0.0 209 209 table 20-3: current consumption and po wer dissipation (regs. disabled)
? 2015 microchip technology inc. ds00001926b-page 471 LAN9354 note 12: vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 , vddio note 13: vdd12tx1 and vdd12tx2 , are driven by the internal regulator via the pcb. the current is accounted for via vdd33 . note 14: current measurements do not include power applied to the magnetics or the optional external leds. note 15: the ethernet component current is ind ependent of the supply rail voltage (2.5v or 3.3v) of the transformer. two internal phy copper tp operation is assumed. current is half if only one phy is enabled or if one phy is using 100base-fx mode. current is zero if neither phy is enabled or if both phys are using 100base- fx mode. note 16: this includes the power dissipated by the transmit ter by way of the current through the transformer. note 17: 3.3*(a) + (2.5)*(c) @ typ note 18: 3.3*(a) + (3.3)*(c) @ typ d0, phy general power down typ. 56.8 0.0 188 188 d1, 100base-tx idle (w/o eee) typ. 99.2 81.0 530 595 d1, 100base-tx idle (with eee) typ. 84.8 0.0 280 280 d1, 10base-t idle typ. 43.6 198.0 639 798 d1, phy energy detect power down typ. 26.2 0.0 87 87 d1, phy general power down typ. 19.2 0.0 64 64 d2, 100base-tx idle (w/o eee) typ. 99.2 81.0 530 595 d2, 100base-tx idle (with eee) typ. 84.9 0.0 281 281 d2, 10base-t idle typ. 43.8 198.0 640 798 d2, phy energy detect power down typ. 14.8 0.0 49 49 d2, phy general power down typ. 8.0 0.0 27 27 d3, phy general power down typ. 4.4 0.0 15 15 table 20-4: current consumption and power dissipation (regs. enabled)
LAN9354 ds00001926b-page 472 ? 2015 microchip technology inc. 20.5 dc specifications table 20-5: non-variable i/o dc electrical characteristics parameter symbol min typ max units notes is type input buffer low input level high input level schmitt trigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vdd33 ) input capacitance pull-up impedance (v in = vss ) pull-down impedance (v in = vdd33 ) v ili v ihi v hys i ih c in r dpu r dpd -0.3 2.0 121 -10 6 52 0.8 3.6 151 10 3 8.9 79 v v mv a pf k ? k ? note 19 ai type input buffer ( fxsdena/fxsdenb ) low input level high input level v il v ih -0.3 1.2 0.8 vdd33 +0.3 v v ai type input buffer ( rxpa/rxna/rxpb/rxnb) differential input level common mode voltage input capacitance v in-diff v cm c in 0.1 1.0 vdd33txrx x - 1.3 vdd33txrx x 5 v v pf ai type input buffer ( fxlosen input) state a threshold state b threshold state c threshold v tha v thb v thc -0.3 1.2 2.3 0.8 1.7 vdd33 + 0.3 v v v iclk type input buffer ( osci input) low input level high input level input leakage v ili v ihi i ilck -0.3 oscvdd12 -0.35 -10 0.35 3.6 10 v v a note 20
? 2015 microchip technology inc. ds00001926b-page 473 LAN9354 note 19: this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resis- tors add +/- 50 a per-pin (typical). note 20: osci can optionally be driven from a 25 mhz singled-ended clock oscillator. note 21: lvpecl compatible. note 22: v offset is a function of the external resistor network co nfiguration. the listed value is recommended to pre- vent issues due to crosstalk. ilvpecl input buffer low input level high input level v il - vdd33txrx x v ih - vdd33txrx x vdd33txrx x + 0.3 -1.14 -1.48 0.3 v v note 21 note 21 olvpecl output buffer low output level high output level peak-to-peak differential (sff mode) peak-to-peak differential (sfp mode) common mode voltage offset voltage load capacitance v ol v oh v diff-sff v diff-sfp v cm v offset c load vdd33txrx x - 1.025 1.2 0.6 1.0 1.6 0.8 vdd33txrx x - 1.3 40 vdd33txrx x - 1.62 2.0 1.0 10 v v v v v mv pf note 22 table 20-5: non-variable i/o dc electrical characteristics (continued) parameter symbol min typ max units notes
LAN9354 ds00001926b-page 474 ? 2015 microchip technology inc. table 20-6: variable i/o dc electrical characteristics parameter symbol min 1.8 v typ 3.3 v typ max units notes vis type input buffer low input level high input level negative-going threshold positive-going threshold schmitt trigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vddio ) input capacitance pull-up impedance (v in = vss ) pull-up current (v in = vss ) pull-down impedance (v in = vdd33 ) pull-down current (v in = vdd33 ) v ili v ihi v ilt v iht v hys i ih c in r dpu i dpu r dpd i dpd -0.3 0.64 0.81 102 -10 54 20 54 19 0.83 0.99 158 68 27 68 26 1.41 1.65 138 82 67 85 66 3.6 1.76 1.90 288 10 2 v v v v mv a pf k ? a k ? a schmitt trigger schmitt trigger note 23 vo8 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 v v i ol = 8 ma i oh = -8 ma vod8 type buffer low output level v ol 0.4 v i ol = 8 ma vo12 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 v v i ol = 12 ma i oh = -12 ma vod12 type buffer low output level v ol 0.4 v i ol = 12 ma vos12 type buffers high output level v oh vddio - 0.4 v i oh = -12 ma vo16 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 v v i ol = 16 ma i oh = -16 ma
? 2015 microchip technology inc. ds00001926b-page 475 LAN9354 note 23: this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resis- tors add 50 a per-pin (typical). note 24: measured at line side of transformer, line replaced by 100 ? (+/- 1%) resistor. note 25: offset from 16 ns pulse width at 50% of pulse peak. note 26: measured differentially. note 27: min/max voltages guaranteed as measured with 100 ? resistive load. table 20-7: 100base-tx transceiver characteristics parameter symbol min typ max units notes peak differential output voltage high v pph 950 - 1050 mvpk note 24 peak differential output voltage low v ppl -950 - -1050 mvpk note 24 signal amplitude symmetry v ss 98 - 102 % note 24 signal rise and fall time t rf 3.0 - 5.0 ns note 24 rise and fall symmetry t rfs --0.5ns note 24 duty cycle distortion d cd 35 50 65 % note 25 overshoot and undershoot v os --5% jitter - - - 1.4 ns note 26 table 20-8: 10base-t tran sceiver characteristics parameter symbol min typ max units notes transmitter peak differential output voltage v out 2.2 2.5 2.8 v note 27 receiver differential squelch threshold v ds 300 420 585 mv
LAN9354 ds00001926b-page 476 ? 2015 microchip technology inc. 20.6 ac specifications this section details the various ac timing specifications of the device. note: the i 2 c timing adheres to the nxp i 2 c-bus specification . refer to the nxp i 2 c-bus specification for detailed i 2 c timing information. note: the mii/smi timing adheres to the ieee 802.3 specification . note: the rmii timing adheres to the rmii consortium rmii specification r1.2 . 20.6.1 equivalent test load output timing specifications assume the 25 pf equivalent test load, unless otherwise noted, as illustrated in figure 20-1 . figure 20-1: output equivalent test load 25 pf output
? 2015 microchip technology inc. ds00001926b-page 477 LAN9354 20.6.2 power sequencing timing these diagrams illustrates the device power sequencing requirements. the vddio , vdd33 , vdd33txrx1 , vdd33txrx2 , vdd33bias and magnetics power supplies must all reach operational levels within the specified time period t pon . when operating with the internal regulators disabled, vddcr , oscvdd12 , vdd12tx1 and vdd12tx2 are also included into this requirement. in addition, once the vddio power supply reaches 1.0 v, it must reach 80% of its operating voltage level (1.44 v when operating at 1.8 v, 2.0 v when operating at 2.5 v, 2.64 v when operating at 3.3 v) within an additional 15ms. this requirement can be safely ignored if using an external reset as shown in section 20.6.3, "reset and configuration strap timing" . device power supplies can turn off in any order provided they all reach 0 volts within the specified time period t poff . figure 20-2: power sequence timing - internal regulators figure 20-3: power sequence timing - external regulators table 20-9: power sequencing timing values symbol description min typ max units t pon power supply turn on time - - 50 ms t poff power supply turn off time - - 500 ms vddio magnetics power t pon t poff vdd33 , vdd33bias , vdd33txrx1 , vdd33txrx2 vddio magnetics power t pon t poff vdd33 , vdd33bias , vdd33txrx1 , vdd33txrx2 vddcr , oscvdd12 , vdd12tx1 , vdd12tx2
LAN9354 ds00001926b-page 478 ? 2015 microchip technology inc. 20.6.3 reset and configuration strap timing this diagram illustrates the rst# pin timing requirements and its relation to the configuration strap pins and output drive. assertion of rst# is not a requi rement. however, if used, it must be asserted for the minimum period specified. the rst# pin can be asserted at any ti me, but must not be deasserted until t purstd after all external power supplies have reached operational levels. refer to section 6.2, "resets," on page 38 for additional information. note: the clock input must be stable prior to rst# deassertion. note: device configuration straps are latched as a result of rst# assertion. refer to section 6.2.1, "chip-level resets," on page 39 for details. note: configuration strap latching and output drive timings shown assume that the power-on reset has finished first otherwise the timings in section 20.6.4, "power-on and configuration strap timing" apply. figure 20-4: rst# pin configuration strap latching timing table 20-10: rst# pin configuration strap latching timing values symbol description min typ max units t purstd external power supplies at operational level to rst# deasser- tion 25 ms t rstia rst# input assertion time 200 - - ? s t css configuration strap pins setup to rst# deassertion 200 - - ns t csh configuration strap pins hold after rst# deassertion 10 - - ns t odad output drive after deassertion 3 - - us t css rst# configuration strap pins t rstia t csh output drive t odad ?? all external power supplies t purstd v opp
? 2015 microchip technology inc. ds00001926b-page 479 LAN9354 20.6.4 power-on and conf iguration strap timing this diagram illustrates the configurati on strap valid timing requirements in relation to power-on. in order for valid con- figuration strap values to be read at power-on, the following timing requirements must be met. note: configuration straps must only be pulled high or low. configuration straps must not be driven as inputs. device configuration straps are also latched as a result of rst# assertion. refer to section 20.6.3, "r eset and config- uration strap timing" and section 6.2.1, "chip-level resets," on page 39 for additional details. 20.6.5 smi slave controller i/o timing timing specifications for the smi slave controller are given in section 14.2.4, "smi timing requirements," on page 349 . 20.6.6 i 2 c slave controller i/o timing the i 2 c slave controller adheres to the philips i 2 c-bus specification . refer to the philips i 2 c-bus specification for detailed i 2 c timing information. refer to section 11.0, "i2c slave controller," on page 319 for additional information on the i 2 c slave controller. 20.6.7 phy management interface (pmi) i/o timing timing specifications for the phy ma nagement interface (pmi) are given in section 14.3.4, "pmi timing requirements," on page 351 . 20.6.8 physical phy external ma nagement access i/o timing timing specifications for physical phy external management access are given in section 9.2.19, "external pin access timing requirements," on page 101 . 20.6.9 virtual phy management access i/o timing timing specifications for virtual phy management access are given in section 9.3.4, "virtual phy timing require- ments," on page 165 . 20.6.10 i 2 c eeprom i/o timing timing specifications for i 2 c eeprom access are given in section 12.3, "i2c master eeprom controller," on page 325 . 20.6.11 mii / turbo mii / rmii i/o timing timing specifications for the mii / tur bo mii and rmii interfaces are given in section 13.4, "switch fabric timing requirements," on page 342 . 20.6.12 jtag timing timing specifications for the jtag interface are given in table 19.1.1, ?jtag timing requirements,? on page 466 . figure 20-5: power-on configura tion strap latching timing table 20-11: power-on configuration strap latching timing values symbol description min typ max units t cfg configuration strap valid time - - 15 ms all external power supplies configuration straps t cfg vopp
LAN9354 ds00001926b-page 480 ? 2015 microchip technology inc. 20.7 clock circuit the device can accept either a 25 mhz crystal or a 25 mhz si ngle-ended clock oscillator (50 ppm) input. if the single- ended clock oscillator method is implemented, osco should be left unconnected and osci should be driven with a clock signal that adheres to the specifications outlined throughout section 20.0, "operational characteristics" . see table 20-12 for the recommended crystal specifications. note 28: the maximum allowable values for frequency tolerance and frequency stability are application dependent. since any particular application must meet the ieee 50 ppm total ppm budge t, the combination of these two values must be approximately 45 ppm (allowing for aging). note 29: frequency deviation over time is also referred to as aging. note 30: the total deviation for 100base-tx is 50 ppm. note 31: the minimum drive level requirement p w is reduced to 100 uw with the addition of a 500 ? series resistor, if c o ? 5pf, c l ? 12 pf and r1 ? 80 ? note 32: 0 c for commercial version, -4 0 c for industrial version note 33: +70 c for commercial version, +85 c for industrial version note 34: this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the osci pin, osco pin and pcb capacitance values are required to accurately calculate the value of the two external load capacitors. the total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 mhz. table 20-12: crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz 802.3 frequency tolerance at 25 o c f tol - - 40 ppm note 28 802.3 frequency stability over te m p f temp - - 40 ppm note 28 802.3 frequency deviation over time f age - 3 to 5 - ppm note 29 802.3 total allowable ppm bud- get - - 50 ppm note 30 shunt capacitance c o --7pf load capacitance c l - - 18 pf drive level p w 300 note 31 --w equivalent series resistance r 1 --100 ? operating temperature range note 32 - note 33 o c osci pin capacitance - 3 typ - pf note 34 osco pin capacitance - 3 typ - pf note 34
? 2015 microchip technology inc. ds00001926b-page 481 LAN9354 21.0 package outlines 21.1 56-qfn figure 21-1: 56-qfn package
LAN9354 ds00001926b-page 482 ? 2015 microchip technology inc. figure 21-2: 56-qfn package dimensions
? 2015 microchip technology inc. ds00001926b-page 483 LAN9354 22.0 revision history table 22-1: revision history revision level section/figure/entry correction ds00001926b (08-06-15) figure 3-1: 56-qfn pin assignments (top view) on page 10 corrected pin 43 and 44 names. ds00001926a (06-30-15) initial release
LAN9354 ds00001926b-page 484 ? 2015 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep custom ers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support
? 2015 microchip technology inc. ds00001926b-page 485 LAN9354 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . device: LAN9354 tape and reel option: blank = standard packaging (tray) t = tape and reel ( note 1 ) temperature range: blank = 0 ? c to +70 ? c (commercial) i= -40 ? c to +85 ? c (industrial) package: ml = 56-pin qfn examples: a) LAN9354/ml standard packaging (tray), commercial temperature, 56-pin qfn b) LAN9354ti/ml tape and reel industrial temperature, 56-pin qfn note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. part no. device tape and reel option / temperature range xx [x] [x] package
LAN9354 ds00001926b-page 486 ? 2015 microchip technology inc. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breac h the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner ou tside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any othe r semiconductor manufacturer can guarantee the secu rity of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with y our specifications. microchip make s no representations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising fr om this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, i ndemnify and hold harmless microchip from any and all dama ges, claims, suits, or expenses resulting from such use. no licenses are conveyed, implic- itly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip l ogo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technol ogy incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technol ogy incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet l ogo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem .net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewsp an, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademar k of microchip technology inc. in other countries. gestic is a registered trademark of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., i n other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 9781632773388 microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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